From 98769010afc4a57f3ce8c359c1c6e88a864c5986 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 7 Jul 2023 15:27:21 +0200 Subject: [PATCH 01/39] synth_quicklogic: rearrange files to prepare for adding more architectures --- techlibs/quicklogic/Makefile.inc | 19 +++-- techlibs/quicklogic/{ => common}/cells_sim.v | 0 techlibs/quicklogic/lut_sim.v | 76 ------------------ techlibs/quicklogic/{ => pp3}/abc9_map.v | 0 techlibs/quicklogic/{ => pp3}/abc9_model.v | 0 techlibs/quicklogic/{ => pp3}/abc9_unmap.v | 0 .../{pp3_cells_map.v => pp3/cells_map.v} | 0 .../{pp3_cells_sim.v => pp3/cells_sim.v} | 77 +++++++++++++++++++ .../{pp3_ffs_map.v => pp3/ffs_map.v} | 0 .../{pp3_latches_map.v => pp3/latches_map.v} | 0 .../{pp3_lut_map.v => pp3/lut_map.v} | 0 techlibs/quicklogic/synth_quicklogic.cc | 50 +++++++++--- tests/arch/quicklogic/add_sub.ys | 2 +- tests/arch/quicklogic/adffs.ys | 8 +- tests/arch/quicklogic/counter.ys | 2 +- tests/arch/quicklogic/dffs.ys | 4 +- tests/arch/quicklogic/fsm.ys | 2 +- tests/arch/quicklogic/logic.ys | 2 +- tests/arch/quicklogic/mux.ys | 8 +- tests/arch/quicklogic/tribuf.ys | 2 +- 20 files changed, 139 insertions(+), 113 deletions(-) rename techlibs/quicklogic/{ => common}/cells_sim.v (100%) delete mode 100644 techlibs/quicklogic/lut_sim.v rename techlibs/quicklogic/{ => pp3}/abc9_map.v (100%) rename techlibs/quicklogic/{ => pp3}/abc9_model.v (100%) rename techlibs/quicklogic/{ => pp3}/abc9_unmap.v (100%) rename techlibs/quicklogic/{pp3_cells_map.v => pp3/cells_map.v} (100%) rename techlibs/quicklogic/{pp3_cells_sim.v => pp3/cells_sim.v} (76%) rename techlibs/quicklogic/{pp3_ffs_map.v => pp3/ffs_map.v} (100%) rename techlibs/quicklogic/{pp3_latches_map.v => pp3/latches_map.v} (100%) rename techlibs/quicklogic/{pp3_lut_map.v => pp3/lut_map.v} (100%) diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 51eb28d44bd..43d8fdf7990 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,13 +1,12 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_ffs_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_lut_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_latches_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/lut_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/pp3_cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_model.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_map.v)) -$(eval $(call add_share_file,share/quicklogic,techlibs/quicklogic/abc9_unmap.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/lut_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/latches_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v)) +$(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v)) diff --git a/techlibs/quicklogic/cells_sim.v b/techlibs/quicklogic/common/cells_sim.v similarity index 100% rename from techlibs/quicklogic/cells_sim.v rename to techlibs/quicklogic/common/cells_sim.v diff --git a/techlibs/quicklogic/lut_sim.v b/techlibs/quicklogic/lut_sim.v deleted file mode 100644 index 851ce4d6845..00000000000 --- a/techlibs/quicklogic/lut_sim.v +++ /dev/null @@ -1,76 +0,0 @@ -(* abc9_lut=1, lib_whitebox *) -module LUT1 ( - output O, - input I0 -); - parameter [1:0] INIT = 0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 698; // FS -> FZ - endspecify - - assign O = I0 ? INIT[1] : INIT[0]; -endmodule - -// TZ TSL TAB -(* abc9_lut=2, lib_whitebox *) -module LUT2 ( - output O, - input I0, I1 -); - parameter [3:0] INIT = 4'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 1251; // TAB -> TZ - (I1 => O) = 1406; // TSL -> TZ - endspecify - - wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -(* abc9_lut=2, lib_whitebox *) -module LUT3 ( - output O, - input I0, I1, I2 -); - parameter [7:0] INIT = 8'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 1251; // TAB -> TZ - (I1 => O) = 1406; // TSL -> TZ - (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ - endspecify - - wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule - -(* abc9_lut=4, lib_whitebox *) -module LUT4 ( - output O, - input I0, I1, I2, I3 -); - parameter [15:0] INIT = 16'h0; - parameter EQN = "(I0)"; - - // These timings are for PolarPro 3E; other families will need updating. - specify - (I0 => O) = 995; // TBS -> CZ - (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ - (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ - (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ - endspecify - - wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; - wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; - wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; - assign O = I0 ? s1[1] : s1[0]; -endmodule diff --git a/techlibs/quicklogic/abc9_map.v b/techlibs/quicklogic/pp3/abc9_map.v similarity index 100% rename from techlibs/quicklogic/abc9_map.v rename to techlibs/quicklogic/pp3/abc9_map.v diff --git a/techlibs/quicklogic/abc9_model.v b/techlibs/quicklogic/pp3/abc9_model.v similarity index 100% rename from techlibs/quicklogic/abc9_model.v rename to techlibs/quicklogic/pp3/abc9_model.v diff --git a/techlibs/quicklogic/abc9_unmap.v b/techlibs/quicklogic/pp3/abc9_unmap.v similarity index 100% rename from techlibs/quicklogic/abc9_unmap.v rename to techlibs/quicklogic/pp3/abc9_unmap.v diff --git a/techlibs/quicklogic/pp3_cells_map.v b/techlibs/quicklogic/pp3/cells_map.v similarity index 100% rename from techlibs/quicklogic/pp3_cells_map.v rename to techlibs/quicklogic/pp3/cells_map.v diff --git a/techlibs/quicklogic/pp3_cells_sim.v b/techlibs/quicklogic/pp3/cells_sim.v similarity index 76% rename from techlibs/quicklogic/pp3_cells_sim.v rename to techlibs/quicklogic/pp3/cells_sim.v index 5820d7a9ec0..201a7d33331 100644 --- a/techlibs/quicklogic/pp3_cells_sim.v +++ b/techlibs/quicklogic/pp3/cells_sim.v @@ -327,3 +327,80 @@ module qlal4s3b_cell_macro ( ); endmodule + +(* abc9_lut=1, lib_whitebox *) +module LUT1 ( + output O, + input I0 +); + parameter [1:0] INIT = 0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 698; // FS -> FZ + endspecify + + assign O = I0 ? INIT[1] : INIT[0]; +endmodule + +// TZ TSL TAB +(* abc9_lut=2, lib_whitebox *) +module LUT2 ( + output O, + input I0, I1 +); + parameter [3:0] INIT = 4'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 1251; // TAB -> TZ + (I1 => O) = 1406; // TSL -> TZ + endspecify + + wire [1:0] s1 = I1 ? INIT[3:2] : INIT[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +(* abc9_lut=2, lib_whitebox *) +module LUT3 ( + output O, + input I0, I1, I2 +); + parameter [7:0] INIT = 8'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 1251; // TAB -> TZ + (I1 => O) = 1406; // TSL -> TZ + (I2 => O) = 1699; // ('TA1', 'TA2', 'TB1', 'TB2') -> TZ + endspecify + + wire [3:0] s2 = I2 ? INIT[7:4] : INIT[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule + +(* abc9_lut=4, lib_whitebox *) +module LUT4 ( + output O, + input I0, I1, I2, I3 +); + parameter [15:0] INIT = 16'h0; + parameter EQN = "(I0)"; + + // These timings are for PolarPro 3E; other families will need updating. + specify + (I0 => O) = 995; // TBS -> CZ + (I1 => O) = 1437; // ('TAB', 'BAB') -> CZ + (I2 => O) = 1593; // ('TSL', 'BSL') -> CZ + (I3 => O) = 1887; // ('TA1', 'TA2', 'TB1', 'TB2', 'BA1', 'BA2', 'BB1', 'BB2') -> CZ + endspecify + + wire [7:0] s3 = I3 ? INIT[15:8] : INIT[7:0]; + wire [3:0] s2 = I2 ? s3[7:4] : s3[3:0]; + wire [1:0] s1 = I1 ? s2[3:2] : s2[1:0]; + assign O = I0 ? s1[1] : s1[0]; +endmodule diff --git a/techlibs/quicklogic/pp3_ffs_map.v b/techlibs/quicklogic/pp3/ffs_map.v similarity index 100% rename from techlibs/quicklogic/pp3_ffs_map.v rename to techlibs/quicklogic/pp3/ffs_map.v diff --git a/techlibs/quicklogic/pp3_latches_map.v b/techlibs/quicklogic/pp3/latches_map.v similarity index 100% rename from techlibs/quicklogic/pp3_latches_map.v rename to techlibs/quicklogic/pp3/latches_map.v diff --git a/techlibs/quicklogic/pp3_lut_map.v b/techlibs/quicklogic/pp3/lut_map.v similarity index 100% rename from techlibs/quicklogic/pp3_lut_map.v rename to techlibs/quicklogic/pp3/lut_map.v diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 94bd44db008..7fddbc97078 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -60,13 +60,14 @@ struct SynthQuickLogicPass : public ScriptPass { log("\n"); } - string top_opt, blif_file, family, currmodule, verilog_file; + string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; bool abc9; void clear_flags() override { top_opt = "-auto-top"; blif_file = ""; + edif_file = ""; verilog_file = ""; currmodule = ""; family = "pp3"; @@ -81,6 +82,14 @@ struct SynthQuickLogicPass : public ScriptPass { size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-run" && argidx+1 < args.size()) { + size_t pos = args[argidx+1].find(':'); + if (pos == std::string::npos) + break; + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos+1); + continue; + } if (args[argidx] == "-top" && argidx+1 < args.size()) { top_opt = "-top " + args[++argidx]; continue; @@ -93,6 +102,10 @@ struct SynthQuickLogicPass : public ScriptPass { blif_file = args[++argidx]; continue; } + if (args[argidx] == "-edif" && argidx + 1 < args.size()) { + edif_file = args[++argidx]; + continue; + } if (args[argidx] == "-verilog" && argidx+1 < args.size()) { verilog_file = args[++argidx]; continue; @@ -126,13 +139,16 @@ struct SynthQuickLogicPass : public ScriptPass { void script() override { + if (help_mode) { + family = ""; + } + if (check_label("begin")) { - run(stringf("read_verilog -lib -specify +/quicklogic/cells_sim.v +/quicklogic/%s_cells_sim.v", family.c_str())); - run("read_verilog -lib -specify +/quicklogic/lut_sim.v"); + run(stringf("read_verilog -lib -specify +/quicklogic/common/cells_sim.v +/quicklogic/%s/cells_sim.v", family.c_str())); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } - if (check_label("coarse")) { + if (check_label("prepare")) { run("proc"); run("flatten"); run("tribuf -logic"); @@ -147,6 +163,9 @@ struct SynthQuickLogicPass : public ScriptPass { run("peepopt"); run("opt_clean"); run("share"); + } + + if (check_label("coarse")) { run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); run("opt_clean"); @@ -175,18 +194,18 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_expr"); run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); - run(stringf("techmap -map +/quicklogic/%s_cells_map.v -map +/quicklogic/%s_ffs_map.v", family.c_str(), family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/cells_map.v -map +/quicklogic/%s/ffs_map.v", family.c_str(), family.c_str())); run("opt_expr -mux_undef"); } if (check_label("map_luts")) { - run(stringf("techmap -map +/quicklogic/%s_latches_map.v", family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/latches_map.v", family.c_str())); if (abc9) { - run("read_verilog -lib -specify -icells +/quicklogic/abc9_model.v"); - run("techmap -map +/quicklogic/abc9_map.v"); + run(stringf("read_verilog -lib -specify -icells +/quicklogic/%s/abc9_model.v", family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/abc9_map.v", family.c_str())); run("abc9 -maxlut 4 -dff"); - run("techmap -map +/quicklogic/abc9_unmap.v"); + run(stringf("techmap -map +/quicklogic/%s/abc9_unmap.v", family.c_str())); } else { run("abc -luts 1,2,2,4 -dress"); } @@ -194,7 +213,7 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_cells")) { - run(stringf("techmap -map +/quicklogic/%s_lut_map.v", family.c_str())); + run(stringf("techmap -map +/quicklogic/%s/lut_map.v", family.c_str())); run("clean"); } @@ -218,17 +237,24 @@ struct SynthQuickLogicPass : public ScriptPass { run("blackbox =A:whitebox"); } - if (check_label("blif")) { + if (check_label("blif", "(if -blif)")) { if (!blif_file.empty() || help_mode) { run(stringf("write_blif -attr -param %s %s", top_opt.c_str(), blif_file.c_str())); } } - if (check_label("verilog")) { + if (check_label("verilog", "(if -verilog)")) { if (!verilog_file.empty() || help_mode) { run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); } } + + if (check_label("edif", "(if -edif)")) { + if (!edif_file.empty() || help_mode) { + run("splitnets -ports -format ()"); + run(stringf("write_edif -nogndvcc -attrprop -pvector par %s %s", top_opt.c_str(), edif_file.c_str())); + } + } } } SynthQuicklogicPass; diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/add_sub.ys index 73ee5cb4413..47db42afc9a 100644 --- a/tests/arch/quicklogic/add_sub.ys +++ b/tests/arch/quicklogic/add_sub.ys @@ -1,6 +1,6 @@ read_verilog ../common/add_sub.v hierarchy -top top -equiv_opt -assert -map +/quicklogic/lut_sim.v -map +/quicklogic/pp3_cells_sim.v synth_quicklogic -family pp3 # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 2 t:LUT2 diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/adffs.ys index 41a17584427..43f36c20cb5 100644 --- a/tests/arch/quicklogic/adffs.ys +++ b/tests/arch/quicklogic/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:dffepc @@ -19,7 +19,7 @@ select -assert-none t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad %% t:* design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 @@ -36,7 +36,7 @@ select -assert-none t:LUT1 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:LUT2 @@ -53,7 +53,7 @@ select -assert-none t:LUT2 t:dffepc t:logic_0 t:logic_1 t:inpad t:outpad t:ckpad design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/counter.ys index 2e266417caf..9a7dcdf0809 100644 --- a/tests/arch/quicklogic/counter.ys +++ b/tests/arch/quicklogic/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -assert -multiclock -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -multiclock -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/dffs.ys index e1fbef635d8..2bcfbf672de 100644 --- a/tests/arch/quicklogic/dffs.ys +++ b/tests/arch/quicklogic/dffs.ys @@ -5,7 +5,7 @@ design -save read hierarchy -top my_dff proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dff # Constrain all select calls below inside the top module select -assert-count 1 t:ckpad @@ -20,7 +20,7 @@ select -assert-none t:ckpad t:dffepc t:inpad t:logic_0 t:logic_1 t:outpad %% t:* design -load read hierarchy -top my_dffe proc -equiv_opt -async2sync -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v synth_quicklogic # equivalency check +equiv_opt -async2sync -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd my_dffe # Constrain all select calls below inside the top module diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/fsm.ys index 130dacf42a9..50dcb71b142 100644 --- a/tests/arch/quicklogic/fsm.ys +++ b/tests/arch/quicklogic/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic +equiv_opt -run :prove -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic async2sync miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/logic.ys index 4b327c00af7..9c34ddaeb3d 100644 --- a/tests/arch/quicklogic/logic.ys +++ b/tests/arch/quicklogic/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/mux.ys index ea17fa99b3d..5214bb7872d 100644 --- a/tests/arch/quicklogic/mux.ys +++ b/tests/arch/quicklogic/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 @@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 3 t:LUT3 @@ -27,7 +27,7 @@ select -assert-none t:LUT3 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 @@ -41,7 +41,7 @@ select -assert-none t:LUT1 t:LUT3 t:mux4x0 t:inpad t:outpad %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/quicklogic/lut_sim.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT3 diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/tribuf.ys index de763009eaf..d74fbbcdd2a 100644 --- a/tests/arch/quicklogic/tribuf.ys +++ b/tests/arch/quicklogic/tribuf.ys @@ -4,7 +4,7 @@ proc tribuf flatten synth -equiv_opt -assert -map +/quicklogic/pp3_cells_sim.v -map +/quicklogic/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check +equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v -map +/simcells.v synth_quicklogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module select -assert-count 2 t:inpad From 48c1fdc33d2fbe4659052376746a2942bc32f0e6 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 27 Nov 2023 09:42:40 +0100 Subject: [PATCH 02/39] add qlf_k6n10f architecture + bram inference (Copied from QuickLogic Yosys plugin repo) --- techlibs/quicklogic/Makefile.inc | 12 + techlibs/quicklogic/ql-bram-merge.cc | 216 + techlibs/quicklogic/qlf_k6n10f/arith_map.v | 99 + .../quicklogic/qlf_k6n10f/bram_types_sim.v | 73373 ++++++++++++++++ .../quicklogic/qlf_k6n10f/brams_final_map.v | 1464 + techlibs/quicklogic/qlf_k6n10f/brams_map.v | 2839 + techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 11081 +++ techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 376 + techlibs/quicklogic/qlf_k6n10f/ffs_map.v | 133 + .../quicklogic/qlf_k6n10f/libmap_brams.txt | 22 + .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 457 + techlibs/quicklogic/quicklogic_eqn.cc | 100 + techlibs/quicklogic/synth_quicklogic.cc | 187 +- 13 files changed, 90338 insertions(+), 21 deletions(-) create mode 100644 techlibs/quicklogic/ql-bram-merge.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/arith_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_final_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_sim.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/cells_sim.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/ffs_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt create mode 100644 techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v create mode 100644 techlibs/quicklogic/quicklogic_eqn.cc diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 43d8fdf7990..fcc49cd77f8 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,4 +1,6 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o +OBJS += techlibs/quicklogic/ql-bram-merge.o +OBJS += techlibs/quicklogic/quicklogic_eqn.o $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) @@ -10,3 +12,13 @@ $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/cells_ $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_model.v)) $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_map.v)) $(eval $(call add_share_file,share/quicklogic/pp3,techlibs/quicklogic/pp3/abc9_unmap.v)) + +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/arith_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_final_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql-bram-merge.cc new file mode 100644 index 00000000000..d64bd64cf60 --- /dev/null +++ b/techlibs/quicklogic/ql-bram-merge.cc @@ -0,0 +1,216 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + + +struct QlBramMergeWorker { + + const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); + const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); + + // can be used to record parameter values that have to match on both sides + typedef dict MergeableGroupKeyType; + + RTLIL::Module *module; + dict> mergeable_groups; + + QlBramMergeWorker(RTLIL::Module* module) : module(module) + { + for (RTLIL::Cell* cell : module->selected_cells()) + { + if(cell->type != split_cell_type) continue; + if(!cell->hasParam(ID(OPTION_SPLIT))) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + mergeable_groups[get_key(cell)].insert(cell); + } + } + + static MergeableGroupKeyType get_key(RTLIL::Cell* cell) + { + MergeableGroupKeyType key; + // For now, there are no restrictions on which cells can be merged + (void) cell; + return key; + } + + const dict& param_map(bool second) + { + static const dict bram1_map = { + { ID(INIT), ID(INIT1) }, + { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } + }; + static const dict bram2_map = { + { ID(INIT), ID(INIT2) }, + { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + const dict& port_map(bool second) + { + static const dict bram1_map = { + { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } + }; + static const dict bram2_map = { + { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) + { + + // Create the new cell + RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); + + for (auto &it : param_map(false)) + { + if(bram1->hasParam(it.first)) + merged->setParam(it.second, bram1->getParam(it.first)); + } + for (auto &it : param_map(true)) + { + if(bram2->hasParam(it.first)) + merged->setParam(it.second, bram2->getParam(it.first)); + } + + for (auto &it : port_map(false)) + { + if (bram1->hasPort(it.first)) + merged->setPort(it.second, bram1->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); + } + for (auto &it : port_map(true)) + { + if (bram2->hasPort(it.first)) + merged->setPort(it.second, bram2->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); + } + merged->attributes = bram1->attributes; + for (auto attr: bram2->attributes) + if (!merged->has_attribute(attr.first)) + merged->attributes.insert(attr); + + // Remove the old cells + module->remove(bram1); + module->remove(bram2); + + } + + void merge_bram_groups() + { + for (auto &it : mergeable_groups) + { + while (it.second.size() > 1) + { + merge_brams(it.second.pop(), it.second.pop()); + } + } + } + +}; + +struct QlBramMergePass : public Pass { + + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_merge [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); + log(" into a TDP36K cell operating in split mode\n"); + log("\n"); + } + + + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_MERGE pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + { + QlBramMergeWorker worker(module); + worker.merge_bram_groups(); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/techlibs/quicklogic/qlf_k6n10f/arith_map.v new file mode 100644 index 00000000000..908b17189c5 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/arith_map.v @@ -0,0 +1,99 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 2; + parameter B_WIDTH = 2; + parameter Y_WIDTH = 2; + parameter _TECHMAP_CONSTVAL_CI_ = 0; + parameter _TECHMAP_CONSTMSK_CI_ = 0; + + (* force_downto *) + input [A_WIDTH-1:0] A; + (* force_downto *) + input [B_WIDTH-1:0] B; + (* force_downto *) + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + (* force_downto *) + output [Y_WIDTH-1:0] CO; + + + wire _TECHMAP_FAIL_ = Y_WIDTH <= 2; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + + genvar i; + wire co; + + (* force_downto *) + //wire [Y_WIDTH-1:0] C = {CO, CI}; + wire [Y_WIDTH:0] C; + (* force_downto *) + wire [Y_WIDTH-1:0] S = {AA ^ BB}; + assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1]; + //assign CO[Y_WIDTH-1] = co; + + generate + adder_carry intermediate_adder ( + .cin ( ), + .cout (C[0]), + .p (1'b0), + .g (CI), + .sumout () + ); + endgenerate + genvar i; + generate if (Y_WIDTH > 2) begin + for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice + adder_carry my_adder ( + .cin(C[i]), + .g(AA[i]), + .p(S[i]), + .cout(C[i+1]), + .sumout(Y[i]) + ); + end + end endgenerate + generate + adder_carry final_adder ( + .cin (C[Y_WIDTH-2]), + .cout (), + .p (1'b0), + .g (1'b0), + .sumout (co) + ); + endgenerate + + assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co; + assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; + assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1]; + assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; + + assign X = S; +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v new file mode 100644 index 00000000000..3a06f676d68 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v @@ -0,0 +1,73373 @@ +// **AUTOGENERATED FILE** **DO NOT EDIT** +// Generated by qlf_k6n10f/generate_bram_types_sim.py at 2023-05-02 10:42:53.971682+00:00 + +module TDP36K_BRAM_A_X1_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X1_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X2_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X4_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X1_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X2_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X4_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule + +module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v new file mode 100644 index 00000000000..7d04c5dda6c --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v @@ -0,0 +1,1464 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v new file mode 100644 index 00000000000..42e1fc98b85 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -0,0 +1,2839 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module RAM_36K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 36; +parameter RD_DATA_WIDTH = 36; +parameter BE_WIDTH = 4; + +parameter INIT = 0; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +32, 36: rwmode = 36; +default: rwmode = 36; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] WR_BE; + +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; + +wire [14:0] WR_ADDR_INT; +wire [14:0] RD_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + +localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); +localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + +assign PORT_A_CLK = WR_CLK_i; +assign PORT_B_CLK = RD_CLK_i; + +generate + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end +endgenerate + +case (WR_DATA_WIDTH) + 1: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = WR_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = WR_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = WR_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = WR_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = WR_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end +endcase + +generate + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end +endgenerate + +case (RD_DATA_WIDTH) + 1: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = RD_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = RD_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = RD_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = RD_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = RD_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end +endcase + +case (BE_WIDTH) + 4: begin + assign WR_BE = WR_BE_i[BE_WIDTH-1 :0]; + end + default: begin + assign WR_BE[3:BE_WIDTH] = 0; + assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN_i; +assign {BE_A2_i, BE_A1_i} = WR_BE; + +assign REN_B1_i = REN_i; +assign WEN_B1_i = 1'b0; +assign {BE_B2_i, BE_B1_i} = 4'h0; + +generate + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +assign WDATA_B1_i = 18'h0; +assign WDATA_B2_i = 18'h0; + +generate + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A_WRWIDTH *) +(* port_b_dwidth = PORT_B_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module RAM_18K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 18; +parameter RD_DATA_WIDTH = 18; +parameter BE_WIDTH = 2; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + + (* is_inferred = 0 *) + (* is_split = 0 *) + (* is_fifo = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + +endmodule + +module RAM_18K_X2_BLK ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* is_fifo = 0 *) +(* port_a1_dwidth = PORT_A1_WRWIDTH *) +(* port_a2_dwidth = PORT_A2_WRWIDTH *) +(* port_b1_dwidth = PORT_B1_WRWIDTH *) +(* port_b2_dwidth = PORT_B2_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input PORT_A_CLK_i; +input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input PORT_A_WEN_i; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input PORT_A_REN_i; +output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input PORT_B_CLK_i; +input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input PORT_B_WEN_i; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input PORT_B_REN_i; +output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +32, 36: rwmode = 36; +default: rwmode = 36; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] PORT_A_WR_BE; +wire [3:0] PORT_B_WR_BE; + +wire [35:0] PORT_B_WDATA; +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; +wire [35:0] PORT_A_RDATA; + +wire [14:0] PORT_A_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_DWIDTH); + +localparam PORT_A_WRWIDTH = rwmode(PORT_A_DWIDTH); +localparam PORT_B_WRWIDTH = rwmode(PORT_B_DWIDTH); + +assign PORT_A_CLK = PORT_A_CLK_i; +assign PORT_B_CLK = PORT_B_CLK_i; + +generate + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end +endgenerate + +case (PORT_A_DWIDTH) + 1: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end +endcase + +generate + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end +endgenerate + +case (PORT_B_DWIDTH) + 1: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end +endcase + +case (PORT_A_WR_BE_WIDTH) + 4: begin + assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0; + assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B_WR_BE_WIDTH) + 4: begin + assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0; + assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A_REN_i; +assign WEN_A1_i = PORT_A_WEN_i; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_REN_i; +assign WEN_B1_i = PORT_B_WEN_i; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end +endgenerate + +assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B_WDATA[17:0]; +assign WDATA_B2_i = PORT_B_WDATA[35:18]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A_WRWIDTH *) +(* port_b_dwidth = PORT_B_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input PORT_A_CLK_i; +input [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input PORT_A_WEN_i; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input PORT_A_REN_i; +output [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input PORT_B_CLK_i; +input [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input PORT_B_WEN_i; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input PORT_B_REN_i; +output [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +BRAM2x18_dP #( + .PORT_A1_AWIDTH(PORT_A_AWIDTH), + .PORT_A1_DWIDTH(PORT_A_DWIDTH), + .PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH), + .PORT_B1_AWIDTH(PORT_B_AWIDTH), + .PORT_B1_DWIDTH(PORT_B_DWIDTH), + .PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH), + .PORT_A2_AWIDTH(), + .PORT_A2_DWIDTH(), + .PORT_A2_WR_BE_WIDTH(), + .PORT_B2_AWIDTH(), + .PORT_B2_DWIDTH(), + .PORT_B2_WR_BE_WIDTH() +) U1 ( + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() +); + +endmodule + + +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* is_fifo = 0 *) +(* port_a1_dwidth = PORT_A1_WRWIDTH *) +(* port_a2_dwidth = PORT_A2_WRWIDTH *) +(* port_b1_dwidth = PORT_B1_WRWIDTH *) +(* port_b2_dwidth = PORT_B2_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module SFIFO_36K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + + + +endmodule + +module AFIFO_36K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + + + +endmodule + +module SFIFO_18K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_SFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module SFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module AFIFO_18K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_AFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module AFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v new file mode 100644 index 00000000000..2c2b814abb1 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -0,0 +1,11081 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 +`timescale 1ns /10ps + +`default_nettype none + +module TDP36K ( + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); +endmodule + +module RAM_18K_X2_BLK ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* port_a1_dwidth = WR1_DATA_WIDTH *) +(* port_a2_dwidth = WR2_DATA_WIDTH *) +(* port_b1_dwidth = RD1_DATA_WIDTH *) +(* port_b2_dwidth = RD2_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* port_a_dwidth = WR1_DATA_WIDTH *) +(* port_b_dwidth = RD1_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module RAM_18K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 18; +parameter RD_DATA_WIDTH = 18; +parameter BE_WIDTH = 2; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + + (* is_inferred = 0 *) + (* is_split = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + +endmodule + +module RAM_36K_BLK ( + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o +); + +parameter WR_ADDR_WIDTH = 10; +parameter RD_ADDR_WIDTH = 10; +parameter WR_DATA_WIDTH = 36; +parameter RD_DATA_WIDTH = 36; +parameter BE_WIDTH = 4; + +parameter INIT = 0; + +input wire WEN_i; +input wire REN_i; +input wire WR_CLK_i; +input wire RD_CLK_i; +input wire [BE_WIDTH-1:0] WR_BE_i; +input wire [WR_ADDR_WIDTH-1 :0] WR_ADDR_i; +input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; +input wire [WR_DATA_WIDTH-1 :0] WDATA_i; +output wire [RD_DATA_WIDTH-1 :0] RDATA_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] WR_BE; + +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; + +wire [14:0] WR_ADDR_INT; +wire [14:0] RD_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + +assign PORT_A_CLK = WR_CLK_i; +assign PORT_B_CLK = RD_CLK_i; + +generate + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end +endgenerate + +case (WR_DATA_WIDTH) + 1: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = WR_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = WR_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = WR_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = WR_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = WR_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = WR_ADDR_INT; + end +endcase + +generate + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end +endgenerate + +case (RD_DATA_WIDTH) + 1: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = RD_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = RD_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = RD_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = RD_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = RD_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = RD_ADDR_INT; + end +endcase + +case (BE_WIDTH) + 4: begin + assign WR_BE = WR_BE_i[BE_WIDTH-1 :0]; + end + default: begin + assign WR_BE[3:BE_WIDTH] = 0; + assign WR_BE[BE_WIDTH-1 :0] = WR_BE_i[BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN_i; +assign {BE_A2_i, BE_A1_i} = WR_BE; + +assign REN_B1_i = REN_i; +assign WEN_B1_i = 1'b0; +assign {BE_B2_i, BE_B1_i} = 4'h0; + +generate + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +assign WDATA_B1_i = 18'h0; +assign WDATA_B2_i = 18'h0; + +generate + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = WR_DATA_WIDTH *) +(* port_b_width = RD_DATA_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + + +input wire PORT_A1_CLK_i; +input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input wire PORT_A1_WEN_i; +input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input wire PORT_A1_REN_i; +output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input wire PORT_B1_CLK_i; +input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input wire PORT_B1_WEN_i; +input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input wire PORT_B1_REN_i; +output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input wire PORT_A2_CLK_i; +input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input wire PORT_A2_WEN_i; +input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input wire PORT_A2_REN_i; +output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input wire PORT_B2_CLK_i; +input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input wire PORT_B2_WEN_i; +input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input wire PORT_B2_REN_i; +output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 1 *) +(* port_a1_dwidth = PORT_A1_DWIDTH *) +(* port_a2_dwidth = PORT_A2_DWIDTH *) +(* port_b1_dwidth = PORT_B1_DWIDTH *) +(* port_b2_dwidth = PORT_B2_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input wire PORT_A1_CLK_i; +input wire [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input wire [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input wire PORT_A1_WEN_i; +input wire [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input wire PORT_A1_REN_i; +output wire [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input wire PORT_B1_CLK_i; +input wire [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input wire [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input wire PORT_B1_WEN_i; +input wire [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input wire PORT_B1_REN_i; +output wire [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input wire PORT_A2_CLK_i; +input wire [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input wire [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input wire PORT_A2_WEN_i; +input wire [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input wire PORT_A2_REN_i; +output wire [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input wire PORT_B2_CLK_i; +input wire [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input wire [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input wire PORT_B2_WEN_i; +input wire [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input wire PORT_B2_REN_i; +output wire [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* port_a_dwidth = PORT_A1_DWIDTH *) +(* port_b_dwidth = PORT_B1_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input wire PORT_A_CLK_i; +input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input wire PORT_A_WEN_i; +input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input wire PORT_A_REN_i; +output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input wire PORT_B_CLK_i; +input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input wire PORT_B_WEN_i; +input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input wire PORT_B_REN_i; +output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +(* is_inferred = 0 *) +(* is_split = 0 *) +BRAM2x18_dP #( + .PORT_A1_AWIDTH(PORT_A_AWIDTH), + .PORT_A1_DWIDTH(PORT_A_DWIDTH), + .PORT_A1_WR_BE_WIDTH(PORT_A_WR_BE_WIDTH), + .PORT_B1_AWIDTH(PORT_B_AWIDTH), + .PORT_B1_DWIDTH(PORT_B_DWIDTH), + .PORT_B1_WR_BE_WIDTH(PORT_B_WR_BE_WIDTH), + .PORT_A2_AWIDTH(), + .PORT_A2_DWIDTH(), + .PORT_A2_WR_BE_WIDTH(), + .PORT_B2_AWIDTH(), + .PORT_B2_DWIDTH(), + .PORT_B2_WR_BE_WIDTH() +) U1 ( + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() +); + +endmodule + +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o +); + +parameter PORT_A_AWIDTH = 10; +parameter PORT_A_DWIDTH = 36; +parameter PORT_A_WR_BE_WIDTH = 4; + +parameter PORT_B_AWIDTH = 10; +parameter PORT_B_DWIDTH = 36; +parameter PORT_B_WR_BE_WIDTH = 4; + +input wire PORT_A_CLK_i; +input wire [PORT_A_AWIDTH-1:0] PORT_A_ADDR_i; +input wire [PORT_A_DWIDTH-1:0] PORT_A_WR_DATA_i; +input wire PORT_A_WEN_i; +input wire [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE_i; +input wire PORT_A_REN_i; +output wire [PORT_A_DWIDTH-1:0] PORT_A_RD_DATA_o; + +input wire PORT_B_CLK_i; +input wire [PORT_B_AWIDTH-1:0] PORT_B_ADDR_i; +input wire [PORT_B_DWIDTH-1:0] PORT_B_WR_DATA_i; +input wire PORT_B_WEN_i; +input wire [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE_i; +input wire PORT_B_REN_i; +output wire [PORT_B_DWIDTH-1:0] PORT_B_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [3:0] PORT_A_WR_BE; +wire [3:0] PORT_B_WR_BE; + +wire [35:0] PORT_B_WDATA; +wire [35:0] PORT_B_RDATA; +wire [35:0] PORT_A_WDATA; +wire [35:0] PORT_A_RDATA; + +wire [14:0] PORT_A_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; + +wire [14:0] PORT_A_ADDR; +wire [14:0] PORT_B_ADDR; + +wire PORT_A_CLK; +wire PORT_B_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_DWIDTH); + +assign PORT_A_CLK = PORT_A_CLK_i; +assign PORT_B_CLK = PORT_B_CLK_i; + +generate + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end +endgenerate + +case (PORT_A_DWIDTH) + 1: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end + 2: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 1; + end + 4: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT << 5; + end + default: begin + assign PORT_A_ADDR = PORT_A_ADDR_INT; + end +endcase + +generate + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end +endgenerate + +case (PORT_B_DWIDTH) + 1: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end + 2: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 1; + end + 4: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 4; + end + 32, 36: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT << 5; + end + default: begin + assign PORT_B_ADDR = PORT_B_ADDR_INT; + end +endcase + +case (PORT_A_WR_BE_WIDTH) + 4: begin + assign PORT_A_WR_BE = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A_WR_BE[3:PORT_A_WR_BE_WIDTH] = 0; + assign PORT_A_WR_BE[PORT_A_WR_BE_WIDTH-1 :0] = PORT_A_WR_BE_i[PORT_A_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B_WR_BE_WIDTH) + 4: begin + assign PORT_B_WR_BE = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B_WR_BE[3:PORT_B_WR_BE_WIDTH] = 0; + assign PORT_B_WR_BE[PORT_B_WR_BE_WIDTH-1 :0] = PORT_B_WR_BE_i[PORT_B_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A_REN_i; +assign WEN_A1_i = PORT_A_WEN_i; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_REN_i; +assign WEN_B1_i = PORT_B_WEN_i; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A_WDATA[17:0]; +assign WDATA_A2_i = PORT_A_WDATA[35:18]; + +generate + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end +endgenerate + +assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B_WDATA[17:0]; +assign WDATA_B2_i = PORT_B_WDATA[35:18]; + +generate + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end +endgenerate + +assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = PORT_A_DWIDTH *) +(* port_b_width = PORT_B_DWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module SFIFO_18K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_SFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module SFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module AFIFO_18K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + BRAM2x18_AFIFO #( + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() + ); + +endmodule + +module AFIFO_18K_X2_BLK ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + +module SFIFO_36K_BLK ( + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + +endmodule + + +module AFIFO_36K_BLK ( + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT +); + + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg[17:0]), + .WDATA_A2_i(in_reg[35:18]), + .RDATA_A1_o(fifo_flags), + .RDATA_A2_o(), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk), + .CLK_A2_i(1'b0), + .REN_A1_i(1'b1), + .REN_A2_i(1'b0), + .WEN_A1_i(PUSH), + .WEN_A2_i(1'b0), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg[17:0]), + .RDATA_B2_o(out_reg[35:18]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk), + .CLK_B2_i(1'b0), + .REN_B1_i(POP), + .REN_B2_i(1'b0), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush), + .FLUSH2_i(1'b0) + ); + +endmodule + +//=============================================================================== +module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule + +module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i +); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + +`ifdef SDF_SIM + specify + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify +`endif + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v new file mode 100644 index 00000000000..645a62f833a --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -0,0 +1,376 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none +(* abc9_lut=1 *) +module LUT1(output wire O, input wire I0); + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 74; + endspecify +endmodule + +(* abc9_lut=2 *) +module LUT2(output wire O, input wire I0, I1); + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 116; + (I1 => O) = 74; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT3(output wire O, input wire I0, I1, I2); + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 162; + (I1 => O) = 116; + (I2 => O) = 174; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT4(output wire O, input wire I0, I1, I2, I3); + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 201; + (I1 => O) = 162; + (I2 => O) = 116; + (I3 => O) = 74; + endspecify +endmodule + +(* abc9_lut=3 *) +module LUT5(output wire O, input wire I0, I1, I2, I3, I4); + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 228; + (I1 => O) = 189; + (I2 => O) = 143; + (I3 => O) = 100; + (I4 => O) = 55; + endspecify +endmodule + +(* abc9_lut=5 *) +module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5); + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 251; + (I1 => O) = 212; + (I2 => O) = 166; + (I3 => O) = 123; + (I4 => O) = 77; + (I5 => O) = 43; + endspecify +endmodule + +(* abc9_flop, lib_whitebox *) +module sh_dff( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + + initial Q <= 1'b0; + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify + +endmodule + +(* abc9_box, lib_whitebox *) +(* blackbox *) +(* keep *) +module adder_carry( + output wire sumout, + (* abc9_carry *) + output wire cout, + input wire p, + input wire g, + (* abc9_carry *) + input wire cin +); + assign sumout = p ^ cin; + assign cout = p ? cin : g; + + specify + (p => sumout) = 35; + (g => sumout) = 35; + (cin => sumout) = 40; + (p => cout) = 67; + (g => cout) = 65; + (cin => cout) = 69; + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + initial Q <= 1'b0; + + always @(posedge C) + Q <= D; + + specify + (posedge C=>(Q+:D)) = 285; + $setuphold(posedge C, D, 56, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffn( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C +); + initial Q <= 1'b0; + + always @(negedge C) + Q <= D; + + specify + (negedge C=>(Q+:D)) = 285; + $setuphold(negedge C, D, 56, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, E, 32, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module dffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, E, 32, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, R, 32, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module sdffnsre( + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S +); + initial Q <= 1'b0; + + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, R, 32, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchsre ( + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E +); + initial Q <= 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && G) + Q <= D; + end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify + +endmodule + +(* abc9_flop, lib_whitebox *) +module latchnsre ( + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E +); + initial Q <= 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && !G) + Q <= D; + end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v new file mode 100644 index 00000000000..26fa6ed3604 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v @@ -0,0 +1,133 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +// DFF, asynchronous set/reset, enable +module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; + output Q; + dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); +endmodule + +module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); + input C; + input S; + input R; + input E; + input D; + output Q; + dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); +endmodule + +// DFF, synchronous set or reset, enable +module \$_SDFFE_PN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); +endmodule + +module \$_SDFFE_PN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); +endmodule + +module \$_SDFFE_NN0P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); +endmodule + +module \$_SDFFE_NN1P_ (D, C, R, E, Q); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); +endmodule + +// Latch, no set/reset, no enable +module \$_DLATCH_P_ (input E, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); +endmodule + +module \$_DLATCH_N_ (input E, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); +endmodule + +// Latch with async set and reset and enable +module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule + +module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); +endmodule + +module \$__SHREG_DFF_P_ (D, Q, C); + input D; + input C; + output Q; + + parameter DEPTH = 2; + + reg [DEPTH-2:0] q; + + genvar i; + generate for (i = 0; i < DEPTH; i = i + 1) begin: slice + + // First in chain + generate if (i == 0) begin + sh_dff #() shreg_beg ( + .Q(q[i]), + .D(D), + .C(C) + ); + end endgenerate + // Middle in chain + generate if (i > 0 && i != DEPTH-1) begin + sh_dff #() shreg_mid ( + .Q(q[i]), + .D(q[i-1]), + .C(C) + ); + end endgenerate + // Last in chain + generate if (i == DEPTH-1) begin + sh_dff #() shreg_end ( + .Q(Q), + .D(q[i-1]), + .C(C) + ); + end endgenerate + end: slice + endgenerate + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt b/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt new file mode 100644 index 00000000000..3317956f822 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt @@ -0,0 +1,22 @@ +ram block $__QLF_TDP36K { + init any; + byte 9; + option "SPLIT" 0 { + abits 15; + widths 1 2 4 9 18 36 per_port; + } + option "SPLIT" 1 { + abits 14; + widths 1 2 4 9 18 per_port; + } + cost 65; + port srsw "A" "B" { + width tied; + clock posedge; + # wen causes read even when ren is low + # map clken = wen || ren + clken; + wrbe_separate; + rdwr old; + } +} diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v new file mode 100644 index 00000000000..20638c4f9af --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -0,0 +1,457 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QLF_TDP36K (PORT_A_CLK, PORT_A_ADDR, PORT_A_WR_DATA, PORT_A_WR_EN, PORT_A_WR_BE, PORT_A_CLK_EN, PORT_A_RD_DATA, + PORT_B_CLK, PORT_B_ADDR, PORT_B_WR_DATA, PORT_B_WR_EN, PORT_B_WR_BE, PORT_B_CLK_EN, PORT_B_RD_DATA); + +parameter INIT = 0; + +parameter OPTION_SPLIT = 0; + +parameter PORT_A_WIDTH = 1; +parameter PORT_A_WR_BE_WIDTH = 1; + +parameter PORT_B_WIDTH = 1; +parameter PORT_B_WR_BE_WIDTH = 1; + +input PORT_A_CLK; +input [14:0] PORT_A_ADDR; +input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA; +input PORT_A_WR_EN; +input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE; +input PORT_A_CLK_EN; +output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA; + +input PORT_B_CLK; +input [14:0] PORT_B_ADDR; +input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA; +input PORT_B_WR_EN; +input [PORT_B_WR_BE_WIDTH-1:0] PORT_B_WR_BE; +input PORT_B_CLK_EN; +output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B_WIDTH); + +assign REN_A1_i = PORT_A_CLK_EN; +assign WEN_A1_i = PORT_A_CLK_EN & PORT_A_WR_EN; +assign {BE_A2_i, BE_A1_i} = PORT_A_WR_BE; + +assign REN_B1_i = PORT_B_CLK_EN; +assign WEN_B1_i = PORT_B_CLK_EN & PORT_B_WR_EN; +assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; + +case (PORT_A_WIDTH) +9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA; +18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A_WR_DATA; +36: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0], WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0]} = PORT_A_WR_DATA; +default: assign WDATA_A1_i = PORT_A_WR_DATA; // 1,2,4 +endcase + +case (PORT_B_WIDTH) +9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA; +18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B_WR_DATA; +36: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0], WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0]} = PORT_B_WR_DATA; +default: assign WDATA_B1_i = PORT_B_WR_DATA; // 1,2,4 +endcase + +case (PORT_A_WIDTH) +9: assign PORT_A_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] }; +18: assign PORT_A_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] }; +36: assign PORT_A_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0], RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0]}; +default: assign PORT_A_RD_DATA = RDATA_A1_o; // 1,2,4 +endcase + +case (PORT_B_WIDTH) +9: assign PORT_B_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] }; +18: assign PORT_B_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] }; +36: assign PORT_B_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0], RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0]}; +default: assign PORT_B_RD_DATA = RDATA_B1_o; // 1,2,4 +endcase + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 1 *) +(* is_split = 0 *) +(* port_a_width = PORT_A_WIDTH *) +(* port_b_width = PORT_B_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A_CLK), + .ADDR_A1_i(PORT_A_ADDR), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A_CLK), + .ADDR_A2_i(PORT_A_ADDR[13:0]), + .WEN_A2_i(WEN_A1_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A1_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B_CLK), + .ADDR_B1_i(PORT_B_ADDR), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B_CLK), + .ADDR_B2_i(PORT_B_ADDR[13:0]), + .WEN_B2_i(WEN_B1_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B1_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module \$__QLF_TDP36K_MERGED (...); + +parameter INIT1 = 0; + +parameter PORT_A1_WIDTH = 1; +parameter PORT_B1_WIDTH = 1; + +parameter PORT_A1_WR_BE_WIDTH = 1; +parameter PORT_B1_WR_BE_WIDTH = 1; + +input PORT_A1_CLK; +input [14:0] PORT_A1_ADDR; +input [PORT_A1_WIDTH-1:0] PORT_A1_WR_DATA; +input PORT_A1_WR_EN; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE; +input PORT_A1_CLK_EN; +output [PORT_A1_WIDTH-1:0] PORT_A1_RD_DATA; + +input PORT_B1_CLK; +input [14:0] PORT_B1_ADDR; +input [PORT_B1_WIDTH-1:0] PORT_B1_WR_DATA; +input PORT_B1_WR_EN; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE; +input PORT_B1_CLK_EN; +output [PORT_B1_WIDTH-1:0] PORT_B1_RD_DATA; + +parameter INIT2 = 0; + +parameter PORT_A2_WIDTH = 1; +parameter PORT_B2_WIDTH = 1; +parameter PORT_A2_WR_BE_WIDTH = 1; +parameter PORT_B2_WR_BE_WIDTH = 1; + +input PORT_A2_CLK; +input [14:0] PORT_A2_ADDR; +input [PORT_A2_WIDTH-1:0] PORT_A2_WR_DATA; +input PORT_A2_WR_EN; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE; +input PORT_A2_CLK_EN; +output [PORT_A2_WIDTH-1:0] PORT_A2_RD_DATA; + +input PORT_B2_CLK; +input [14:0] PORT_B2_ADDR; +input [PORT_B2_WIDTH-1:0] PORT_B2_WR_DATA; +input PORT_B2_WR_EN; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE; +input PORT_B2_CLK_EN; +output [PORT_B2_WIDTH-1:0] PORT_B2_RD_DATA; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +default: mode = 3'b000; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_WIDTH); +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_WIDTH); + +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_WIDTH); + +assign REN_A1_i = PORT_A1_CLK_EN; +assign WEN_A1_i = PORT_A1_CLK_EN & PORT_A1_WR_EN; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_B1_i = PORT_B1_CLK_EN; +assign WEN_B1_i = PORT_B1_CLK_EN & PORT_B1_WR_EN; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_A2_i = PORT_A2_CLK_EN; +assign WEN_A2_i = PORT_A2_CLK_EN & PORT_A2_WR_EN; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B2_i = PORT_B2_CLK_EN; +assign WEN_B2_i = PORT_B2_CLK_EN & PORT_B2_WR_EN; +assign BE_B2_i = PORT_B2_WR_BE; + +assign ADDR_A1_i = PORT_A1_ADDR; +assign ADDR_B1_i = PORT_B1_ADDR; +assign ADDR_A2_i = PORT_A2_ADDR; +assign ADDR_B2_i = PORT_B2_ADDR; + +case (PORT_A1_WIDTH) +9: assign { WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA; +18: assign { WDATA_A1_i[17], WDATA_A1_i[15:8], WDATA_A1_i[16], WDATA_A1_i[7:0] } = PORT_A1_WR_DATA; +default: assign WDATA_A1_i = PORT_A1_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_B1_WIDTH) +9: assign { WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA; +18: assign { WDATA_B1_i[17], WDATA_B1_i[15:8], WDATA_B1_i[16], WDATA_B1_i[7:0] } = PORT_B1_WR_DATA; +default: assign WDATA_B1_i = PORT_B1_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_A1_WIDTH) +9: assign PORT_A1_RD_DATA = { RDATA_A1_o[16], RDATA_A1_o[7:0] }; +18: assign PORT_A1_RD_DATA = { RDATA_A1_o[17], RDATA_A1_o[15:8], RDATA_A1_o[16], RDATA_A1_o[7:0] }; +default: assign PORT_A1_RD_DATA = RDATA_A1_o; // 1,2,4,8,16 +endcase + +case (PORT_B1_WIDTH) +9: assign PORT_B1_RD_DATA = { RDATA_B1_o[16], RDATA_B1_o[7:0] }; +18: assign PORT_B1_RD_DATA = { RDATA_B1_o[17], RDATA_B1_o[15:8], RDATA_B1_o[16], RDATA_B1_o[7:0] }; +default: assign PORT_B1_RD_DATA = RDATA_B1_o; // 1,2,4,8,16 +endcase + +case (PORT_A2_WIDTH) +9: assign { WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA; +18: assign { WDATA_A2_i[17], WDATA_A2_i[15:8], WDATA_A2_i[16], WDATA_A2_i[7:0] } = PORT_A2_WR_DATA; +default: assign WDATA_A2_i = PORT_A2_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_B2_WIDTH) +9: assign { WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA; +18: assign { WDATA_B2_i[17], WDATA_B2_i[15:8], WDATA_B2_i[16], WDATA_B2_i[7:0] } = PORT_B2_WR_DATA; +default: assign WDATA_B2_i = PORT_B2_WR_DATA; // 1,2,4,8,16 +endcase + +case (PORT_A2_WIDTH) +9: assign PORT_A2_RD_DATA = { RDATA_A2_o[16], RDATA_A2_o[7:0] }; +18: assign PORT_A2_RD_DATA = { RDATA_A2_o[17], RDATA_A2_o[15:8], RDATA_A2_o[16], RDATA_A2_o[7:0] }; +default: assign PORT_A2_RD_DATA = RDATA_A2_o; // 1,2,4,8,16 +endcase + +case (PORT_B2_WIDTH) +9: assign PORT_B2_RD_DATA = { RDATA_B2_o[16], RDATA_B2_o[7:0] }; +18: assign PORT_B2_RD_DATA = { RDATA_B2_o[17], RDATA_B2_o[15:8], RDATA_B2_o[16], RDATA_B2_o[7:0] }; +default: assign PORT_B2_RD_DATA = RDATA_B2_o; // 1,2,4,8,16 +endcase + +defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + +(* is_inferred = 1 *) +(* is_split = 1 *) +(* port_a1_width = PORT_A1_WIDTH *) +(* port_a2_width = PORT_A2_WIDTH *) +(* port_b1_width = PORT_B1_WIDTH *) +(* port_b2_width = PORT_B2_WIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(WDATA_A1_i), + .WDATA_A2_i(WDATA_A2_i), + .RDATA_A1_o(RDATA_A1_o), + .RDATA_A2_o(RDATA_A2_o), + .ADDR_A1_i(ADDR_A1_i), + .ADDR_A2_i(ADDR_A2_i), + .CLK_A1_i(PORT_A1_CLK), + .CLK_A2_i(PORT_A2_CLK), + .REN_A1_i(REN_A1_i), + .REN_A2_i(REN_A2_i), + .WEN_A1_i(WEN_A1_i), + .WEN_A2_i(WEN_A2_i), + .BE_A1_i(BE_A1_i), + .BE_A2_i(BE_A2_i), + + .WDATA_B1_i(WDATA_B1_i), + .WDATA_B2_i(WDATA_B2_i), + .RDATA_B1_o(RDATA_B1_o), + .RDATA_B2_o(RDATA_B2_o), + .ADDR_B1_i(ADDR_B1_i), + .ADDR_B2_i(ADDR_B2_i), + .CLK_B1_i(PORT_B1_CLK), + .CLK_B2_i(PORT_B2_CLK), + .REN_B1_i(REN_B1_i), + .REN_B2_i(REN_B2_i), + .WEN_B1_i(WEN_B1_i), + .WEN_B2_i(WEN_B2_i), + .BE_B1_i(BE_B1_i), + .BE_B2_i(BE_B2_i), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/quicklogic_eqn.cc b/techlibs/quicklogic/quicklogic_eqn.cc new file mode 100644 index 00000000000..b82a1b2866e --- /dev/null +++ b/techlibs/quicklogic/quicklogic_eqn.cc @@ -0,0 +1,100 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct QuicklogicEqnPass : public Pass { + QuicklogicEqnPass() : Pass("quicklogic_eqn", "Quicklogic: Calculate equations for luts") {} + void help() override + { + log("\n"); + log(" quicklogic_eqn [selection]\n"); + log("\n"); + log("Calculate equations for luts since bitstream generator depends on it.\n"); + log("\n"); + } + + Const init2eqn(Const init, int inputs) + { + std::string init_bits = init.as_string(); + const char *names[] = {"I0", "I1", "I2", "I3", "I4"}; + + std::string eqn; + int width = (int)pow(2, inputs); + for (int i = 0; i < width; i++) { + if (init_bits[width - 1 - i] == '1') { + eqn += "("; + for (int j = 0; j < inputs; j++) { + if (i & (1 << j)) + eqn += names[j]; + else + eqn += std::string("~") + names[j]; + + if (j != (inputs - 1)) + eqn += "*"; + } + eqn += ")+"; + } + } + if (eqn.empty()) + return Const("0"); + eqn = eqn.substr(0, eqn.length() - 1); + return Const(eqn); + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing Quicklogic_EQN pass (calculate equations for luts).\n"); + + extra_args(args, args.size(), design); + + int cnt = 0; + for (auto module : design->selected_modules()) { + for (auto cell : module->selected_cells()) { + if (cell->type == ID(LUT1)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 1)); + cnt++; + } + if (cell->type == ID(LUT2)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 2)); + cnt++; + } + if (cell->type == ID(LUT3)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 3)); + cnt++; + } + if (cell->type == ID(LUT4)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 4)); + cnt++; + } + if (cell->type == ID(LUT5)) { + cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 5)); + cnt++; + } + } + } + log_header(design, "Updated %d of LUT* elements with equation.\n", cnt); + } +} QuicklogicEqnPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 7fddbc97078..15ab68a3f72 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -2,6 +2,7 @@ * yosys -- Yosys Open SYnthesis Suite * * Copyright (C) 2021 QuickLogic Corp. + * Copyright 2020-2022 F4PGA Authors * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above @@ -30,6 +31,7 @@ struct SynthQuickLogicPass : public ScriptPass { void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" synth_quicklogic [options]\n"); log("This command runs synthesis for QuickLogic FPGAs\n"); @@ -42,6 +44,17 @@ struct SynthQuickLogicPass : public ScriptPass { log(" generate the synthesis netlist for the specified family.\n"); log(" supported values:\n"); log(" - pp3: PolarPro 3 \n"); + log(" - qlf_k6n10f: K6N10f\n"); + log("\n"); + log(" -nocarry\n"); + log(" do not use adder_carry cells in output netlist.\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use block RAM cells in output netlist.\n"); + log("\n"); + log(" -bramtypes\n"); + log(" Emit specialized BRAM cells for particular address and data width\n"); + log(" configurations.\n"); log("\n"); log(" -blif \n"); log(" write the design to the specified BLIF file. writing of an output file\n"); @@ -61,7 +74,7 @@ struct SynthQuickLogicPass : public ScriptPass { } string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; - bool abc9; + bool abc9, inferAdder, nobram, bramTypes; void clear_flags() override { @@ -72,12 +85,26 @@ struct SynthQuickLogicPass : public ScriptPass { currmodule = ""; family = "pp3"; abc9 = true; + inferAdder = true; + nobram = false; + bramTypes = false; + lib_path = "+/quicklogic/"; + } + + void set_scratchpad_defaults(RTLIL::Design *design) { + lib_path = design->scratchpad_get_string("ql.lib_path", lib_path); + if (lib_path.back() != '/') + lib_path += "/"; + inferAdder = !design->scratchpad_get_bool("ql.nocarry", false); + nobram = design->scratchpad_get_bool("ql.nobram", false); + bramTypes = design->scratchpad_get_bool("ql.bramtypes", false); } void execute(std::vector args, RTLIL::Design *design) override { string run_from, run_to; clear_flags(); + set_scratchpad_defaults(design); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) @@ -114,6 +141,18 @@ struct SynthQuickLogicPass : public ScriptPass { abc9 = false; continue; } + if (args[argidx] == "-nocarry") { + inferAdder = false; + continue; + } + if (args[argidx] == "-nobram") { + nobram = true; + continue; + } + if (args[argidx] == "-bramtypes") { + bramTypes = true; + continue; + } break; } extra_args(args, argidx, design); @@ -121,7 +160,7 @@ struct SynthQuickLogicPass : public ScriptPass { if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (family != "pp3") + if (family != "pp3" && family != "qlf_k6n10f") log_cmd_error("Invalid family specified: '%s'\n", family.c_str()); if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { @@ -144,14 +183,22 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("begin")) { - run(stringf("read_verilog -lib -specify +/quicklogic/common/cells_sim.v +/quicklogic/%s/cells_sim.v", family.c_str())); + std::string read_simlibs = stringf("read_verilog -lib -specify %scommon/cells_sim.v %s%s/cells_sim.v", lib_path.c_str(), lib_path.c_str(), family.c_str()); + if (family == "qlf_k6n10f") { + read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); + if (bramTypes) + read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + } + run(read_simlibs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); } if (check_label("prepare")) { run("proc"); run("flatten"); - run("tribuf -logic"); + if (help_mode || family == "pp3") { + run("tribuf -logic", " (for pp3)"); + } run("deminout"); run("opt_expr"); run("opt_clean"); @@ -176,6 +223,71 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") && (help_mode || family == "qlf_k6n10f")) { + run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); + run("ql_bram_merge"); + run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); + run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); + run("techmap -map " + lib_path + family + "/brams_final_map.v"); + + if (help_mode) { + run("chtype -set TDP36K_ t:TDP36K a:", "(if -bram_types)"); + } + else if (bramTypes) { + for (int a_dwidth : {1, 2, 4, 9, 18, 36}) + for (int b_dwidth: {1, 2, 4, 9, 18, 36}) { + run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " + "a:is_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", + a_dwidth, b_dwidth, a_dwidth, b_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_ASYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " + "a:is_fifo=1 %%i a:sync_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", + a_dwidth, b_dwidth, a_dwidth, b_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_SYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " + "a:is_fifo=1 %%i a:sync_fifo=1 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", + a_dwidth, b_dwidth, a_dwidth, b_dwidth)); + } + + for (int a1_dwidth : {1, 2, 4, 9, 18}) + for (int b1_dwidth: {1, 2, 4, 9, 18}) + for (int a2_dwidth : {1, 2, 4, 9, 18}) + for (int b2_dwidth: {1, 2, 4, 9, 18}) { + run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " + "a:is_split=1 %%i a:is_fifo=0 %%i " + "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", + a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_ASYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " + "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=0 %%i " + "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", + a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); + + run(stringf("chtype -set TDP36K_FIFO_SYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " + "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=1 %%i " + "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", + a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); + } + + + for (int a_width : {1, 2, 4, 9, 18, 36}) + for (int b_width: {1, 2, 4, 9, 18, 36}) { + run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i " + "a:port_a_width=%d %%i a:port_b_width=%d %%i", + a_width, b_width, a_width, b_width)); + } + + for (int a1_width : {1, 2, 4, 9, 18}) + for (int b1_width: {1, 2, 4, 9, 18}) + for (int a2_width : {1, 2, 4, 9, 18}) + for (int b2_width: {1, 2, 4, 9, 18}) { + run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=1 %%i " + "a:port_a1_width=%d %%i a:port_b1_width=%d %%i a:port_a2_width=%d %%i a:port_b2_width=%d %%i", + a1_width, b1_width, a2_width, b2_width, a1_width, b1_width, a2_width, b2_width)); + } + } + } + if (check_label("map_ffram")) { run("opt -fast -mux_undef -undriven -fine"); run("memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block " @@ -185,36 +297,65 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_gates")) { - run("techmap"); + if (inferAdder && family == "qlf_k6n10f") { + run("techmap -map +/techmap.v -map " + lib_path + family + "/arith_map.v", "(unless -no_adder)"); + } else { + run("techmap"); + } run("opt -fast"); - run("muxcover -mux8 -mux4"); + if (help_mode || family == "pp3") { + run("muxcover -mux8 -mux4", "(for pp3)"); + } } if (check_label("map_ffs")) { run("opt_expr"); - run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); - - run(stringf("techmap -map +/quicklogic/%s/cells_map.v -map +/quicklogic/%s/ffs_map.v", family.c_str(), family.c_str())); - - run("opt_expr -mux_undef"); + if (help_mode) { + run("shregmap -minlen -maxlen ", "(for qlf_k6n10f)"); + run("dfflegalize -cell "); + run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)"); + } + if (family == "pp3") { + run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); + run("techmap -map " + lib_path + family + "/cells_map.v -map " + lib_path + family + "/ffs_map.v"); + run("opt_expr -mux_undef"); + } else if (family == "qlf_k6n10f") { + run("shregmap -minlen 8 -maxlen 20"); + // FIXME: Apparently dfflegalize leaves around $_DLATCH_[NP]_ even if + // not in the allowed set. As a workaround we put them in the allowed + // set explicitly and map them later to $_DLATCHSR_[NP]NN_. + run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0"); + } + run("opt"); } - if (check_label("map_luts")) { - run(stringf("techmap -map +/quicklogic/%s/latches_map.v", family.c_str())); + if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { + run("techmap -map " + lib_path + family + "/latches_map.v"); if (abc9) { - run(stringf("read_verilog -lib -specify -icells +/quicklogic/%s/abc9_model.v", family.c_str())); - run(stringf("techmap -map +/quicklogic/%s/abc9_map.v", family.c_str())); + run("read_verilog -lib -specify -icells " + lib_path + family + "/abc9_model.v"); + run("techmap -map " + lib_path + family + "/abc9_map.v"); run("abc9 -maxlut 4 -dff"); - run(stringf("techmap -map +/quicklogic/%s/abc9_unmap.v", family.c_str())); + run("techmap -map " + lib_path + family + "/abc9_unmap.v"); } else { run("abc -luts 1,2,2,4 -dress"); } run("clean"); } - if (check_label("map_cells")) { - run(stringf("techmap -map +/quicklogic/%s/lut_map.v", family.c_str())); + if (check_label("map_luts", "(for qlf_k6n10f)") && (help_mode || family == "qlf_k6n10f")) { + if (abc9) { + run("abc9 -maxlut 6"); + } else { + run("abc -lut 6 -dress"); + } + run("clean"); + run("opt_lut"); + } + + if (check_label("map_cells", "(for pp3)") && (help_mode || family == "pp3")) { + run("techmap -map " + lib_path + family + "/lut_map.v"); run("clean"); + run("opt_lut"); } if (check_label("check")) { @@ -224,14 +365,18 @@ struct SynthQuickLogicPass : public ScriptPass { run("check -noinit"); } - if (check_label("iomap")) { + if (check_label("iomap", "(for pp3)") && (family == "pp3" || help_mode)) { run("clkbufmap -inpad ckpad Q:P"); run("iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top"); } if (check_label("finalize")) { - run("setundef -zero -params -undriven"); - run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top"); + if (help_mode || family == "pp3") { + run("setundef -zero -params -undriven", "(for pp3)"); + } + if (family == "pp3" || !edif_file.empty()) { + run("hilomap -hicell logic_1 A -locell logic_0 A -singleton A:top", "(for pp3 or if -edif)"); + } run("opt_clean -purge"); run("check"); run("blackbox =A:whitebox"); From 6682693888148594c21bba3a75e1fe0ab6aef950 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 14 Aug 2023 16:20:36 +0200 Subject: [PATCH 03/39] change ql-bram-types pass to use mode parameter; clean up primitive libraries --- techlibs/quicklogic/Makefile.inc | 2 +- techlibs/quicklogic/ql-bram-merge.cc | 348 +- techlibs/quicklogic/ql-bram-types.cc | 165 + techlibs/quicklogic/qlf_k6n10f/arith_map.v | 46 +- .../quicklogic/qlf_k6n10f/bram_types_sim.v | 142779 ++++++++------- .../quicklogic/qlf_k6n10f/brams_final_map.v | 1152 +- techlibs/quicklogic/qlf_k6n10f/brams_map.v | 2426 +- techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 13460 +- techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 534 +- techlibs/quicklogic/qlf_k6n10f/ffs_map.v | 154 +- .../qlf_k6n10f/generate_bram_types_sim.py | 246 + techlibs/quicklogic/quicklogic_eqn.cc | 100 - techlibs/quicklogic/synth_quicklogic.cc | 74 +- 13 files changed, 80867 insertions(+), 80619 deletions(-) create mode 100644 techlibs/quicklogic/ql-bram-types.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py delete mode 100644 techlibs/quicklogic/quicklogic_eqn.cc diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index fcc49cd77f8..df69a3fc32c 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,6 @@ OBJS += techlibs/quicklogic/synth_quicklogic.o OBJS += techlibs/quicklogic/ql-bram-merge.o -OBJS += techlibs/quicklogic/quicklogic_eqn.o +OBJS += techlibs/quicklogic/ql-bram-types.o $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql-bram-merge.cc index d64bd64cf60..1098bc8f696 100644 --- a/techlibs/quicklogic/ql-bram-merge.cc +++ b/techlibs/quicklogic/ql-bram-merge.cc @@ -31,184 +31,184 @@ PRIVATE_NAMESPACE_BEGIN struct QlBramMergeWorker { - const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); - const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); - - // can be used to record parameter values that have to match on both sides - typedef dict MergeableGroupKeyType; - - RTLIL::Module *module; - dict> mergeable_groups; - - QlBramMergeWorker(RTLIL::Module* module) : module(module) - { - for (RTLIL::Cell* cell : module->selected_cells()) - { - if(cell->type != split_cell_type) continue; - if(!cell->hasParam(ID(OPTION_SPLIT))) continue; - if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; - mergeable_groups[get_key(cell)].insert(cell); - } - } - - static MergeableGroupKeyType get_key(RTLIL::Cell* cell) - { - MergeableGroupKeyType key; - // For now, there are no restrictions on which cells can be merged - (void) cell; - return key; - } - - const dict& param_map(bool second) - { - static const dict bram1_map = { - { ID(INIT), ID(INIT1) }, - { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, - { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, - { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, - { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } - }; - static const dict bram2_map = { - { ID(INIT), ID(INIT2) }, - { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, - { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, - { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, - { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } - }; - - if(second) - return bram2_map; - else - return bram1_map; - } - - const dict& port_map(bool second) - { - static const dict bram1_map = { - { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, - { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, - { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, - { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, - { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, - { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, - { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, - { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, - { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, - { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, - { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, - { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, - { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, - { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } - }; - static const dict bram2_map = { - { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, - { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, - { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, - { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, - { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, - { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, - { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, - { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, - { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, - { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, - { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, - { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, - { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, - { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } - }; - - if(second) - return bram2_map; - else - return bram1_map; - } - - void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) - { - - // Create the new cell - RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); - log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); - - for (auto &it : param_map(false)) - { - if(bram1->hasParam(it.first)) - merged->setParam(it.second, bram1->getParam(it.first)); - } - for (auto &it : param_map(true)) - { - if(bram2->hasParam(it.first)) - merged->setParam(it.second, bram2->getParam(it.first)); - } - - for (auto &it : port_map(false)) - { - if (bram1->hasPort(it.first)) - merged->setPort(it.second, bram1->getPort(it.first)); - else - log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); - } - for (auto &it : port_map(true)) - { - if (bram2->hasPort(it.first)) - merged->setPort(it.second, bram2->getPort(it.first)); - else - log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); - } - merged->attributes = bram1->attributes; - for (auto attr: bram2->attributes) - if (!merged->has_attribute(attr.first)) - merged->attributes.insert(attr); - - // Remove the old cells - module->remove(bram1); - module->remove(bram2); - - } - - void merge_bram_groups() - { - for (auto &it : mergeable_groups) - { - while (it.second.size() > 1) - { - merge_brams(it.second.pop(), it.second.pop()); - } - } - } + const RTLIL::IdString split_cell_type = ID($__QLF_TDP36K); + const RTLIL::IdString merged_cell_type = ID($__QLF_TDP36K_MERGED); + + // can be used to record parameter values that have to match on both sides + typedef dict MergeableGroupKeyType; + + RTLIL::Module *module; + dict> mergeable_groups; + + QlBramMergeWorker(RTLIL::Module* module) : module(module) + { + for (RTLIL::Cell* cell : module->selected_cells()) + { + if(cell->type != split_cell_type) continue; + if(!cell->hasParam(ID(OPTION_SPLIT))) continue; + if(cell->getParam(ID(OPTION_SPLIT)) != RTLIL::Const(1, 32)) continue; + mergeable_groups[get_key(cell)].insert(cell); + } + } + + static MergeableGroupKeyType get_key(RTLIL::Cell* cell) + { + MergeableGroupKeyType key; + // For now, there are no restrictions on which cells can be merged + (void) cell; + return key; + } + + const dict& param_map(bool second) + { + static const dict bram1_map = { + { ID(INIT), ID(INIT1) }, + { ID(PORT_A_WIDTH), ID(PORT_A1_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B1_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A1_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B1_WR_BE_WIDTH) } + }; + static const dict bram2_map = { + { ID(INIT), ID(INIT2) }, + { ID(PORT_A_WIDTH), ID(PORT_A2_WIDTH) }, + { ID(PORT_B_WIDTH), ID(PORT_B2_WIDTH) }, + { ID(PORT_A_WR_BE_WIDTH), ID(PORT_A2_WR_BE_WIDTH) }, + { ID(PORT_B_WR_BE_WIDTH), ID(PORT_B2_WR_BE_WIDTH) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + const dict& port_map(bool second) + { + static const dict bram1_map = { + { ID(PORT_A_CLK), ID(PORT_A1_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B1_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A1_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B1_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A1_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B1_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A1_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B1_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A1_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B1_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A1_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B1_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A1_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B1_RD_DATA) } + }; + static const dict bram2_map = { + { ID(PORT_A_CLK), ID(PORT_A2_CLK) }, + { ID(PORT_B_CLK), ID(PORT_B2_CLK) }, + { ID(PORT_A_CLK_EN), ID(PORT_A2_CLK_EN) }, + { ID(PORT_B_CLK_EN), ID(PORT_B2_CLK_EN) }, + { ID(PORT_A_ADDR), ID(PORT_A2_ADDR) }, + { ID(PORT_B_ADDR), ID(PORT_B2_ADDR) }, + { ID(PORT_A_WR_DATA), ID(PORT_A2_WR_DATA) }, + { ID(PORT_B_WR_DATA), ID(PORT_B2_WR_DATA) }, + { ID(PORT_A_WR_EN), ID(PORT_A2_WR_EN) }, + { ID(PORT_B_WR_EN), ID(PORT_B2_WR_EN) }, + { ID(PORT_A_WR_BE), ID(PORT_A2_WR_BE) }, + { ID(PORT_B_WR_BE), ID(PORT_B2_WR_BE) }, + { ID(PORT_A_RD_DATA), ID(PORT_A2_RD_DATA) }, + { ID(PORT_B_RD_DATA), ID(PORT_B2_RD_DATA) } + }; + + if(second) + return bram2_map; + else + return bram1_map; + } + + void merge_brams(RTLIL::Cell* bram1, RTLIL::Cell* bram2) + { + + // Create the new cell + RTLIL::Cell* merged = module->addCell(NEW_ID, merged_cell_type); + log_debug("Merging split BRAM cells %s and %s -> %s\n", log_id(bram1->name), log_id(bram2->name), log_id(merged->name)); + + for (auto &it : param_map(false)) + { + if(bram1->hasParam(it.first)) + merged->setParam(it.second, bram1->getParam(it.first)); + } + for (auto &it : param_map(true)) + { + if(bram2->hasParam(it.first)) + merged->setParam(it.second, bram2->getParam(it.first)); + } + + for (auto &it : port_map(false)) + { + if (bram1->hasPort(it.first)) + merged->setPort(it.second, bram1->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram1->name)); + } + for (auto &it : port_map(true)) + { + if (bram2->hasPort(it.first)) + merged->setPort(it.second, bram2->getPort(it.first)); + else + log_error("Can't find port %s on cell %s!\n", log_id(it.first), log_id(bram2->name)); + } + merged->attributes = bram1->attributes; + for (auto attr: bram2->attributes) + if (!merged->has_attribute(attr.first)) + merged->attributes.insert(attr); + + // Remove the old cells + module->remove(bram1); + module->remove(bram2); + + } + + void merge_bram_groups() + { + for (auto &it : mergeable_groups) + { + while (it.second.size() > 1) + { + merge_brams(it.second.pop(), it.second.pop()); + } + } + } }; struct QlBramMergePass : public Pass { - - QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} - - void help() override - { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" ql_bram_merge [selection]\n"); - log("\n"); - log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); - log(" into a TDP36K cell operating in split mode\n"); - log("\n"); - } - - - - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing QL_BRAM_MERGE pass.\n"); - - size_t argidx = 1; - extra_args(args, argidx, design); - - for (RTLIL::Module* module : design->selected_modules()) - { - QlBramMergeWorker worker(module); - worker.merge_bram_groups(); - } - } + + QlBramMergePass() : Pass("ql_bram_merge", "Infers QuickLogic k6n10f BRAM pairs that can operate independently") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_merge [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f 18K BRAM cells and packs pairs of them together\n"); + log(" into a TDP36K cell operating in split mode\n"); + log("\n"); + } + + + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_MERGE pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + { + QlBramMergeWorker worker(module); + worker.merge_bram_groups(); + } + } } QlBramMergePass; diff --git a/techlibs/quicklogic/ql-bram-types.cc b/techlibs/quicklogic/ql-bram-types.cc new file mode 100644 index 00000000000..cf42703aaac --- /dev/null +++ b/techlibs/quicklogic/ql-bram-types.cc @@ -0,0 +1,165 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2023 N. Engelhardt + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +// ============================================================================ + + +struct QlBramTypesPass : public Pass { + + QlBramTypesPass() : Pass("ql_bram_types", "Change TDP36K type to subtypes") {} + + void help() override + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" ql_bram_types [selection]\n"); + log("\n"); + log(" This pass changes the type of TDP36K cells to different types based on the\n"); + log(" configuration of the cell.\n"); + log("\n"); + } + + int width_for_mode(int mode){ + // 1: mode = 3'b101; + // 2: mode = 3'b110; + // 4: mode = 3'b100; + // 8,9: mode = 3'b001; + // 16, 18: mode = 3'b010; + // 32, 36: mode = 3'b011; + switch (mode) + { + case 1: + return 9; + case 2: + return 18; + case 3: + return 36; + case 4: + return 4; + case 5: + return 1; + case 6: + return 2; + default: + log_error("Invalid mode: %x", mode); + } + } + + void execute(std::vector args, RTLIL::Design *design) override + { + log_header(design, "Executing QL_BRAM_TYPES pass.\n"); + + size_t argidx = 1; + extra_args(args, argidx, design); + + for (RTLIL::Module* module : design->selected_modules()) + for (RTLIL::Cell* cell: module->selected_cells()) + { + if (cell->type != ID(TDP36K) || !cell->hasParam(ID(MODE_BITS))) + continue; + + RTLIL::Const mode_bits = cell->getParam(ID(MODE_BITS)); + + bool split = mode_bits.extract(80).as_bool(); + + bool FMODE1_i = mode_bits.extract(13).as_bool(); + bool FMODE2_i = mode_bits.extract(54).as_bool(); + if (FMODE1_i != FMODE2_i) { + log_debug("Can't change type of mixed use TDP36K block: FMODE1_i = %s, FMODE2_i = %s\n", FMODE1_i ? "true" : "false", FMODE2_i ? "true" : "false"); + continue; + } + bool is_fifo = FMODE1_i; + + bool SYNC_FIFO1_i = mode_bits.extract(0).as_bool(); + bool SYNC_FIFO2_i = mode_bits.extract(41).as_bool(); + if (SYNC_FIFO1_i != SYNC_FIFO2_i) { + log_debug("Can't change type of mixed use TDP36K block: SYNC_FIFO1_i = %s, SYNC_FIFO2_i = %s\n", SYNC_FIFO1_i ? "true" : "false", SYNC_FIFO2_i ? "true" : "false"); + continue; + } + bool sync_fifo = SYNC_FIFO1_i; + + int RMODE_A1_i = mode_bits.extract(1, 3).as_int(); + int RMODE_B1_i = mode_bits.extract(4, 3).as_int(); + int WMODE_A1_i = mode_bits.extract(7, 3).as_int(); + int WMODE_B1_i = mode_bits.extract(10, 3).as_int(); + + int RMODE_A2_i = mode_bits.extract(42, 3).as_int(); + int RMODE_B2_i = mode_bits.extract(45, 3).as_int(); + int WMODE_A2_i = mode_bits.extract(48, 3).as_int(); + int WMODE_B2_i = mode_bits.extract(51, 3).as_int(); + + // TODO: should these be a warning or an error? + if (RMODE_A1_i != WMODE_A1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A1_i), width_for_mode(WMODE_A1_i)); + continue; + } + if (RMODE_B1_i != WMODE_B1_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B1 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B1_i), width_for_mode(WMODE_B1_i)); + continue; + } + if (RMODE_A2_i != WMODE_A2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port A2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_A2_i), width_for_mode(WMODE_A2_i)); + continue; + } + if (RMODE_B2_i != WMODE_B2_i) { + log_warning("Can't change type of misconfigured TDP36K block: Port B2 configured with read width = %d different from write width = %d\n", width_for_mode(RMODE_B2_i), width_for_mode(WMODE_B2_i)); + continue; + } + + // TODO: For nonsplit blocks, should RMODE_A1_i == RMODE_A2_i etc be checked/enforced? + + std::string type = "TDP36K"; + if (is_fifo) { + type += "_FIFO_"; + if (sync_fifo) + type += "SYNC_"; + else + type += "ASYNC_"; + } else + type += "_BRAM_"; + + if (split) { + type += stringf("A1_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B1_X%d_", width_for_mode(RMODE_B1_i)); + type += stringf("A2_X%d_", width_for_mode(RMODE_A2_i)); + type += stringf("B2_X%d_", width_for_mode(RMODE_B2_i)); + type += "split"; + } else { + type += stringf("A_X%d_", width_for_mode(RMODE_A1_i)); + type += stringf("B_X%d_", width_for_mode(RMODE_B1_i)); + type += "nonsplit"; + } + + cell->type = RTLIL::escape_id(type); + log_debug("Changed type of memory cell %s to %s\n", log_id(cell->name), log_id(cell->type)); + } + } + + +} QlBramMergePass; + +PRIVATE_NAMESPACE_END \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/arith_map.v b/techlibs/quicklogic/qlf_k6n10f/arith_map.v index 908b17189c5..d39a3a19f9a 100644 --- a/techlibs/quicklogic/qlf_k6n10f/arith_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/arith_map.v @@ -56,43 +56,43 @@ module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); (* force_downto *) wire [Y_WIDTH-1:0] S = {AA ^ BB}; assign CO[Y_WIDTH-1:0] = C[Y_WIDTH:1]; - //assign CO[Y_WIDTH-1] = co; + //assign CO[Y_WIDTH-1] = co; generate - adder_carry intermediate_adder ( - .cin ( ), - .cout (C[0]), - .p (1'b0), - .g (CI), - .sumout () - ); + adder_carry intermediate_adder ( + .cin ( ), + .cout (C[0]), + .p (1'b0), + .g (CI), + .sumout () + ); endgenerate genvar i; generate if (Y_WIDTH > 2) begin for (i = 0; i < Y_WIDTH-2; i = i + 1) begin:slice adder_carry my_adder ( - .cin(C[i]), - .g(AA[i]), - .p(S[i]), - .cout(C[i+1]), - .sumout(Y[i]) + .cin (C[i]), + .g (AA[i]), + .p (S[i]), + .cout (C[i+1]), + .sumout (Y[i]) ); - end + end end endgenerate generate - adder_carry final_adder ( - .cin (C[Y_WIDTH-2]), - .cout (), - .p (1'b0), - .g (1'b0), - .sumout (co) - ); + adder_carry final_adder ( + .cin (C[Y_WIDTH-2]), + .cout (), + .p (1'b0), + .g (1'b0), + .sumout (co) + ); endgenerate assign Y[Y_WIDTH-2] = S[Y_WIDTH-2] ^ co; - assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; + assign C[Y_WIDTH-1] = S[Y_WIDTH-2] ? co : AA[Y_WIDTH-2]; assign Y[Y_WIDTH-1] = S[Y_WIDTH-1] ^ C[Y_WIDTH-1]; - assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; + assign C[Y_WIDTH] = S[Y_WIDTH-1] ? C[Y_WIDTH-1] : AA[Y_WIDTH-1]; assign X = S; endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v index 3a06f676d68..39e59d43f08 100644 --- a/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v @@ -1,73373 +1,73374 @@ // **AUTOGENERATED FILE** **DO NOT EDIT** -// Generated by qlf_k6n10f/generate_bram_types_sim.py at 2023-05-02 10:42:53.971682+00:00 +// Generated by generate_bram_types_sim.py at 2023-08-17 16:34:43.930013+00:00 +`timescale 1ns /10ps module TDP36K_BRAM_A_X1_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X1_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X2_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X4_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X1_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X2_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X4_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X1_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X2_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X4_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X1_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X2_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X4_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X1_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X2_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X4_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X1_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X2_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X4_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule module TDP36K_BRAM_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i - ); - - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - - `ifdef SDF_SIM - specify - (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; - (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; - (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; - (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; - (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); - $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); - $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); - $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); - $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); - $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); - endspecify - `endif + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v index 7d04c5dda6c..43f5dc95e94 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v @@ -15,27 +15,27 @@ // SPDX-License-Identifier: Apache-2.0 module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -161,10 +161,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -190,12 +190,12 @@ localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -220,12 +220,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -250,12 +250,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -280,12 +280,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -344,49 +344,49 @@ assign WEN_B2_i = 1'b0; assign BE_B2_i = 4'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -442,44 +442,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -487,7 +487,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -621,11 +621,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -661,12 +661,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -691,12 +691,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -721,12 +721,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -751,12 +751,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -837,93 +837,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -981,209 +981,209 @@ endmodule module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -1224,207 +1224,207 @@ endmodule module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v index 42e1fc98b85..82bbceeff52 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -15,15 +15,15 @@ // SPDX-License-Identifier: Apache-2.0 module RAM_36K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -130,7 +130,7 @@ wire [35:0] PORT_B_RDATA; wire [35:0] PORT_A_WDATA; wire [14:0] WR_ADDR_INT; -wire [14:0] RD_ADDR_INT; +wire [14:0] RD_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -156,12 +156,12 @@ assign PORT_A_CLK = WR_CLK_i; assign PORT_B_CLK = RD_CLK_i; generate - if (WR_ADDR_WIDTH == 15) begin - assign WR_ADDR_INT = WR_ADDR_i; - end else begin - assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; - assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; - end + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end endgenerate case (WR_DATA_WIDTH) @@ -189,12 +189,12 @@ case (WR_DATA_WIDTH) endcase generate - if (RD_ADDR_WIDTH == 15) begin - assign RD_ADDR_INT = RD_ADDR_i; - end else begin - assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; - assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; - end + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end endgenerate case (RD_DATA_WIDTH) @@ -240,17 +240,17 @@ assign WEN_B1_i = 1'b0; assign {BE_B2_i, BE_B1_i} = 4'h0; generate - if (WR_DATA_WIDTH == 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; @@ -260,15 +260,15 @@ assign WDATA_B1_i = 18'h0; assign WDATA_B2_i = 18'h0; generate - if (RD_DATA_WIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; @@ -326,15 +326,15 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module RAM_18K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -353,69 +353,69 @@ input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; input wire [WR_DATA_WIDTH-1 :0] WDATA_i; output wire [RD_DATA_WIDTH-1 :0] RDATA_o; - (* is_inferred = 0 *) - (* is_split = 0 *) - (* is_fifo = 0 *) - BRAM2x18_SP #( - .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), - .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .BE1_WIDTH(BE_WIDTH), - .WR2_ADDR_WIDTH(), - .RD2_ADDR_WIDTH(), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .BE2_WIDTH() - ) U1 - ( - .RESET_ni(1'b1), - - .WEN1_i(WEN_i), - .REN1_i(REN_i), - .WR1_CLK_i(WR_CLK_i), - .RD1_CLK_i(RD_CLK_i), - .WR1_BE_i(WR_BE_i), - .WR1_ADDR_i(WR_ADDR_i), - .RD1_ADDR_i(RD_ADDR_i), - .WDATA1_i(WDATA_i), - .RDATA1_o(RDATA_o), - - .WEN2_i(1'b0), - .REN2_i(1'b0), - .WR2_CLK_i(1'b0), - .RD2_CLK_i(1'b0), - .WR2_BE_i(2'b00), - .WR2_ADDR_i(14'h0), - .RD2_ADDR_i(14'h0), - .WDATA2_i(18'h0), - .RDATA2_o() - ); - + (* is_inferred = 0 *) + (* is_split = 0 *) + (* is_fifo = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + endmodule module RAM_18K_X2_BLK ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -541,10 +541,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -570,12 +570,12 @@ localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -600,12 +600,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -630,12 +630,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -660,12 +660,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -724,49 +724,49 @@ assign WEN_B2_i = 1'b0; assign BE_B2_i = 4'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -824,22 +824,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_36K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -956,7 +956,7 @@ wire [35:0] PORT_A_WDATA; wire [35:0] PORT_A_RDATA; wire [14:0] PORT_A_ADDR_INT; -wire [14:0] PORT_B_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -982,12 +982,12 @@ assign PORT_A_CLK = PORT_A_CLK_i; assign PORT_B_CLK = PORT_B_CLK_i; generate - if (PORT_A_AWIDTH == 15) begin - assign PORT_A_ADDR_INT = PORT_A_ADDR_i; - end else begin - assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; - assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; - end + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end endgenerate case (PORT_A_DWIDTH) @@ -1015,12 +1015,12 @@ case (PORT_A_DWIDTH) endcase generate - if (PORT_B_AWIDTH == 15) begin - assign PORT_B_ADDR_INT = PORT_B_ADDR_i; - end else begin - assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; - assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; - end + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end endgenerate case (PORT_B_DWIDTH) @@ -1076,63 +1076,63 @@ assign WEN_B1_i = PORT_B_WEN_i; assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; assign WDATA_A2_i = PORT_A_WDATA[35:18]; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end endgenerate assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; - assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; - end else begin - assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B_WDATA[17:0]; assign WDATA_B2_i = PORT_B_WDATA[35:18]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; @@ -1188,22 +1188,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -1248,80 +1248,80 @@ BRAM2x18_dP #( .PORT_B2_DWIDTH(), .PORT_B2_WR_BE_WIDTH() ) U1 ( - .PORT_A1_CLK_i(PORT_A_CLK_i), - .PORT_A1_WEN_i(PORT_A_WEN_i), - .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), - .PORT_A1_REN_i(PORT_A_REN_i), - .PORT_A1_ADDR_i(PORT_A_ADDR_i), - .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), - .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), - - .PORT_B1_CLK_i(PORT_B_CLK_i), - .PORT_B1_WEN_i(PORT_B_WEN_i), - .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), - .PORT_B1_REN_i(PORT_B_REN_i), - .PORT_B1_ADDR_i(PORT_B_ADDR_i), - .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), - .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), - - .PORT_A2_CLK_i(1'b0), - .PORT_A2_WEN_i(1'b0), - .PORT_A2_WR_BE_i(2'b00), - .PORT_A2_REN_i(1'b0), - .PORT_A2_ADDR_i(14'h0), - .PORT_A2_WR_DATA_i(18'h0), - .PORT_A2_RD_DATA_o(), - - .PORT_B2_CLK_i(1'b0), - .PORT_B2_WEN_i(1'b0), - .PORT_B2_WR_BE_i(2'b00), - .PORT_B2_REN_i(1'b0), - .PORT_B2_ADDR_i(14'h0), - .PORT_B2_WR_DATA_i(18'h0), - .PORT_B2_RD_DATA_o() + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() ); endmodule -module DPRAM_18K_X2_BLK ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -1329,7 +1329,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -1464,11 +1464,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -1504,12 +1504,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -1534,12 +1534,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -1564,12 +1564,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -1594,12 +1594,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -1680,93 +1680,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -1825,154 +1825,154 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module SFIFO_36K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - 32, 36: rwmode = 36; - default: rwmode = 36; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - - wire Push_Clk, Pop_Clk; - - assign Push_Clk = CLK; - assign Pop_Clk = CLK; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); - localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = PORT_A_WRWIDTH *) - (* port_b_dwidth = PORT_B_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), .WDATA_A2_i(in_reg[35:18]), @@ -2008,155 +2008,155 @@ module SFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); - -endmodule + +endmodule module AFIFO_36K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - 32, 36: rwmode = 36; - default: rwmode = 36; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); - localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + 32, 36: rwmode = 36; + default: rwmode = 36; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + localparam PORT_A_WRWIDTH = rwmode(WR_DATA_WIDTH); + localparam PORT_B_WRWIDTH = rwmode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = PORT_A_WRWIDTH *) - (* port_b_dwidth = PORT_B_WRWIDTH *) + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = PORT_A_WRWIDTH *) + (* port_b_dwidth = PORT_B_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), @@ -2193,292 +2193,292 @@ module AFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); - -endmodule + +endmodule module SFIFO_18K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_SFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .CLK1(CLK), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .CLK2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module SFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = PORT_A1_WRWIDTH *) - (* port_a2_dwidth = PORT_A2_WRWIDTH *) - (* port_b1_dwidth = PORT_B1_WRWIDTH *) - (* port_b2_dwidth = PORT_B2_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -2518,288 +2518,288 @@ module SFIFO_18K_X2_BLK ( endmodule module AFIFO_18K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_AFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .Push_Clk1(Push_Clk), - .Pop_Clk1(Pop_Clk), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .Push_Clk2(1'b0), - .Pop_Clk2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module AFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = PORT_A1_WRWIDTH *) - (* port_a2_dwidth = PORT_A2_WRWIDTH *) - (* port_b1_dwidth = PORT_B1_WRWIDTH *) - (* port_b2_dwidth = PORT_B2_WRWIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = PORT_A1_WRWIDTH *) + (* port_a2_dwidth = PORT_A2_WRWIDTH *) + (* port_b1_dwidth = PORT_B1_WRWIDTH *) + (* port_b2_dwidth = PORT_B2_WRWIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v index 2c2b814abb1..5f04c0e7fac 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -18,685 +18,685 @@ `default_nettype none module TDP36K ( - RESET_ni, - WEN_A1_i, - WEN_B1_i, - REN_A1_i, - REN_B1_i, - CLK_A1_i, - CLK_B1_i, - BE_A1_i, - BE_B1_i, - ADDR_A1_i, - ADDR_B1_i, - WDATA_A1_i, - WDATA_B1_i, - RDATA_A1_o, - RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, - WEN_B2_i, - REN_A2_i, - REN_B2_i, - CLK_A2_i, - CLK_B2_i, - BE_A2_i, - BE_B2_i, - ADDR_A2_i, - ADDR_B2_i, - WDATA_A2_i, - WDATA_B2_i, - RDATA_A2_o, - RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, + WEN_B1_i, + REN_A1_i, + REN_B1_i, + CLK_A1_i, + CLK_B1_i, + BE_A1_i, + BE_B1_i, + ADDR_A1_i, + ADDR_B1_i, + WDATA_A1_i, + WDATA_B1_i, + RDATA_A1_o, + RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, + WEN_B2_i, + REN_A2_i, + REN_B2_i, + CLK_A2_i, + CLK_B2_i, + BE_A2_i, + BE_B2_i, + ADDR_A2_i, + ADDR_B2_i, + WDATA_A2_i, + WDATA_B2_i, + RDATA_A2_o, + RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - // First 18K RAMFIFO (41 bits) - localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; - localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; - localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; - localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; - localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; - localparam [ 0:0] FMODE1_i = MODE_BITS[13]; - localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; - localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; - localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; - localparam [11:0] UPAE1_i = MODE_BITS[28:17]; - localparam [11:0] UPAF1_i = MODE_BITS[40:29]; - - // Second 18K RAMFIFO (39 bits) - localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; - localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; - localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; - localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; - localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; - localparam [ 0:0] FMODE2_i = MODE_BITS[54]; - localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; - localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; - localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; - localparam [10:0] UPAE2_i = MODE_BITS[68:58]; - localparam [10:0] UPAF2_i = MODE_BITS[79:69]; - - // Split (1 bit) - localparam [ 0:0] SPLIT_i = MODE_BITS[80]; - - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - input wire RESET_ni; - input wire WEN_A1_i; - input wire WEN_B1_i; - input wire REN_A1_i; - input wire REN_B1_i; - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - input wire [1:0] BE_A1_i; - input wire [1:0] BE_B1_i; - input wire [14:0] ADDR_A1_i; - input wire [14:0] ADDR_B1_i; - input wire [17:0] WDATA_A1_i; - input wire [17:0] WDATA_B1_i; - output reg [17:0] RDATA_A1_o; - output reg [17:0] RDATA_B1_o; - input wire FLUSH1_i; - input wire WEN_A2_i; - input wire WEN_B2_i; - input wire REN_A2_i; - input wire REN_B2_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - input wire [1:0] BE_A2_i; - input wire [1:0] BE_B2_i; - input wire [13:0] ADDR_A2_i; - input wire [13:0] ADDR_B2_i; - input wire [17:0] WDATA_A2_i; - input wire [17:0] WDATA_B2_i; - output reg [17:0] RDATA_A2_o; - output reg [17:0] RDATA_B2_o; - input wire FLUSH2_i; - wire EMPTY2; - wire EPO2; - wire EWM2; - wire FULL2; - wire FMO2; - wire FWM2; - wire EMPTY1; - wire EPO1; - wire EWM1; - wire FULL1; - wire FMO1; - wire FWM1; - wire UNDERRUN1; - wire OVERRUN1; - wire UNDERRUN2; - wire OVERRUN2; - wire UNDERRUN3; - wire OVERRUN3; - wire EMPTY3; - wire EPO3; - wire EWM3; - wire FULL3; - wire FMO3; - wire FWM3; - wire ram_fmode1; - wire ram_fmode2; - wire [17:0] ram_rdata_a1; - wire [17:0] ram_rdata_b1; - wire [17:0] ram_rdata_a2; - wire [17:0] ram_rdata_b2; - reg [17:0] ram_wdata_a1; - reg [17:0] ram_wdata_b1; - reg [17:0] ram_wdata_a2; - reg [17:0] ram_wdata_b2; - reg [14:0] laddr_a1; - reg [14:0] laddr_b1; - wire [13:0] ram_addr_a1; - wire [13:0] ram_addr_b1; - wire [13:0] ram_addr_a2; - wire [13:0] ram_addr_b2; - wire smux_clk_a1; - wire smux_clk_b1; - wire smux_clk_a2; - wire smux_clk_b2; - reg [1:0] ram_be_a1; - reg [1:0] ram_be_a2; - reg [1:0] ram_be_b1; - reg [1:0] ram_be_b2; - wire [2:0] ram_rmode_a1; - wire [2:0] ram_wmode_a1; - wire [2:0] ram_rmode_b1; - wire [2:0] ram_wmode_b1; - wire [2:0] ram_rmode_a2; - wire [2:0] ram_wmode_a2; - wire [2:0] ram_rmode_b2; - wire [2:0] ram_wmode_b2; - wire ram_ren_a1; - wire ram_ren_b1; - wire ram_ren_a2; - wire ram_ren_b2; - wire ram_wen_a1; - wire ram_wen_b1; - wire ram_wen_a2; - wire ram_wen_b2; - wire ren_o; - wire [11:0] ff_raddr; - wire [11:0] ff_waddr; - reg [35:0] fifo_rdata; - wire [1:0] fifo_rmode; - wire [1:0] fifo_wmode; - wire [1:0] bwl; - wire [17:0] pl_dout0; - wire [17:0] pl_dout1; - wire sclk_a1; - wire sclk_b1; - wire sclk_a2; - wire sclk_b2; - wire sreset; - wire flush1; - wire flush2; - assign sreset = RESET_ni; - assign flush1 = ~FLUSH1_i; - assign flush2 = ~FLUSH2_i; - assign ram_fmode1 = FMODE1_i & SPLIT_i; - assign ram_fmode2 = FMODE2_i & SPLIT_i; - assign smux_clk_a1 = CLK_A1_i; - assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); - assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); - assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); - assign sclk_a1 = smux_clk_a1; - assign sclk_a2 = smux_clk_a2; - assign sclk_b1 = smux_clk_b1; - assign sclk_b2 = smux_clk_b2; - assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); - assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); - assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); - localparam MODE_36 = 3'b011; - assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); - assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); - assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); - assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); - assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); - assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); - assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); - localparam MODE_18 = 3'b010; - localparam MODE_9 = 3'b001; - always @(*) begin : WDATA_SEL - case (SPLIT_i) - 1: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_wdata_b1 = WDATA_B1_i; - ram_wdata_b2 = WDATA_B2_i; - ram_be_a2 = BE_A2_i; - ram_be_b2 = BE_B2_i; - ram_be_a1 = BE_A1_i; - ram_be_b1 = BE_B1_i; - end - 0: begin - case (WMODE_A1_i) - MODE_36: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A2_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - MODE_18: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); - ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); - end - MODE_9: begin - ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a1[16] = WDATA_A1_i[16]; - ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a1[17] = WDATA_A1_i[16]; - ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; - ram_wdata_a2[16] = WDATA_A1_i[16]; - ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; - ram_wdata_a2[17] = WDATA_A1_i[16]; - case (bwl) - 0: {ram_be_a2, ram_be_a1} = 4'b0001; - 1: {ram_be_a2, ram_be_a1} = 4'b0010; - 2: {ram_be_a2, ram_be_a1} = 4'b0100; - 3: {ram_be_a2, ram_be_a1} = 4'b1000; - endcase - end - default: begin - ram_wdata_a1 = WDATA_A1_i; - ram_wdata_a2 = WDATA_A1_i; - ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); - ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); - end - endcase - case (WMODE_B1_i) - MODE_36: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); - ram_be_b2 = BE_B2_i; - ram_be_b1 = BE_B1_i; - end - MODE_18: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b1 = BE_B1_i; - ram_be_b2 = BE_B1_i; - end - MODE_9: begin - ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b1[16] = WDATA_B1_i[16]; - ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b1[17] = WDATA_B1_i[16]; - ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; - ram_wdata_b2[16] = WDATA_B1_i[16]; - ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; - ram_wdata_b2[17] = WDATA_B1_i[16]; - case (ADDR_B1_i[4:3]) - 0: {ram_be_b2, ram_be_b1} = 4'b0001; - 1: {ram_be_b2, ram_be_b1} = 4'b0010; - 2: {ram_be_b2, ram_be_b1} = 4'b0100; - 3: {ram_be_b2, ram_be_b1} = 4'b1000; - endcase - end - default: begin - ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); - ram_be_b2 = BE_B1_i; - ram_be_b1 = BE_B1_i; - end - endcase - end - endcase - end - assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); - assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); - assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); - assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); - always @(*) begin : FIFO_READ_SEL - case (RMODE_B1_i) - MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; - MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); - MODE_9: - case (ff_raddr[1:0]) - 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; - 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; - 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; - 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; - endcase - default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; - endcase - end - localparam MODE_1 = 3'b101; - localparam MODE_2 = 3'b110; - localparam MODE_4 = 3'b100; - always @(*) begin : RDATA_SEL - case (SPLIT_i) - 1: begin - RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); - RDATA_B1_o = ram_rdata_b1; - RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); - RDATA_B2_o = ram_rdata_b2; - end - 0: begin - if (FMODE1_i) begin - RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; - RDATA_A2_o = 18'b000000000000000000; - end - else - case (RMODE_A1_i) - MODE_36: begin - RDATA_A1_o = {ram_rdata_a1[17:0]}; - RDATA_A2_o = {ram_rdata_a2[17:0]}; - end - MODE_18: begin - RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); - RDATA_A2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:4] = 14'b00000000000000; - RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); - end - MODE_2: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:2] = 16'b0000000000000000; - RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); - end - MODE_1: begin - RDATA_A2_o = 18'b000000000000000000; - RDATA_A1_o[17:1] = 17'b00000000000000000; - RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); - end - default: begin - RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; - RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; - end - endcase - case (RMODE_B1_i) - MODE_36: begin - RDATA_B1_o = {ram_rdata_b1}; - RDATA_B2_o = {ram_rdata_b2}; - end - MODE_18: begin - RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_9: begin - RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); - RDATA_B2_o = 18'b000000000000000000; - end - MODE_4: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:4] = 14'b00000000000000; - RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); - end - MODE_2: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:2] = 16'b0000000000000000; - RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); - end - MODE_1: begin - RDATA_B2_o = 18'b000000000000000000; - RDATA_B1_o[17:1] = 17'b00000000000000000; - RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); - end - default: begin - RDATA_B1_o = ram_rdata_b1; - RDATA_B2_o = ram_rdata_b2; - end - endcase - end - endcase - end - always @(posedge sclk_a1 or negedge sreset) - if (sreset == 0) - laddr_a1 <= 1'sb0; - else - laddr_a1 <= ADDR_A1_i; - always @(posedge sclk_b1 or negedge sreset) - if (sreset == 0) - laddr_b1 <= 1'sb0; - else - laddr_b1 <= ADDR_B1_i; - assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); - assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); - fifo_ctl #( - .ADDR_WIDTH(12), - .FIFO_WIDTH(3'd4), - .DEPTH(7) - ) fifo36_ctl( - .rclk(sclk_b1), - .rst_R_n(flush1), - .wclk(sclk_a1), - .rst_W_n(flush1), - .ren(REN_B1_i), - .wen(ram_wen_a1), - .sync(SYNC_FIFO1_i), - .rmode(fifo_rmode), - .wmode(fifo_wmode), - .ren_o(ren_o), - .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), - .raddr(ff_raddr), - .waddr(ff_waddr), - .upaf(UPAF1_i), - .upae(UPAE1_i) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF1_i[10:0]), - .UPAE_i(UPAE1_i[10:0]), - .SYNC_FIFO_i(SYNC_FIFO1_i), - .POWERDN_i(POWERDN1_i), - .SLEEP_i(SLEEP1_i), - .PROTECT_i(PROTECT1_i) - )u1( - .RMODE_A_i(ram_rmode_a1), - .RMODE_B_i(ram_rmode_b1), - .WMODE_A_i(ram_wmode_a1), - .WMODE_B_i(ram_wmode_b1), - .WEN_A_i(ram_wen_a1), - .WEN_B_i(ram_wen_b1), - .REN_A_i(ram_ren_a1), - .REN_B_i(ram_ren_b1), - .CLK_A_i(sclk_a1), - .CLK_B_i(sclk_b1), - .BE_A_i(ram_be_a1), - .BE_B_i(ram_be_b1), - .ADDR_A_i(ram_addr_a1), - .ADDR_B_i(ram_addr_b1), - .WDATA_A_i(ram_wdata_a1), - .WDATA_B_i(ram_wdata_b1), - .RDATA_A_o(ram_rdata_a1), - .RDATA_B_o(ram_rdata_b1), - .EMPTY_o(EMPTY1), - .EPO_o(EPO1), - .EWM_o(EWM1), - .UNDERRUN_o(UNDERRUN1), - .FULL_o(FULL1), - .FMO_o(FMO1), - .FWM_o(FWM1), - .OVERRUN_o(OVERRUN1), - .FLUSH_ni(flush1), - .FMODE_i(ram_fmode1) - ); - TDP18K_FIFO #( - .UPAF_i(UPAF2_i), - .UPAE_i(UPAE2_i), - .SYNC_FIFO_i(SYNC_FIFO2_i), - .POWERDN_i(POWERDN2_i), - .SLEEP_i(SLEEP2_i), - .PROTECT_i(PROTECT2_i) - )u2( - .RMODE_A_i(ram_rmode_a2), - .RMODE_B_i(ram_rmode_b2), - .WMODE_A_i(ram_wmode_a2), - .WMODE_B_i(ram_wmode_b2), - .WEN_A_i(ram_wen_a2), - .WEN_B_i(ram_wen_b2), - .REN_A_i(ram_ren_a2), - .REN_B_i(ram_ren_b2), - .CLK_A_i(sclk_a2), - .CLK_B_i(sclk_b2), - .BE_A_i(ram_be_a2), - .BE_B_i(ram_be_b2), - .ADDR_A_i(ram_addr_a2), - .ADDR_B_i(ram_addr_b2), - .WDATA_A_i(ram_wdata_a2), - .WDATA_B_i(ram_wdata_b2), - .RDATA_A_o(ram_rdata_a2), - .RDATA_B_o(ram_rdata_b2), - .EMPTY_o(EMPTY2), - .EPO_o(EPO2), - .EWM_o(EWM2), - .UNDERRUN_o(UNDERRUN2), - .FULL_o(FULL2), - .FMO_o(FMO2), - .FWM_o(FWM2), - .OVERRUN_o(OVERRUN2), - .FLUSH_ni(flush2), - .FMODE_i(ram_fmode2) - ); + parameter [80:0] MODE_BITS = 81'd0; + + // First 18K RAMFIFO (41 bits) + localparam [ 0:0] SYNC_FIFO1_i = MODE_BITS[0]; + localparam [ 2:0] RMODE_A1_i = MODE_BITS[3 : 1]; + localparam [ 2:0] RMODE_B1_i = MODE_BITS[6 : 4]; + localparam [ 2:0] WMODE_A1_i = MODE_BITS[9 : 7]; + localparam [ 2:0] WMODE_B1_i = MODE_BITS[12:10]; + localparam [ 0:0] FMODE1_i = MODE_BITS[13]; + localparam [ 0:0] POWERDN1_i = MODE_BITS[14]; + localparam [ 0:0] SLEEP1_i = MODE_BITS[15]; + localparam [ 0:0] PROTECT1_i = MODE_BITS[16]; + localparam [11:0] UPAE1_i = MODE_BITS[28:17]; + localparam [11:0] UPAF1_i = MODE_BITS[40:29]; + + // Second 18K RAMFIFO (39 bits) + localparam [ 0:0] SYNC_FIFO2_i = MODE_BITS[41]; + localparam [ 2:0] RMODE_A2_i = MODE_BITS[44:42]; + localparam [ 2:0] RMODE_B2_i = MODE_BITS[47:45]; + localparam [ 2:0] WMODE_A2_i = MODE_BITS[50:48]; + localparam [ 2:0] WMODE_B2_i = MODE_BITS[53:51]; + localparam [ 0:0] FMODE2_i = MODE_BITS[54]; + localparam [ 0:0] POWERDN2_i = MODE_BITS[55]; + localparam [ 0:0] SLEEP2_i = MODE_BITS[56]; + localparam [ 0:0] PROTECT2_i = MODE_BITS[57]; + localparam [10:0] UPAE2_i = MODE_BITS[68:58]; + localparam [10:0] UPAF2_i = MODE_BITS[79:69]; + + // Split (1 bit) + localparam [ 0:0] SPLIT_i = MODE_BITS[80]; + + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + input wire RESET_ni; + input wire WEN_A1_i; + input wire WEN_B1_i; + input wire REN_A1_i; + input wire REN_B1_i; + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + input wire [1:0] BE_A1_i; + input wire [1:0] BE_B1_i; + input wire [14:0] ADDR_A1_i; + input wire [14:0] ADDR_B1_i; + input wire [17:0] WDATA_A1_i; + input wire [17:0] WDATA_B1_i; + output reg [17:0] RDATA_A1_o; + output reg [17:0] RDATA_B1_o; + input wire FLUSH1_i; + input wire WEN_A2_i; + input wire WEN_B2_i; + input wire REN_A2_i; + input wire REN_B2_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + input wire [1:0] BE_A2_i; + input wire [1:0] BE_B2_i; + input wire [13:0] ADDR_A2_i; + input wire [13:0] ADDR_B2_i; + input wire [17:0] WDATA_A2_i; + input wire [17:0] WDATA_B2_i; + output reg [17:0] RDATA_A2_o; + output reg [17:0] RDATA_B2_o; + input wire FLUSH2_i; + wire EMPTY2; + wire EPO2; + wire EWM2; + wire FULL2; + wire FMO2; + wire FWM2; + wire EMPTY1; + wire EPO1; + wire EWM1; + wire FULL1; + wire FMO1; + wire FWM1; + wire UNDERRUN1; + wire OVERRUN1; + wire UNDERRUN2; + wire OVERRUN2; + wire UNDERRUN3; + wire OVERRUN3; + wire EMPTY3; + wire EPO3; + wire EWM3; + wire FULL3; + wire FMO3; + wire FWM3; + wire ram_fmode1; + wire ram_fmode2; + wire [17:0] ram_rdata_a1; + wire [17:0] ram_rdata_b1; + wire [17:0] ram_rdata_a2; + wire [17:0] ram_rdata_b2; + reg [17:0] ram_wdata_a1; + reg [17:0] ram_wdata_b1; + reg [17:0] ram_wdata_a2; + reg [17:0] ram_wdata_b2; + reg [14:0] laddr_a1; + reg [14:0] laddr_b1; + wire [13:0] ram_addr_a1; + wire [13:0] ram_addr_b1; + wire [13:0] ram_addr_a2; + wire [13:0] ram_addr_b2; + wire smux_clk_a1; + wire smux_clk_b1; + wire smux_clk_a2; + wire smux_clk_b2; + reg [1:0] ram_be_a1; + reg [1:0] ram_be_a2; + reg [1:0] ram_be_b1; + reg [1:0] ram_be_b2; + wire [2:0] ram_rmode_a1; + wire [2:0] ram_wmode_a1; + wire [2:0] ram_rmode_b1; + wire [2:0] ram_wmode_b1; + wire [2:0] ram_rmode_a2; + wire [2:0] ram_wmode_a2; + wire [2:0] ram_rmode_b2; + wire [2:0] ram_wmode_b2; + wire ram_ren_a1; + wire ram_ren_b1; + wire ram_ren_a2; + wire ram_ren_b2; + wire ram_wen_a1; + wire ram_wen_b1; + wire ram_wen_a2; + wire ram_wen_b2; + wire ren_o; + wire [11:0] ff_raddr; + wire [11:0] ff_waddr; + reg [35:0] fifo_rdata; + wire [1:0] fifo_rmode; + wire [1:0] fifo_wmode; + wire [1:0] bwl; + wire [17:0] pl_dout0; + wire [17:0] pl_dout1; + wire sclk_a1; + wire sclk_b1; + wire sclk_a2; + wire sclk_b2; + wire sreset; + wire flush1; + wire flush2; + assign sreset = RESET_ni; + assign flush1 = ~FLUSH1_i; + assign flush2 = ~FLUSH2_i; + assign ram_fmode1 = FMODE1_i & SPLIT_i; + assign ram_fmode2 = FMODE2_i & SPLIT_i; + assign smux_clk_a1 = CLK_A1_i; + assign smux_clk_b1 = (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i); + assign smux_clk_a2 = (SPLIT_i ? CLK_A2_i : CLK_A1_i); + assign smux_clk_b2 = (SPLIT_i ? (FMODE2_i ? (SYNC_FIFO2_i ? CLK_A2_i : CLK_B2_i) : CLK_B2_i) : (FMODE1_i ? (SYNC_FIFO1_i ? CLK_A1_i : CLK_B1_i) : CLK_B1_i)); + assign sclk_a1 = smux_clk_a1; + assign sclk_a2 = smux_clk_a2; + assign sclk_b1 = smux_clk_b1; + assign sclk_b2 = smux_clk_b2; + assign ram_ren_a1 = (SPLIT_i ? REN_A1_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_a2 = (SPLIT_i ? REN_A2_i : (FMODE1_i ? 0 : REN_A1_i)); + assign ram_ren_b1 = (SPLIT_i ? REN_B1_i : (FMODE1_i ? ren_o : REN_B1_i)); + assign ram_ren_b2 = (SPLIT_i ? REN_B2_i : (FMODE1_i ? ren_o : REN_B1_i)); + localparam MODE_36 = 3'b011; + assign ram_wen_a1 = (SPLIT_i ? WEN_A1_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ~ADDR_A1_i[4]))); + assign ram_wen_a2 = (SPLIT_i ? WEN_A2_i : (FMODE1_i ? ~FULL3 & WEN_A1_i : (WMODE_A1_i == MODE_36 ? WEN_A1_i : WEN_A1_i & ADDR_A1_i[4]))); + assign ram_wen_b1 = (SPLIT_i ? WEN_B1_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ~ADDR_B1_i[4])); + assign ram_wen_b2 = (SPLIT_i ? WEN_B2_i : (WMODE_B1_i == MODE_36 ? WEN_B1_i : WEN_B1_i & ADDR_B1_i[4])); + assign ram_addr_a1 = (SPLIT_i ? ADDR_A1_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b1 = (SPLIT_i ? ADDR_B1_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign ram_addr_a2 = (SPLIT_i ? ADDR_A2_i[13:0] : (FMODE1_i ? {ff_waddr[11:2], ff_waddr[0], 3'b000} : {ADDR_A1_i[14:5], ADDR_A1_i[3:0]})); + assign ram_addr_b2 = (SPLIT_i ? ADDR_B2_i[13:0] : (FMODE1_i ? {ff_raddr[11:2], ff_raddr[0], 3'b000} : {ADDR_B1_i[14:5], ADDR_B1_i[3:0]})); + assign bwl = (SPLIT_i ? ADDR_A1_i[4:3] : (FMODE1_i ? ff_waddr[1:0] : ADDR_A1_i[4:3])); + localparam MODE_18 = 3'b010; + localparam MODE_9 = 3'b001; + always @(*) begin : WDATA_SEL + case (SPLIT_i) + 1: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_wdata_b1 = WDATA_B1_i; + ram_wdata_b2 = WDATA_B2_i; + ram_be_a2 = BE_A2_i; + ram_be_b2 = BE_B2_i; + ram_be_a1 = BE_A1_i; + ram_be_b1 = BE_B1_i; + end + 0: begin + case (WMODE_A1_i) + MODE_36: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A2_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A2_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + MODE_18: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a1 = (FMODE1_i ? (ff_waddr[1] ? 2'b00 : 2'b11) : BE_A1_i); + ram_be_a2 = (FMODE1_i ? (ff_waddr[1] ? 2'b11 : 2'b00) : BE_A1_i); + end + MODE_9: begin + ram_wdata_a1[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a1[16] = WDATA_A1_i[16]; + ram_wdata_a1[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a1[17] = WDATA_A1_i[16]; + ram_wdata_a2[7:0] = WDATA_A1_i[7:0]; + ram_wdata_a2[16] = WDATA_A1_i[16]; + ram_wdata_a2[15:8] = WDATA_A1_i[7:0]; + ram_wdata_a2[17] = WDATA_A1_i[16]; + case (bwl) + 0: {ram_be_a2, ram_be_a1} = 4'b0001; + 1: {ram_be_a2, ram_be_a1} = 4'b0010; + 2: {ram_be_a2, ram_be_a1} = 4'b0100; + 3: {ram_be_a2, ram_be_a1} = 4'b1000; + endcase + end + default: begin + ram_wdata_a1 = WDATA_A1_i; + ram_wdata_a2 = WDATA_A1_i; + ram_be_a2 = (FMODE1_i ? 2'b11 : BE_A1_i); + ram_be_a1 = (FMODE1_i ? 2'b11 : BE_A1_i); + end + endcase + case (WMODE_B1_i) + MODE_36: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B2_i); + ram_be_b2 = BE_B2_i; + ram_be_b1 = BE_B1_i; + end + MODE_18: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b1 = BE_B1_i; + ram_be_b2 = BE_B1_i; + end + MODE_9: begin + ram_wdata_b1[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b1[16] = WDATA_B1_i[16]; + ram_wdata_b1[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b1[17] = WDATA_B1_i[16]; + ram_wdata_b2[7:0] = WDATA_B1_i[7:0]; + ram_wdata_b2[16] = WDATA_B1_i[16]; + ram_wdata_b2[15:8] = WDATA_B1_i[7:0]; + ram_wdata_b2[17] = WDATA_B1_i[16]; + case (ADDR_B1_i[4:3]) + 0: {ram_be_b2, ram_be_b1} = 4'b0001; + 1: {ram_be_b2, ram_be_b1} = 4'b0010; + 2: {ram_be_b2, ram_be_b1} = 4'b0100; + 3: {ram_be_b2, ram_be_b1} = 4'b1000; + endcase + end + default: begin + ram_wdata_b1 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_wdata_b2 = (FMODE1_i ? 18'b000000000000000000 : WDATA_B1_i); + ram_be_b2 = BE_B1_i; + ram_be_b1 = BE_B1_i; + end + endcase + end + endcase + end + assign ram_rmode_a1 = (SPLIT_i ? (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_rmode_a2 = (SPLIT_i ? (RMODE_A2_i == MODE_36 ? MODE_18 : RMODE_A2_i) : (RMODE_A1_i == MODE_36 ? MODE_18 : RMODE_A1_i)); + assign ram_wmode_a1 = (SPLIT_i ? (WMODE_A1_i == MODE_36 ? MODE_18 : WMODE_A1_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_wmode_a2 = (SPLIT_i ? (WMODE_A2_i == MODE_36 ? MODE_18 : WMODE_A2_i) : (WMODE_A1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : WMODE_A1_i))); + assign ram_rmode_b1 = (SPLIT_i ? (RMODE_B1_i == MODE_36 ? MODE_18 : RMODE_B1_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_rmode_b2 = (SPLIT_i ? (RMODE_B2_i == MODE_36 ? MODE_18 : RMODE_B2_i) : (RMODE_B1_i == MODE_36 ? MODE_18 : (FMODE1_i ? MODE_18 : RMODE_B1_i))); + assign ram_wmode_b1 = (SPLIT_i ? (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + assign ram_wmode_b2 = (SPLIT_i ? (WMODE_B2_i == MODE_36 ? MODE_18 : WMODE_B2_i) : (WMODE_B1_i == MODE_36 ? MODE_18 : WMODE_B1_i)); + always @(*) begin : FIFO_READ_SEL + case (RMODE_B1_i) + MODE_36: fifo_rdata = {ram_rdata_b2[17:16], ram_rdata_b1[17:16], ram_rdata_b2[15:0], ram_rdata_b1[15:0]}; + MODE_18: fifo_rdata = (ff_raddr[1] ? {18'b000000000000000000, ram_rdata_b2} : {18'b000000000000000000, ram_rdata_b1}); + MODE_9: + case (ff_raddr[1:0]) + 0: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]}; + 1: fifo_rdata = {19'b0000000000000000000, ram_rdata_b1[17], 8'b00000000, ram_rdata_b1[15:8]}; + 2: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]}; + 3: fifo_rdata = {19'b0000000000000000000, ram_rdata_b2[17], 8'b00000000, ram_rdata_b2[15:8]}; + endcase + default: fifo_rdata = {ram_rdata_b2, ram_rdata_b1}; + endcase + end + localparam MODE_1 = 3'b101; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : RDATA_SEL + case (SPLIT_i) + 1: begin + RDATA_A1_o = (FMODE1_i ? {10'b0000000000, EMPTY1, EPO1, EWM1, UNDERRUN1, FULL1, FMO1, FWM1, OVERRUN1} : ram_rdata_a1); + RDATA_B1_o = ram_rdata_b1; + RDATA_A2_o = (FMODE2_i ? {10'b0000000000, EMPTY2, EPO2, EWM2, UNDERRUN2, FULL2, FMO2, FWM2, OVERRUN2} : ram_rdata_a2); + RDATA_B2_o = ram_rdata_b2; + end + 0: begin + if (FMODE1_i) begin + RDATA_A1_o = {10'b0000000000, EMPTY3, EPO3, EWM3, UNDERRUN3, FULL3, FMO3, FWM3, OVERRUN3}; + RDATA_A2_o = 18'b000000000000000000; + end + else + case (RMODE_A1_i) + MODE_36: begin + RDATA_A1_o = {ram_rdata_a1[17:0]}; + RDATA_A2_o = {ram_rdata_a2[17:0]}; + end + MODE_18: begin + RDATA_A1_o = (laddr_a1[4] ? ram_rdata_a2 : ram_rdata_a1); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_A1_o = (laddr_a1[4] ? {{2 {ram_rdata_a2[16]}}, {2 {ram_rdata_a2[7:0]}}} : {{2 {ram_rdata_a1[16]}}, {2 {ram_rdata_a1[7:0]}}}); + RDATA_A2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:4] = 14'b00000000000000; + RDATA_A1_o[3:0] = (laddr_a1[4] ? ram_rdata_a2[3:0] : ram_rdata_a1[3:0]); + end + MODE_2: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:2] = 16'b0000000000000000; + RDATA_A1_o[1:0] = (laddr_a1[4] ? ram_rdata_a2[1:0] : ram_rdata_a1[1:0]); + end + MODE_1: begin + RDATA_A2_o = 18'b000000000000000000; + RDATA_A1_o[17:1] = 17'b00000000000000000; + RDATA_A1_o[0] = (laddr_a1[4] ? ram_rdata_a2[0] : ram_rdata_a1[0]); + end + default: begin + RDATA_A1_o = {ram_rdata_a2[1:0], ram_rdata_a1[15:0]}; + RDATA_A2_o = {ram_rdata_a2[17:16], ram_rdata_a1[17:16], ram_rdata_a2[15:2]}; + end + endcase + case (RMODE_B1_i) + MODE_36: begin + RDATA_B1_o = {ram_rdata_b1}; + RDATA_B2_o = {ram_rdata_b2}; + end + MODE_18: begin + RDATA_B1_o = (FMODE1_i ? fifo_rdata[17:0] : (laddr_b1[4] ? ram_rdata_b2 : ram_rdata_b1)); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_9: begin + RDATA_B1_o = (FMODE1_i ? {fifo_rdata[17:0]} : (laddr_b1[4] ? {1'b0, ram_rdata_b2[16], 8'b00000000, ram_rdata_b2[7:0]} : {1'b0, ram_rdata_b1[16], 8'b00000000, ram_rdata_b1[7:0]})); + RDATA_B2_o = 18'b000000000000000000; + end + MODE_4: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:4] = 14'b00000000000000; + RDATA_B1_o[3:0] = (laddr_b1[4] ? ram_rdata_b2[3:0] : ram_rdata_b1[3:0]); + end + MODE_2: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:2] = 16'b0000000000000000; + RDATA_B1_o[1:0] = (laddr_b1[4] ? ram_rdata_b2[1:0] : ram_rdata_b1[1:0]); + end + MODE_1: begin + RDATA_B2_o = 18'b000000000000000000; + RDATA_B1_o[17:1] = 17'b00000000000000000; + RDATA_B1_o[0] = (laddr_b1[4] ? ram_rdata_b2[0] : ram_rdata_b1[0]); + end + default: begin + RDATA_B1_o = ram_rdata_b1; + RDATA_B2_o = ram_rdata_b2; + end + endcase + end + endcase + end + always @(posedge sclk_a1 or negedge sreset) + if (sreset == 0) + laddr_a1 <= 1'sb0; + else + laddr_a1 <= ADDR_A1_i; + always @(posedge sclk_b1 or negedge sreset) + if (sreset == 0) + laddr_b1 <= 1'sb0; + else + laddr_b1 <= ADDR_B1_i; + assign fifo_wmode = ((WMODE_A1_i == MODE_36) ? 2'b00 : ((WMODE_A1_i == MODE_18) ? 2'b01 : ((WMODE_A1_i == MODE_9) ? 2'b10 : 2'b00))); + assign fifo_rmode = ((RMODE_B1_i == MODE_36) ? 2'b00 : ((RMODE_B1_i == MODE_18) ? 2'b01 : ((RMODE_B1_i == MODE_9) ? 2'b10 : 2'b00))); + fifo_ctl #( + .ADDR_WIDTH(12), + .FIFO_WIDTH(3'd4), + .DEPTH(7) + ) fifo36_ctl( + .rclk(sclk_b1), + .rst_R_n(flush1), + .wclk(sclk_a1), + .rst_W_n(flush1), + .ren(REN_B1_i), + .wen(ram_wen_a1), + .sync(SYNC_FIFO1_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL3, FMO3, FWM3, OVERRUN3, EMPTY3, EPO3, EWM3, UNDERRUN3}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF1_i), + .upae(UPAE1_i) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF1_i[10:0]), + .UPAE_i(UPAE1_i[10:0]), + .SYNC_FIFO_i(SYNC_FIFO1_i), + .POWERDN_i(POWERDN1_i), + .SLEEP_i(SLEEP1_i), + .PROTECT_i(PROTECT1_i) + )u1( + .RMODE_A_i(ram_rmode_a1), + .RMODE_B_i(ram_rmode_b1), + .WMODE_A_i(ram_wmode_a1), + .WMODE_B_i(ram_wmode_b1), + .WEN_A_i(ram_wen_a1), + .WEN_B_i(ram_wen_b1), + .REN_A_i(ram_ren_a1), + .REN_B_i(ram_ren_b1), + .CLK_A_i(sclk_a1), + .CLK_B_i(sclk_b1), + .BE_A_i(ram_be_a1), + .BE_B_i(ram_be_b1), + .ADDR_A_i(ram_addr_a1), + .ADDR_B_i(ram_addr_b1), + .WDATA_A_i(ram_wdata_a1), + .WDATA_B_i(ram_wdata_b1), + .RDATA_A_o(ram_rdata_a1), + .RDATA_B_o(ram_rdata_b1), + .EMPTY_o(EMPTY1), + .EPO_o(EPO1), + .EWM_o(EWM1), + .UNDERRUN_o(UNDERRUN1), + .FULL_o(FULL1), + .FMO_o(FMO1), + .FWM_o(FWM1), + .OVERRUN_o(OVERRUN1), + .FLUSH_ni(flush1), + .FMODE_i(ram_fmode1) + ); + TDP18K_FIFO #( + .UPAF_i(UPAF2_i), + .UPAE_i(UPAE2_i), + .SYNC_FIFO_i(SYNC_FIFO2_i), + .POWERDN_i(POWERDN2_i), + .SLEEP_i(SLEEP2_i), + .PROTECT_i(PROTECT2_i) + )u2( + .RMODE_A_i(ram_rmode_a2), + .RMODE_B_i(ram_rmode_b2), + .WMODE_A_i(ram_wmode_a2), + .WMODE_B_i(ram_wmode_b2), + .WEN_A_i(ram_wen_a2), + .WEN_B_i(ram_wen_b2), + .REN_A_i(ram_ren_a2), + .REN_B_i(ram_ren_b2), + .CLK_A_i(sclk_a2), + .CLK_B_i(sclk_b2), + .BE_A_i(ram_be_a2), + .BE_B_i(ram_be_b2), + .ADDR_A_i(ram_addr_a2), + .ADDR_B_i(ram_addr_b2), + .WDATA_A_i(ram_wdata_a2), + .WDATA_B_i(ram_wdata_b2), + .RDATA_A_o(ram_rdata_a2), + .RDATA_B_o(ram_rdata_b2), + .EMPTY_o(EMPTY2), + .EPO_o(EPO2), + .EWM_o(EWM2), + .UNDERRUN_o(UNDERRUN2), + .FULL_o(FULL2), + .FMO_o(FMO2), + .FWM_o(FWM2), + .OVERRUN_o(OVERRUN2), + .FLUSH_ni(flush2), + .FMODE_i(ram_fmode2) + ); endmodule module RAM_18K_X2_BLK ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -810,10 +810,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -834,12 +834,12 @@ localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -864,12 +864,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -894,12 +894,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -924,12 +924,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -982,55 +982,55 @@ assign BE_A2_i = WR2_BE; assign REN_B1_i = REN1_i; assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; +assign BE_B1_i = 2'h0; assign REN_B2_i = REN2_i; assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; +assign BE_B2_i = 2'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -1088,27 +1088,27 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o ); parameter WR1_ADDR_WIDTH = 10; @@ -1222,10 +1222,10 @@ wire [17:0] PORT_B2_RDATA; wire [17:0] PORT_A2_WDATA; wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -1246,12 +1246,12 @@ localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end endgenerate case (WR1_DATA_WIDTH) @@ -1276,12 +1276,12 @@ case (WR1_DATA_WIDTH) endcase generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end endgenerate case (RD1_DATA_WIDTH) @@ -1306,12 +1306,12 @@ case (RD1_DATA_WIDTH) endcase generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end endgenerate case (WR2_DATA_WIDTH) @@ -1336,12 +1336,12 @@ case (WR2_DATA_WIDTH) endcase generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end endgenerate case (RD2_DATA_WIDTH) @@ -1394,55 +1394,55 @@ assign BE_A2_i = WR2_BE; assign REN_B1_i = REN1_i; assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; +assign BE_B1_i = 2'h0; assign REN_B2_i = REN2_i; assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; +assign BE_B2_i = 2'h0; generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA[17:0]; assign WDATA_B1_i = 18'h0; generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA[17:0]; assign WDATA_B2_i = 18'h0; generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; @@ -1498,15 +1498,15 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module RAM_18K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -1525,56 +1525,56 @@ input wire [RD_ADDR_WIDTH-1 :0] RD_ADDR_i; input wire [WR_DATA_WIDTH-1 :0] WDATA_i; output wire [RD_DATA_WIDTH-1 :0] RDATA_o; - (* is_inferred = 0 *) - (* is_split = 0 *) - BRAM2x18_SP #( - .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), - .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .BE1_WIDTH(BE_WIDTH), - .WR2_ADDR_WIDTH(), - .RD2_ADDR_WIDTH(), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .BE2_WIDTH() - ) U1 - ( - .RESET_ni(1'b1), - - .WEN1_i(WEN_i), - .REN1_i(REN_i), - .WR1_CLK_i(WR_CLK_i), - .RD1_CLK_i(RD_CLK_i), - .WR1_BE_i(WR_BE_i), - .WR1_ADDR_i(WR_ADDR_i), - .RD1_ADDR_i(RD_ADDR_i), - .WDATA1_i(WDATA_i), - .RDATA1_o(RDATA_o), - - .WEN2_i(1'b0), - .REN2_i(1'b0), - .WR2_CLK_i(1'b0), - .RD2_CLK_i(1'b0), - .WR2_BE_i(2'b00), - .WR2_ADDR_i(14'h0), - .RD2_ADDR_i(14'h0), - .WDATA2_i(18'h0), - .RDATA2_o() - ); - + (* is_inferred = 0 *) + (* is_split = 0 *) + BRAM2x18_SP #( + .WR1_ADDR_WIDTH(WR_ADDR_WIDTH), + .RD1_ADDR_WIDTH(RD_ADDR_WIDTH), + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .BE1_WIDTH(BE_WIDTH), + .WR2_ADDR_WIDTH(), + .RD2_ADDR_WIDTH(), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .BE2_WIDTH() + ) U1 + ( + .RESET_ni(1'b1), + + .WEN1_i(WEN_i), + .REN1_i(REN_i), + .WR1_CLK_i(WR_CLK_i), + .RD1_CLK_i(RD_CLK_i), + .WR1_BE_i(WR_BE_i), + .WR1_ADDR_i(WR_ADDR_i), + .RD1_ADDR_i(RD_ADDR_i), + .WDATA1_i(WDATA_i), + .RDATA1_o(RDATA_o), + + .WEN2_i(1'b0), + .REN2_i(1'b0), + .WR2_CLK_i(1'b0), + .RD2_CLK_i(1'b0), + .WR2_BE_i(2'b00), + .WR2_ADDR_i(14'h0), + .RD2_ADDR_i(14'h0), + .WDATA2_i(18'h0), + .RDATA2_o() + ); + endmodule module RAM_36K_BLK ( - WEN_i, - REN_i, - WR_CLK_i, - RD_CLK_i, - WR_BE_i, - WR_ADDR_i, - RD_ADDR_i, - WDATA_i, - RDATA_o + WEN_i, + REN_i, + WR_CLK_i, + RD_CLK_i, + WR_BE_i, + WR_ADDR_i, + RD_ADDR_i, + WDATA_i, + RDATA_o ); parameter WR_ADDR_WIDTH = 10; @@ -1668,7 +1668,7 @@ wire [35:0] PORT_B_RDATA; wire [35:0] PORT_A_WDATA; wire [14:0] WR_ADDR_INT; -wire [14:0] RD_ADDR_INT; +wire [14:0] RD_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -1691,12 +1691,12 @@ assign PORT_A_CLK = WR_CLK_i; assign PORT_B_CLK = RD_CLK_i; generate - if (WR_ADDR_WIDTH == 15) begin - assign WR_ADDR_INT = WR_ADDR_i; - end else begin - assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; - assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; - end + if (WR_ADDR_WIDTH == 15) begin + assign WR_ADDR_INT = WR_ADDR_i; + end else begin + assign WR_ADDR_INT[14:WR_ADDR_WIDTH] = 0; + assign WR_ADDR_INT[WR_ADDR_WIDTH-1:0] = WR_ADDR_i; + end endgenerate case (WR_DATA_WIDTH) @@ -1724,12 +1724,12 @@ case (WR_DATA_WIDTH) endcase generate - if (RD_ADDR_WIDTH == 15) begin - assign RD_ADDR_INT = RD_ADDR_i; - end else begin - assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; - assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; - end + if (RD_ADDR_WIDTH == 15) begin + assign RD_ADDR_INT = RD_ADDR_i; + end else begin + assign RD_ADDR_INT[14:RD_ADDR_WIDTH] = 0; + assign RD_ADDR_INT[RD_ADDR_WIDTH-1:0] = RD_ADDR_i; + end endgenerate case (RD_DATA_WIDTH) @@ -1775,17 +1775,17 @@ assign WEN_B1_i = 1'b0; assign {BE_B2_i, BE_B1_i} = 4'h0; generate - if (WR_DATA_WIDTH == 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; - assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; - end + if (WR_DATA_WIDTH == 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign PORT_A_WDATA[WR_DATA_WIDTH+1:18] = WDATA_i[WR_DATA_WIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,WDATA_i[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, WDATA_i[8], 8'h0, WDATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:WR_DATA_WIDTH] = 0; + assign PORT_A_WDATA[WR_DATA_WIDTH-1:0] = WDATA_i[WR_DATA_WIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; @@ -1795,15 +1795,15 @@ assign WDATA_B1_i = 18'h0; assign WDATA_B2_i = 18'h0; generate - if (RD_DATA_WIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (RD_DATA_WIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign RDATA_o = PORT_B_RDATA[RD_DATA_WIDTH-1:0]; @@ -1859,44 +1859,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_X2_BLK ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module DPRAM_18K_X2_BLK ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -1904,7 +1904,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -2027,11 +2027,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -2062,12 +2062,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -2092,12 +2092,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -2122,12 +2122,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -2152,12 +2152,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -2238,93 +2238,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -2381,44 +2381,44 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o ); parameter PORT_A1_AWIDTH = 10; parameter PORT_A1_DWIDTH = 18; parameter PORT_A1_WR_BE_WIDTH = 2; - + parameter PORT_B1_AWIDTH = 10; parameter PORT_B1_DWIDTH = 18; parameter PORT_B1_WR_BE_WIDTH = 2; @@ -2426,7 +2426,7 @@ parameter PORT_B1_WR_BE_WIDTH = 2; parameter PORT_A2_AWIDTH = 10; parameter PORT_A2_DWIDTH = 18; parameter PORT_A2_WR_BE_WIDTH = 2; - + parameter PORT_B2_AWIDTH = 10; parameter PORT_B2_DWIDTH = 18; parameter PORT_B2_WR_BE_WIDTH = 2; @@ -2548,11 +2548,11 @@ wire [17:0] PORT_A2_WDATA; wire [17:0] PORT_A2_RDATA; wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - +wire [13:0] PORT_B2_ADDR_INT; + wire [13:0] PORT_A1_ADDR; wire [13:0] PORT_B1_ADDR; @@ -2583,12 +2583,12 @@ assign PORT_A2_CLK = PORT_A2_CLK_i; assign PORT_B2_CLK = PORT_B2_CLK_i; generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end endgenerate case (PORT_A1_DWIDTH) @@ -2613,12 +2613,12 @@ case (PORT_A1_DWIDTH) endcase generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end endgenerate case (PORT_B1_DWIDTH) @@ -2643,12 +2643,12 @@ case (PORT_B1_DWIDTH) endcase generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end endgenerate case (PORT_A2_DWIDTH) @@ -2673,12 +2673,12 @@ case (PORT_A2_DWIDTH) endcase generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end endgenerate case (PORT_B2_DWIDTH) @@ -2759,93 +2759,93 @@ assign WEN_B2_i = PORT_B2_WEN_i; assign BE_B2_i = PORT_B2_WR_BE; generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A1_WDATA; generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end endgenerate assign WDATA_A2_i = PORT_A2_WDATA; generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end endgenerate assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end endgenerate assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B1_WDATA; generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end endgenerate assign WDATA_B2_i = PORT_B2_WDATA; generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end endgenerate assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end endgenerate assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; @@ -2900,22 +2900,22 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule -module DPRAM_18K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_18K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -2959,57 +2959,57 @@ BRAM2x18_dP #( .PORT_B2_DWIDTH(), .PORT_B2_WR_BE_WIDTH() ) U1 ( - .PORT_A1_CLK_i(PORT_A_CLK_i), - .PORT_A1_WEN_i(PORT_A_WEN_i), - .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), - .PORT_A1_REN_i(PORT_A_REN_i), - .PORT_A1_ADDR_i(PORT_A_ADDR_i), - .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), - .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), - - .PORT_B1_CLK_i(PORT_B_CLK_i), - .PORT_B1_WEN_i(PORT_B_WEN_i), - .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), - .PORT_B1_REN_i(PORT_B_REN_i), - .PORT_B1_ADDR_i(PORT_B_ADDR_i), - .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), - .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), - - .PORT_A2_CLK_i(1'b0), - .PORT_A2_WEN_i(1'b0), - .PORT_A2_WR_BE_i(2'b00), - .PORT_A2_REN_i(1'b0), - .PORT_A2_ADDR_i(14'h0), - .PORT_A2_WR_DATA_i(18'h0), - .PORT_A2_RD_DATA_o(), - - .PORT_B2_CLK_i(1'b0), - .PORT_B2_WEN_i(1'b0), - .PORT_B2_WR_BE_i(2'b00), - .PORT_B2_REN_i(1'b0), - .PORT_B2_ADDR_i(14'h0), - .PORT_B2_WR_DATA_i(18'h0), - .PORT_B2_RD_DATA_o() + .PORT_A1_CLK_i(PORT_A_CLK_i), + .PORT_A1_WEN_i(PORT_A_WEN_i), + .PORT_A1_WR_BE_i(PORT_A_WR_BE_i), + .PORT_A1_REN_i(PORT_A_REN_i), + .PORT_A1_ADDR_i(PORT_A_ADDR_i), + .PORT_A1_WR_DATA_i(PORT_A_WR_DATA_i), + .PORT_A1_RD_DATA_o(PORT_A_RD_DATA_o), + + .PORT_B1_CLK_i(PORT_B_CLK_i), + .PORT_B1_WEN_i(PORT_B_WEN_i), + .PORT_B1_WR_BE_i(PORT_B_WR_BE_i), + .PORT_B1_REN_i(PORT_B_REN_i), + .PORT_B1_ADDR_i(PORT_B_ADDR_i), + .PORT_B1_WR_DATA_i(PORT_B_WR_DATA_i), + .PORT_B1_RD_DATA_o(PORT_B_RD_DATA_o), + + .PORT_A2_CLK_i(1'b0), + .PORT_A2_WEN_i(1'b0), + .PORT_A2_WR_BE_i(2'b00), + .PORT_A2_REN_i(1'b0), + .PORT_A2_ADDR_i(14'h0), + .PORT_A2_WR_DATA_i(18'h0), + .PORT_A2_RD_DATA_o(), + + .PORT_B2_CLK_i(1'b0), + .PORT_B2_WEN_i(1'b0), + .PORT_B2_WR_BE_i(2'b00), + .PORT_B2_REN_i(1'b0), + .PORT_B2_ADDR_i(14'h0), + .PORT_B2_WR_DATA_i(18'h0), + .PORT_B2_RD_DATA_o() ); endmodule -module DPRAM_36K_BLK ( - PORT_A_CLK_i, - PORT_A_WEN_i, - PORT_A_WR_BE_i, - PORT_A_REN_i, - PORT_A_ADDR_i, - PORT_A_WR_DATA_i, - PORT_A_RD_DATA_o, - - PORT_B_CLK_i, - PORT_B_WEN_i, - PORT_B_WR_BE_i, - PORT_B_REN_i, - PORT_B_ADDR_i, - PORT_B_WR_DATA_i, - PORT_B_RD_DATA_o +module DPRAM_36K_BLK ( + PORT_A_CLK_i, + PORT_A_WEN_i, + PORT_A_WR_BE_i, + PORT_A_REN_i, + PORT_A_ADDR_i, + PORT_A_WR_DATA_i, + PORT_A_RD_DATA_o, + + PORT_B_CLK_i, + PORT_B_WEN_i, + PORT_B_WR_BE_i, + PORT_B_REN_i, + PORT_B_ADDR_i, + PORT_B_WR_DATA_i, + PORT_B_RD_DATA_o ); parameter PORT_A_AWIDTH = 10; @@ -3113,7 +3113,7 @@ wire [35:0] PORT_A_WDATA; wire [35:0] PORT_A_RDATA; wire [14:0] PORT_A_ADDR_INT; -wire [14:0] PORT_B_ADDR_INT; +wire [14:0] PORT_B_ADDR_INT; wire [14:0] PORT_A_ADDR; wire [14:0] PORT_B_ADDR; @@ -3136,12 +3136,12 @@ assign PORT_A_CLK = PORT_A_CLK_i; assign PORT_B_CLK = PORT_B_CLK_i; generate - if (PORT_A_AWIDTH == 15) begin - assign PORT_A_ADDR_INT = PORT_A_ADDR_i; - end else begin - assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; - assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; - end + if (PORT_A_AWIDTH == 15) begin + assign PORT_A_ADDR_INT = PORT_A_ADDR_i; + end else begin + assign PORT_A_ADDR_INT[14:PORT_A_AWIDTH] = 0; + assign PORT_A_ADDR_INT[PORT_A_AWIDTH-1:0] = PORT_A_ADDR_i; + end endgenerate case (PORT_A_DWIDTH) @@ -3169,12 +3169,12 @@ case (PORT_A_DWIDTH) endcase generate - if (PORT_B_AWIDTH == 15) begin - assign PORT_B_ADDR_INT = PORT_B_ADDR_i; - end else begin - assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; - assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; - end + if (PORT_B_AWIDTH == 15) begin + assign PORT_B_ADDR_INT = PORT_B_ADDR_i; + end else begin + assign PORT_B_ADDR_INT[14:PORT_B_AWIDTH] = 0; + assign PORT_B_ADDR_INT[PORT_B_AWIDTH-1:0] = PORT_B_ADDR_i; + end endgenerate case (PORT_B_DWIDTH) @@ -3230,63 +3230,63 @@ assign WEN_B1_i = PORT_B_WEN_i; assign {BE_B2_i, BE_B1_i} = PORT_B_WR_BE; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; - assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; - end else begin - assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; - assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_WDATA[PORT_A_DWIDTH+1:18] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:16]; + assign PORT_A_WDATA[17:0] = {2'b00,PORT_A_WR_DATA_i[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_WDATA = {19'h0, PORT_A_WR_DATA_i[8], 8'h0, PORT_A_WR_DATA_i[7:0]}; + end else begin + assign PORT_A_WDATA[35:PORT_A_DWIDTH] = 0; + assign PORT_A_WDATA[PORT_A_DWIDTH-1:0] = PORT_A_WR_DATA_i[PORT_A_DWIDTH-1:0]; + end endgenerate assign WDATA_A1_i = PORT_A_WDATA[17:0]; assign WDATA_A2_i = PORT_A_WDATA[35:18]; generate - if (PORT_A_DWIDTH == 36) begin - assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; - end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin - assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; - end else if (PORT_A_DWIDTH == 9) begin - assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; - end + if (PORT_A_DWIDTH == 36) begin + assign PORT_A_RDATA = {RDATA_A2_o, RDATA_A1_o}; + end else if (PORT_A_DWIDTH > 18 && PORT_A_DWIDTH < 36) begin + assign PORT_A_RDATA = {2'b00,RDATA_A2_o[17:0],RDATA_A1_o[15:0]}; + end else if (PORT_A_DWIDTH == 9) begin + assign PORT_A_RDATA = { 27'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A_RDATA = {18'h0, RDATA_A1_o}; + end endgenerate assign PORT_A_RD_DATA_o = PORT_A_RDATA[PORT_A_DWIDTH-1:0]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; - assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; - end else begin - assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; - assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_WDATA[PORT_B_DWIDTH+1:18] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:16]; + assign PORT_B_WDATA[17:0] = {2'b00,PORT_B_WR_DATA_i[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_WDATA = {19'h0, PORT_B_WR_DATA_i[8], 8'h0, PORT_B_WR_DATA_i[7:0]}; + end else begin + assign PORT_B_WDATA[35:PORT_B_DWIDTH] = 0; + assign PORT_B_WDATA[PORT_B_DWIDTH-1:0] = PORT_B_WR_DATA_i[PORT_B_DWIDTH-1:0]; + end endgenerate assign WDATA_B1_i = PORT_B_WDATA[17:0]; assign WDATA_B2_i = PORT_B_WDATA[35:18]; generate - if (PORT_B_DWIDTH == 36) begin - assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; - end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin - assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; - end else if (PORT_B_DWIDTH == 9) begin - assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; - end + if (PORT_B_DWIDTH == 36) begin + assign PORT_B_RDATA = {RDATA_B2_o, RDATA_B1_o}; + end else if (PORT_B_DWIDTH > 18 && PORT_B_DWIDTH < 36) begin + assign PORT_B_RDATA = {2'b00,RDATA_B2_o[17:0],RDATA_B1_o[15:0]}; + end else if (PORT_B_DWIDTH == 9) begin + assign PORT_B_RDATA = { 27'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B_RDATA = {18'h0, RDATA_B1_o}; + end endgenerate assign PORT_B_RD_DATA_o = PORT_B_RDATA[PORT_B_DWIDTH-1:0]; @@ -3342,192 +3342,192 @@ TDP36K _TECHMAP_REPLACE_ ( endmodule module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire CLK1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire CLK2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = WR1_DATA_WIDTH *) - (* port_b_dwidth = RD1_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -3567,270 +3567,270 @@ module BRAM2x18_SFIFO ( endmodule module SFIFO_18K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_SFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .CLK1(CLK), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .CLK2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .CLK1(CLK), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .CLK2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module SFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire CLK1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire CLK2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire CLK1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire CLK2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = WR1_DATA_WIDTH *) - (* port_a2_dwidth = WR2_DATA_WIDTH *) - (* port_b1_dwidth = RD1_DATA_WIDTH *) - (* port_b2_dwidth = RD2_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -3871,187 +3871,187 @@ endmodule module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire Push_Clk1, Pop_Clk1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire Push_Clk2, Pop_Clk2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = WR1_DATA_WIDTH *) - (* port_b_dwidth = RD1_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = WR1_DATA_WIDTH *) + (* port_b_dwidth = RD1_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -4091,268 +4091,268 @@ module BRAM2x18_AFIFO ( endmodule module AFIFO_18K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - - parameter WR_DATA_WIDTH = 18; - parameter RD_DATA_WIDTH = 18; - parameter UPAE_DBITS = 11'd10; - parameter UPAF_DBITS = 11'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - + + parameter WR_DATA_WIDTH = 18; + parameter RD_DATA_WIDTH = 18; + parameter UPAE_DBITS = 11'd10; + parameter UPAF_DBITS = 11'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + BRAM2x18_AFIFO #( - .WR1_DATA_WIDTH(WR_DATA_WIDTH), - .RD1_DATA_WIDTH(RD_DATA_WIDTH), - .UPAE_DBITS1(UPAE_DBITS), - .UPAF_DBITS1(UPAF_DBITS), - .WR2_DATA_WIDTH(), - .RD2_DATA_WIDTH(), - .UPAE_DBITS2(), - .UPAF_DBITS2() - ) U1 - ( - .DIN1(DIN), - .PUSH1(PUSH), - .POP1(POP), - .Push_Clk1(Push_Clk), - .Pop_Clk1(Pop_Clk), - .Async_Flush1(Async_Flush), - .Overrun_Error1(Overrun_Error), - .Full_Watermark1(Full_Watermark), - .Almost_Full1(Almost_Full), - .Full1(Full), - .Underrun_Error1(Underrun_Error), - .Empty_Watermark1(Empty_Watermark), - .Almost_Empty1(Almost_Empty), - .Empty1(Empty), - .DOUT1(DOUT), - - .DIN2(18'h0), - .PUSH2(1'b0), - .POP2(1'b0), - .Push_Clk2(1'b0), - .Pop_Clk2(1'b0), - .Async_Flush2(1'b0), - .Overrun_Error2(), - .Full_Watermark2(), - .Almost_Full2(), - .Full2(), - .Underrun_Error2(), - .Empty_Watermark2(), - .Almost_Empty2(), - .Empty2(), - .DOUT2() + .WR1_DATA_WIDTH(WR_DATA_WIDTH), + .RD1_DATA_WIDTH(RD_DATA_WIDTH), + .UPAE_DBITS1(UPAE_DBITS), + .UPAF_DBITS1(UPAF_DBITS), + .WR2_DATA_WIDTH(), + .RD2_DATA_WIDTH(), + .UPAE_DBITS2(), + .UPAF_DBITS2() + ) U1 + ( + .DIN1(DIN), + .PUSH1(PUSH), + .POP1(POP), + .Push_Clk1(Push_Clk), + .Pop_Clk1(Pop_Clk), + .Async_Flush1(Async_Flush), + .Overrun_Error1(Overrun_Error), + .Full_Watermark1(Full_Watermark), + .Almost_Full1(Almost_Full), + .Full1(Full), + .Underrun_Error1(Underrun_Error), + .Empty_Watermark1(Empty_Watermark), + .Almost_Empty1(Almost_Empty), + .Empty1(Empty), + .DOUT1(DOUT), + + .DIN2(18'h0), + .PUSH2(1'b0), + .POP2(1'b0), + .Push_Clk2(1'b0), + .Pop_Clk2(1'b0), + .Async_Flush2(1'b0), + .Overrun_Error2(), + .Full_Watermark2(), + .Almost_Full2(), + .Full2(), + .Underrun_Error2(), + .Empty_Watermark2(), + .Almost_Empty2(), + .Empty2(), + .DOUT2() ); endmodule module AFIFO_18K_X2_BLK ( - DIN1, - PUSH1, - POP1, - Push_Clk1, + DIN1, + PUSH1, + POP1, + Push_Clk1, Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 ); - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input wire Push_Clk1, Pop_Clk1; - input wire PUSH1, POP1; - input wire [WR1_DATA_WIDTH-1:0] DIN1; - input wire Async_Flush1; - output wire [RD1_DATA_WIDTH-1:0] DOUT1; - output wire Almost_Full1, Almost_Empty1; - output wire Full1, Empty1; - output wire Full_Watermark1, Empty_Watermark1; - output wire Overrun_Error1, Underrun_Error1; - - input wire Push_Clk2, Pop_Clk2; - input wire PUSH2, POP2; - input wire [WR2_DATA_WIDTH-1:0] DIN2; - input wire Async_Flush2; - output wire [RD2_DATA_WIDTH-1:0] DOUT2; - output wire Almost_Full2, Almost_Empty2; - output wire Full2, Empty2; - output wire Full_Watermark2, Empty_Watermark2; - output wire Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input wire Push_Clk1, Pop_Clk1; + input wire PUSH1, POP1; + input wire [WR1_DATA_WIDTH-1:0] DIN1; + input wire Async_Flush1; + output wire [RD1_DATA_WIDTH-1:0] DOUT1; + output wire Almost_Full1, Almost_Empty1; + output wire Full1, Empty1; + output wire Full_Watermark1, Empty_Watermark1; + output wire Overrun_Error1, Underrun_Error1; + + input wire Push_Clk2, Pop_Clk2; + input wire PUSH2, POP2; + input wire [WR2_DATA_WIDTH-1:0] DIN2; + input wire Async_Flush2; + output wire [RD2_DATA_WIDTH-1:0] DOUT2; + output wire Almost_Full2, Almost_Empty2; + output wire Full2, Empty2; + output wire Full_Watermark2, Empty_Watermark2; + output wire Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 1 *) - (* is_inferred = 0 *) - (* port_a1_dwidth = WR1_DATA_WIDTH *) - (* port_a2_dwidth = WR2_DATA_WIDTH *) - (* port_b1_dwidth = RD1_DATA_WIDTH *) - (* port_b2_dwidth = RD2_DATA_WIDTH *) + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 1 *) + (* is_inferred = 0 *) + (* port_a1_dwidth = WR1_DATA_WIDTH *) + (* port_a2_dwidth = WR2_DATA_WIDTH *) + (* port_b1_dwidth = RD1_DATA_WIDTH *) + (* port_b2_dwidth = RD2_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg1[17:0]), @@ -4392,138 +4392,138 @@ module AFIFO_18K_X2_BLK ( endmodule module SFIFO_36K_BLK ( - DIN, - PUSH, - POP, - CLK, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + CLK, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire CLK; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - - wire Push_Clk, Pop_Clk; - - assign Push_Clk = CLK; - assign Pop_Clk = CLK; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire CLK; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + + wire Push_Clk, Pop_Clk; + + assign Push_Clk = CLK; + assign Pop_Clk = CLK; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = WR_DATA_WIDTH *) - (* port_b_dwidth = RD_DATA_WIDTH *) - TDP36K _TECHMAP_REPLACE_ ( + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) + TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), .WDATA_A2_i(in_reg[35:18]), @@ -4559,138 +4559,138 @@ module SFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); -endmodule +endmodule module AFIFO_36K_BLK ( - DIN, - PUSH, - POP, - Push_Clk, - Pop_Clk, - Async_Flush, - Overrun_Error, - Full_Watermark, - Almost_Full, - Full, - Underrun_Error, - Empty_Watermark, - Almost_Empty, - Empty, - DOUT + DIN, + PUSH, + POP, + Push_Clk, + Pop_Clk, + Async_Flush, + Overrun_Error, + Full_Watermark, + Almost_Full, + Full, + Underrun_Error, + Empty_Watermark, + Almost_Empty, + Empty, + DOUT ); - parameter WR_DATA_WIDTH = 36; - parameter RD_DATA_WIDTH = 36; - parameter UPAE_DBITS = 12'd10; - parameter UPAF_DBITS = 12'd10; - - input wire Push_Clk, Pop_Clk; - input wire PUSH, POP; - input wire [WR_DATA_WIDTH-1:0] DIN; - input wire Async_Flush; - output wire [RD_DATA_WIDTH-1:0] DOUT; - output wire Almost_Full, Almost_Empty; - output wire Full, Empty; - output wire Full_Watermark, Empty_Watermark; - output wire Overrun_Error, Underrun_Error; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS; - localparam [11:0] UPAF1_i = UPAF_DBITS; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd0; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = 11'd10; - localparam [10:0] UPAF2_i = 11'd10; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - wire [35:0] in_reg; - wire [35:0] out_reg; - wire [17:0] fifo_flags; - - wire [35:0] RD_DATA_INT; - wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; - - assign Overrun_Error = fifo_flags[0]; - assign Full_Watermark = fifo_flags[1]; - assign Almost_Full = fifo_flags[2]; - assign Full = fifo_flags[3]; - assign Underrun_Error = fifo_flags[4]; - assign Empty_Watermark = fifo_flags[5]; - assign Almost_Empty = fifo_flags[6]; - assign Empty = fifo_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); - - generate - if (WR_DATA_WIDTH == 36) begin - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin - assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; - assign in_reg[17:0] = {2'b00,DIN[15:0]}; - end else if (WR_DATA_WIDTH == 9) begin - assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; - end else begin - assign in_reg[35:WR_DATA_WIDTH] = 0; - assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD_DATA_WIDTH == 36) begin - assign RD_DATA_INT = out_reg; - end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin - assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; - end else if (RD_DATA_WIDTH == 9) begin - assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; - end else begin - assign RD_DATA_INT = {18'h0, out_reg[17:0]}; - end - endgenerate - - assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, + parameter WR_DATA_WIDTH = 36; + parameter RD_DATA_WIDTH = 36; + parameter UPAE_DBITS = 12'd10; + parameter UPAF_DBITS = 12'd10; + + input wire Push_Clk, Pop_Clk; + input wire PUSH, POP; + input wire [WR_DATA_WIDTH-1:0] DIN; + input wire Async_Flush; + output wire [RD_DATA_WIDTH-1:0] DOUT; + output wire Almost_Full, Almost_Empty; + output wire Full, Empty; + output wire Full_Watermark, Empty_Watermark; + output wire Overrun_Error, Underrun_Error; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS; + localparam [11:0] UPAF1_i = UPAF_DBITS; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd0; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = 11'd10; + localparam [10:0] UPAF2_i = 11'd10; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + wire [35:0] in_reg; + wire [35:0] out_reg; + wire [17:0] fifo_flags; + + wire [35:0] RD_DATA_INT; + wire [35:WR_DATA_WIDTH] WR_DATA_CMPL; + + assign Overrun_Error = fifo_flags[0]; + assign Full_Watermark = fifo_flags[1]; + assign Almost_Full = fifo_flags[2]; + assign Full = fifo_flags[3]; + assign Underrun_Error = fifo_flags[4]; + assign Empty_Watermark = fifo_flags[5]; + assign Almost_Empty = fifo_flags[6]; + assign Empty = fifo_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD_DATA_WIDTH); + + generate + if (WR_DATA_WIDTH == 36) begin + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end else if (WR_DATA_WIDTH > 18 && WR_DATA_WIDTH < 36) begin + assign in_reg[WR_DATA_WIDTH+1:18] = DIN[WR_DATA_WIDTH-1:16]; + assign in_reg[17:0] = {2'b00,DIN[15:0]}; + end else if (WR_DATA_WIDTH == 9) begin + assign in_reg[35:0] = {19'h0, DIN[8], 8'h0, DIN[7:0]}; + end else begin + assign in_reg[35:WR_DATA_WIDTH] = 0; + assign in_reg[WR_DATA_WIDTH-1:0] = DIN[WR_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD_DATA_WIDTH == 36) begin + assign RD_DATA_INT = out_reg; + end else if (RD_DATA_WIDTH > 18 && RD_DATA_WIDTH < 36) begin + assign RD_DATA_INT = {2'b00,out_reg[35:18],out_reg[15:0]}; + end else if (RD_DATA_WIDTH == 9) begin + assign RD_DATA_INT = { 27'h0, out_reg[16], out_reg[7:0]}; + end else begin + assign RD_DATA_INT = {18'h0, out_reg[17:0]}; + end + endgenerate + + assign DOUT[RD_DATA_WIDTH-1 : 0] = RD_DATA_INT[RD_DATA_WIDTH-1 : 0]; + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_inferred = 0 *) - (* is_split = 0 *) - (* port_a_dwidth = WR_DATA_WIDTH *) - (* port_b_dwidth = RD_DATA_WIDTH *) + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_inferred = 0 *) + (* is_split = 0 *) + (* port_a_dwidth = WR_DATA_WIDTH *) + (* port_b_dwidth = RD_DATA_WIDTH *) TDP36K _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(in_reg[17:0]), @@ -4727,97 +4727,97 @@ module AFIFO_36K_BLK ( .FLUSH2_i(1'b0) ); -endmodule +endmodule //=============================================================================== module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -4826,27 +4826,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -4858,93 +4858,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -4953,27 +4953,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -4985,93 +4985,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5080,27 +5080,27 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5112,93 +5112,93 @@ module TDP36K_FIFO_ASYNC_A_X9_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5207,27 +5207,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5239,93 +5239,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5334,27 +5334,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5366,93 +5366,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5461,27 +5461,27 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5493,93 +5493,93 @@ module TDP36K_FIFO_ASYNC_A_X18_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5588,27 +5588,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5620,93 +5620,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X9_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5715,27 +5715,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5747,93 +5747,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X18_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5842,27 +5842,27 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -5874,93 +5874,93 @@ module TDP36K_FIFO_ASYNC_A_X36_B_X36_nonsplit ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -5969,27 +5969,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6001,93 +6001,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6096,27 +6096,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6128,93 +6128,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6223,27 +6223,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6255,93 +6255,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6350,27 +6350,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6382,93 +6382,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6477,27 +6477,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6509,93 +6509,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6604,27 +6604,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6636,93 +6636,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6731,27 +6731,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6763,93 +6763,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6858,27 +6858,27 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -6890,93 +6890,93 @@ module TDP36K_FIFO_ASYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -6985,27 +6985,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7017,93 +7017,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7112,27 +7112,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7144,93 +7144,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7239,27 +7239,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7271,93 +7271,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7366,27 +7366,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7398,93 +7398,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7493,27 +7493,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7525,93 +7525,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7620,27 +7620,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7652,93 +7652,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7747,27 +7747,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7779,93 +7779,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -7874,27 +7874,27 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -7906,93 +7906,93 @@ module TDP36K_FIFO_ASYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8001,27 +8001,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8033,93 +8033,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8128,27 +8128,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8160,93 +8160,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8255,27 +8255,27 @@ module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8287,93 +8287,93 @@ module TDP36K_FIFO_SYNC_A_X9_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8382,27 +8382,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8414,93 +8414,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8509,27 +8509,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8541,93 +8541,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8636,27 +8636,27 @@ module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8668,93 +8668,93 @@ module TDP36K_FIFO_SYNC_A_X18_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8763,27 +8763,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8795,93 +8795,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X9_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -8890,27 +8890,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -8922,93 +8922,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X18_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9017,27 +9017,27 @@ module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9049,93 +9049,93 @@ module TDP36K_FIFO_SYNC_A_X36_B_X36_nonsplit ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9144,27 +9144,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9176,93 +9176,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9271,27 +9271,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9303,93 +9303,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9398,27 +9398,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9430,93 +9430,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9525,27 +9525,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9557,93 +9557,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9652,27 +9652,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9684,93 +9684,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9779,27 +9779,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9811,93 +9811,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -9906,27 +9906,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -9938,93 +9938,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10033,27 +10033,27 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10065,93 +10065,93 @@ module TDP36K_FIFO_SYNC_A1_X18_B1_X9_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10160,27 +10160,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10192,93 +10192,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10287,27 +10287,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10319,93 +10319,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10414,27 +10414,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10446,93 +10446,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10541,27 +10541,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10573,93 +10573,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X18_A2_X9_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10668,27 +10668,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10700,93 +10700,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10795,27 +10795,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10827,93 +10827,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X18_B2_X9_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -10922,27 +10922,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); @@ -10954,93 +10954,93 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X18_split ( endmodule module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( - RESET_ni, - WEN_A1_i, WEN_B1_i, - REN_A1_i, REN_B1_i, - CLK_A1_i, CLK_B1_i, - BE_A1_i, BE_B1_i, - ADDR_A1_i, ADDR_B1_i, - WDATA_A1_i, WDATA_B1_i, - RDATA_A1_o, RDATA_B1_o, - FLUSH1_i, - WEN_A2_i, WEN_B2_i, - REN_A2_i, REN_B2_i, - CLK_A2_i, CLK_B2_i, - BE_A2_i, BE_B2_i, - ADDR_A2_i, ADDR_B2_i, - WDATA_A2_i, WDATA_B2_i, - RDATA_A2_o, RDATA_B2_o, - FLUSH2_i + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i ); - parameter [80:0] MODE_BITS = 81'd0; - - input wire RESET_ni; - input wire WEN_A1_i, WEN_B1_i; - input wire REN_A1_i, REN_B1_i; - input wire WEN_A2_i, WEN_B2_i; - input wire REN_A2_i, REN_B2_i; - - (* clkbuf_sink *) - input wire CLK_A1_i; - (* clkbuf_sink *) - input wire CLK_B1_i; - (* clkbuf_sink *) - input wire CLK_A2_i; - (* clkbuf_sink *) - input wire CLK_B2_i; - - input wire [ 1:0] BE_A1_i, BE_B1_i; - input wire [14:0] ADDR_A1_i, ADDR_B1_i; - input wire [17:0] WDATA_A1_i, WDATA_B1_i; - output wire [17:0] RDATA_A1_o, RDATA_B1_o; - - input wire FLUSH1_i; - - input wire [ 1:0] BE_A2_i, BE_B2_i; - input wire [13:0] ADDR_A2_i, ADDR_B2_i; - input wire [17:0] WDATA_A2_i, WDATA_B2_i; - output wire [17:0] RDATA_A2_o, RDATA_B2_o; - - input wire FLUSH2_i; - - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( - .RESET_ni (RESET_ni), - .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), - .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), - .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), - .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), - .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), - .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), - .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), - .FLUSH1_i (FLUSH1_i), - .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), - .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), - .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), - .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), - .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), - .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), - .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), - .FLUSH2_i (FLUSH2_i) - ); - + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + `ifdef SDF_SIM specify - (FLUSH1_i => RDATA_A1_o[0]) = 0; - (FLUSH1_i => RDATA_A1_o[1]) = 0; - (FLUSH1_i => RDATA_A1_o[2]) = 0; - (FLUSH1_i => RDATA_A1_o[3]) = 0; - (FLUSH1_i => RDATA_A1_o[4]) = 0; - (FLUSH1_i => RDATA_A1_o[5]) = 0; - (FLUSH1_i => RDATA_A1_o[6]) = 0; - (FLUSH1_i => RDATA_A1_o[7]) = 0; - (FLUSH2_i => RDATA_A2_o[0]) = 0; - (FLUSH2_i => RDATA_A2_o[1]) = 0; - (FLUSH2_i => RDATA_A2_o[2]) = 0; - (FLUSH2_i => RDATA_A2_o[3]) = 0; - (FLUSH2_i => RDATA_A2_o[4]) = 0; - (FLUSH2_i => RDATA_A2_o[5]) = 0; - (FLUSH2_i => RDATA_A2_o[6]) = 0; - (FLUSH2_i => RDATA_A2_o[7]) = 0; + (FLUSH1_i => RDATA_A1_o[0]) = 0; + (FLUSH1_i => RDATA_A1_o[1]) = 0; + (FLUSH1_i => RDATA_A1_o[2]) = 0; + (FLUSH1_i => RDATA_A1_o[3]) = 0; + (FLUSH1_i => RDATA_A1_o[4]) = 0; + (FLUSH1_i => RDATA_A1_o[5]) = 0; + (FLUSH1_i => RDATA_A1_o[6]) = 0; + (FLUSH1_i => RDATA_A1_o[7]) = 0; + (FLUSH2_i => RDATA_A2_o[0]) = 0; + (FLUSH2_i => RDATA_A2_o[1]) = 0; + (FLUSH2_i => RDATA_A2_o[2]) = 0; + (FLUSH2_i => RDATA_A2_o[3]) = 0; + (FLUSH2_i => RDATA_A2_o[4]) = 0; + (FLUSH2_i => RDATA_A2_o[5]) = 0; + (FLUSH2_i => RDATA_A2_o[6]) = 0; + (FLUSH2_i => RDATA_A2_o[7]) = 0; (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; @@ -11049,27 +11049,27 @@ module TDP36K_FIFO_SYNC_A1_X9_B1_X9_A2_X9_B2_X9_split ( (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; - $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); - $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); - $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); - $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v index 645a62f833a..b9f40625646 100644 --- a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -19,104 +19,104 @@ `default_nettype none (* abc9_lut=1 *) module LUT1(output wire O, input wire I0); - parameter [1:0] INIT = 0; - assign O = I0 ? INIT[1] : INIT[0]; - specify - (I0 => O) = 74; - endspecify + parameter [1:0] INIT = 0; + assign O = I0 ? INIT[1] : INIT[0]; + specify + (I0 => O) = 74; + endspecify endmodule (* abc9_lut=2 *) module LUT2(output wire O, input wire I0, I1); - parameter [3:0] INIT = 0; - wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 116; - (I1 => O) = 74; - endspecify + parameter [3:0] INIT = 0; + wire [ 1: 0] s1 = I1 ? INIT[ 3: 2] : INIT[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 116; + (I1 => O) = 74; + endspecify endmodule (* abc9_lut=3 *) module LUT3(output wire O, input wire I0, I1, I2); - parameter [7:0] INIT = 0; - wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 162; - (I1 => O) = 116; - (I2 => O) = 174; - endspecify + parameter [7:0] INIT = 0; + wire [ 3: 0] s2 = I2 ? INIT[ 7: 4] : INIT[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 162; + (I1 => O) = 116; + (I2 => O) = 174; + endspecify endmodule (* abc9_lut=3 *) module LUT4(output wire O, input wire I0, I1, I2, I3); - parameter [15:0] INIT = 0; - wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 201; - (I1 => O) = 162; - (I2 => O) = 116; - (I3 => O) = 74; - endspecify + parameter [15:0] INIT = 0; + wire [ 7: 0] s3 = I3 ? INIT[15: 8] : INIT[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 201; + (I1 => O) = 162; + (I2 => O) = 116; + (I3 => O) = 74; + endspecify endmodule (* abc9_lut=3 *) module LUT5(output wire O, input wire I0, I1, I2, I3, I4); - parameter [31:0] INIT = 0; - wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 228; - (I1 => O) = 189; - (I2 => O) = 143; - (I3 => O) = 100; - (I4 => O) = 55; - endspecify + parameter [31:0] INIT = 0; + wire [15: 0] s4 = I4 ? INIT[31:16] : INIT[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 228; + (I1 => O) = 189; + (I2 => O) = 143; + (I3 => O) = 100; + (I4 => O) = 55; + endspecify endmodule (* abc9_lut=5 *) module LUT6(output wire O, input wire I0, I1, I2, I3, I4, I5); - parameter [63:0] INIT = 0; - wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; - wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; - wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; - wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; - wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; - assign O = I0 ? s1[1] : s1[0]; - specify - (I0 => O) = 251; - (I1 => O) = 212; - (I2 => O) = 166; - (I3 => O) = 123; - (I4 => O) = 77; - (I5 => O) = 43; - endspecify + parameter [63:0] INIT = 0; + wire [31: 0] s5 = I5 ? INIT[63:32] : INIT[31: 0]; + wire [15: 0] s4 = I4 ? s5[31:16] : s5[15: 0]; + wire [ 7: 0] s3 = I3 ? s4[15: 8] : s4[ 7: 0]; + wire [ 3: 0] s2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; + wire [ 1: 0] s1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; + assign O = I0 ? s1[1] : s1[0]; + specify + (I0 => O) = 251; + (I1 => O) = 212; + (I2 => O) = 166; + (I3 => O) = 123; + (I4 => O) = 77; + (I5 => O) = 43; + endspecify endmodule (* abc9_flop, lib_whitebox *) module sh_dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; - always @(posedge C) - Q <= D; - - specify - (posedge C => (Q +: D)) = 0; - $setuphold(posedge C, D, 0, 0); - endspecify + initial Q = 1'b0; + always @(posedge C) + Q <= D; + + specify + (posedge C => (Q +: D)) = 0; + $setuphold(posedge C, D, 0, 0); + endspecify endmodule @@ -124,253 +124,253 @@ endmodule (* blackbox *) (* keep *) module adder_carry( - output wire sumout, - (* abc9_carry *) - output wire cout, - input wire p, - input wire g, - (* abc9_carry *) - input wire cin + output wire sumout, + (* abc9_carry *) + output wire cout, + input wire p, + input wire g, + (* abc9_carry *) + input wire cin ); - assign sumout = p ^ cin; - assign cout = p ? cin : g; - - specify - (p => sumout) = 35; - (g => sumout) = 35; - (cin => sumout) = 40; - (p => cout) = 67; - (g => cout) = 65; - (cin => cout) = 69; - endspecify + assign sumout = p ^ cin; + assign cout = p ? cin : g; + + specify + (p => sumout) = 35; + (g => sumout) = 35; + (cin => sumout) = 40; + (p => cout) = 67; + (g => cout) = 65; + (cin => cout) = 69; + endspecify endmodule (* abc9_flop, lib_whitebox *) module dff( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; + initial Q = 1'b0; - always @(posedge C) - Q <= D; + always @(posedge C) + Q <= D; - specify - (posedge C=>(Q+:D)) = 285; - $setuphold(posedge C, D, 56, 0); - endspecify + specify + (posedge C=>(Q+:D)) = 285; + $setuphold(posedge C, D, 56, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffn( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C ); - initial Q <= 1'b0; + initial Q = 1'b0; + + always @(negedge C) + Q <= D; - always @(negedge C) - Q <= D; - - specify - (negedge C=>(Q+:D)) = 285; - $setuphold(negedge C, D, 56, 0); - endspecify + specify + (negedge C=>(Q+:D)) = 285; + $setuphold(negedge C, D, 56, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(posedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (posedge C => (Q +: D)) = 280; - (R => Q) = 0; - (S => Q) = 0; - $setuphold(posedge C, D, 56, 0); - $setuphold(posedge C, E, 32, 0); - $setuphold(posedge C, R, 0, 0); - $setuphold(posedge C, S, 0, 0); - $recrem(posedge R, posedge C, 0, 0); - $recrem(posedge S, posedge C, 0, 0); - endspecify + initial Q = 1'b0; + + always @(posedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, E, 32, 0); + $setuphold(posedge C, R, 0, 0); + $setuphold(posedge C, S, 0, 0); + $recrem(posedge R, posedge C, 0, 0); + $recrem(posedge S, posedge C, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module dffnsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(negedge C or negedge S or negedge R) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (negedge C => (Q +: D)) = 280; - (R => Q) = 0; - (S => Q) = 0; - $setuphold(negedge C, D, 56, 0); - $setuphold(negedge C, E, 32, 0); - $setuphold(negedge C, R, 0, 0); - $setuphold(negedge C, S, 0, 0); - $recrem(posedge R, negedge C, 0, 0); - $recrem(posedge S, negedge C, 0, 0); - endspecify + initial Q = 1'b0; + + always @(negedge C or negedge S or negedge R) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + (R => Q) = 0; + (S => Q) = 0; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, E, 32, 0); + $setuphold(negedge C, R, 0, 0); + $setuphold(negedge C, S, 0, 0); + $recrem(posedge R, negedge C, 0, 0); + $recrem(posedge S, negedge C, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module sdffsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(posedge C) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (posedge C => (Q +: D)) = 280; - $setuphold(posedge C, D, 56, 0); - $setuphold(posedge C, R, 32, 0); - $setuphold(posedge C, S, 0, 0); - $setuphold(posedge C, E, 0, 0); - endspecify + initial Q = 1'b0; + + always @(posedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (posedge C => (Q +: D)) = 280; + $setuphold(posedge C, D, 56, 0); + $setuphold(posedge C, R, 32, 0); + $setuphold(posedge C, S, 0, 0); + $setuphold(posedge C, E, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module sdffnsre( - output reg Q, - input wire D, - (* clkbuf_sink *) - input wire C, - input wire E, - input wire R, - input wire S + output reg Q, + input wire D, + (* clkbuf_sink *) + input wire C, + input wire E, + input wire R, + input wire S ); - initial Q <= 1'b0; - - always @(negedge C) - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E) - Q <= D; - - specify - (negedge C => (Q +: D)) = 280; - $setuphold(negedge C, D, 56, 0); - $setuphold(negedge C, R, 32, 0); - $setuphold(negedge C, S, 0, 0); - $setuphold(negedge C, E, 0, 0); - endspecify + initial Q = 1'b0; + + always @(negedge C) + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E) + Q <= D; + + specify + (negedge C => (Q +: D)) = 280; + $setuphold(negedge C, D, 56, 0); + $setuphold(negedge C, R, 32, 0); + $setuphold(negedge C, S, 0, 0); + $setuphold(negedge C, E, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module latchsre ( - output reg Q, - input wire S, - input wire R, - input wire D, - input wire G, - input wire E + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E ); - initial Q <= 1'b0; - - always @* - begin - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E && G) - Q <= D; - end - - specify - (posedge G => (Q +: D)) = 0; - $setuphold(posedge G, D, 0, 0); - $setuphold(posedge G, E, 0, 0); - $setuphold(posedge G, R, 0, 0); - $setuphold(posedge G, S, 0, 0); - endspecify + initial Q = 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && G) + Q <= D; + end + + specify + (posedge G => (Q +: D)) = 0; + $setuphold(posedge G, D, 0, 0); + $setuphold(posedge G, E, 0, 0); + $setuphold(posedge G, R, 0, 0); + $setuphold(posedge G, S, 0, 0); + endspecify endmodule (* abc9_flop, lib_whitebox *) module latchnsre ( - output reg Q, - input wire S, - input wire R, - input wire D, - input wire G, - input wire E + output reg Q, + input wire S, + input wire R, + input wire D, + input wire G, + input wire E ); - initial Q <= 1'b0; - - always @* - begin - if (!R) - Q <= 1'b0; - else if (!S) - Q <= 1'b1; - else if (E && !G) - Q <= D; - end - - specify - (negedge G => (Q +: D)) = 0; - $setuphold(negedge G, D, 0, 0); - $setuphold(negedge G, E, 0, 0); - $setuphold(negedge G, R, 0, 0); - $setuphold(negedge G, S, 0, 0); - endspecify + initial Q = 1'b0; + + always @* + begin + if (!R) + Q <= 1'b0; + else if (!S) + Q <= 1'b1; + else if (E && !G) + Q <= D; + end + + specify + (negedge G => (Q +: D)) = 0; + $setuphold(negedge G, D, 0, 0); + $setuphold(negedge G, E, 0, 0); + $setuphold(negedge G, R, 0, 0); + $setuphold(negedge G, S, 0, 0); + endspecify endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v index 26fa6ed3604..43a71b425a1 100644 --- a/techlibs/quicklogic/qlf_k6n10f/ffs_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/ffs_map.v @@ -16,116 +16,116 @@ // DFF, asynchronous set/reset, enable module \$_DFFSRE_PNNP_ (C, S, R, E, D, Q); - input C; - input S; - input R; - input E; - input D; - output Q; - dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); + input C; + input S; + input R; + input E; + input D; + output Q; + dffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule module \$_DFFSRE_NNNP_ (C, S, R, E, D, Q); - input C; - input S; - input R; - input E; - input D; - output Q; - dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); + input C; + input S; + input R; + input E; + input D; + output Q; + dffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(S)); endmodule // DFF, synchronous set or reset, enable module \$_SDFFE_PN0P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule module \$_SDFFE_PN1P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); + input D; + input C; + input R; + input E; + output Q; + sdffsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule module \$_SDFFE_NN0P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(R), .S(1'b1)); endmodule module \$_SDFFE_NN1P_ (D, C, R, E, Q); - input D; - input C; - input R; - input E; - output Q; - sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); + input D; + input C; + input R; + input E; + output Q; + sdffnsre _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .E(E), .R(1'b1), .S(R)); endmodule // Latch, no set/reset, no enable module \$_DLATCH_P_ (input E, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule module \$_DLATCH_N_ (input E, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(1'b1), .S(1'b1)); endmodule // Latch with async set and reset and enable module \$_DLATCHSR_PPP_ (input E, S, R, D, output Q); - latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); + latchsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule module \$_DLATCHSR_NPP_ (input E, S, R, D, output Q); - latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); + latchnsre _TECHMAP_REPLACE_ (.D(D), .Q(Q), .E(1'b1), .G(E), .R(!R), .S(!S)); endmodule module \$__SHREG_DFF_P_ (D, Q, C); - input D; - input C; - output Q; - - parameter DEPTH = 2; - - reg [DEPTH-2:0] q; - - genvar i; - generate for (i = 0; i < DEPTH; i = i + 1) begin: slice - - // First in chain - generate if (i == 0) begin - sh_dff #() shreg_beg ( - .Q(q[i]), - .D(D), - .C(C) - ); - end endgenerate - // Middle in chain - generate if (i > 0 && i != DEPTH-1) begin - sh_dff #() shreg_mid ( - .Q(q[i]), - .D(q[i-1]), - .C(C) - ); - end endgenerate - // Last in chain - generate if (i == DEPTH-1) begin - sh_dff #() shreg_end ( - .Q(Q), - .D(q[i-1]), - .C(C) - ); - end endgenerate + input D; + input C; + output Q; + + parameter DEPTH = 2; + + reg [DEPTH-2:0] q; + + genvar i; + generate for (i = 0; i < DEPTH; i = i + 1) begin: slice + + // First in chain + generate if (i == 0) begin + sh_dff #() shreg_beg ( + .Q(q[i]), + .D(D), + .C(C) + ); + end endgenerate + // Middle in chain + generate if (i > 0 && i != DEPTH-1) begin + sh_dff #() shreg_mid ( + .Q(q[i]), + .D(q[i-1]), + .C(C) + ); + end endgenerate + // Last in chain + generate if (i == DEPTH-1) begin + sh_dff #() shreg_end ( + .Q(Q), + .D(q[i-1]), + .C(C) + ); + end endgenerate end: slice endgenerate diff --git a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py new file mode 100644 index 00000000000..5f7da90977e --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py @@ -0,0 +1,246 @@ +import sys +from datetime import datetime, timezone + +def generate(filename): + with open(filename, "w") as f: + f.write("// **AUTOGENERATED FILE** **DO NOT EDIT**\n") + f.write(f"// Generated by {sys.argv[0]} at {datetime.now(timezone.utc)}\n") + + f.write("`timescale 1ns /10ps\n") + for a_width in [1,2,4,9,18,36]: + for b_width in [1,2,4,9,18,36]: + f.write(f""" +module TDP36K_BRAM_A_X{a_width}_B_X{b_width}_nonsplit ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + + for a1_width in [1,2,4,9,18]: + for b1_width in [1,2,4,9,18]: + for a2_width in [1,2,4,9,18]: + for b2_width in [1,2,4,9,18]: + f.write(f""" +module TDP36K_BRAM_A1_X{a1_width}_B1_X{b1_width}_A2_X{a2_width}_B2_X{b2_width}_split ( + RESET_ni, + WEN_A1_i, WEN_B1_i, + REN_A1_i, REN_B1_i, + CLK_A1_i, CLK_B1_i, + BE_A1_i, BE_B1_i, + ADDR_A1_i, ADDR_B1_i, + WDATA_A1_i, WDATA_B1_i, + RDATA_A1_o, RDATA_B1_o, + FLUSH1_i, + WEN_A2_i, WEN_B2_i, + REN_A2_i, REN_B2_i, + CLK_A2_i, CLK_B2_i, + BE_A2_i, BE_B2_i, + ADDR_A2_i, ADDR_B2_i, + WDATA_A2_i, WDATA_B2_i, + RDATA_A2_o, RDATA_B2_o, + FLUSH2_i + ); + + parameter [80:0] MODE_BITS = 81'd0; + + input wire RESET_ni; + input wire WEN_A1_i, WEN_B1_i; + input wire REN_A1_i, REN_B1_i; + input wire WEN_A2_i, WEN_B2_i; + input wire REN_A2_i, REN_B2_i; + + (* clkbuf_sink *) + input wire CLK_A1_i; + (* clkbuf_sink *) + input wire CLK_B1_i; + (* clkbuf_sink *) + input wire CLK_A2_i; + (* clkbuf_sink *) + input wire CLK_B2_i; + + input wire [ 1:0] BE_A1_i, BE_B1_i; + input wire [14:0] ADDR_A1_i, ADDR_B1_i; + input wire [17:0] WDATA_A1_i, WDATA_B1_i; + output wire [17:0] RDATA_A1_o, RDATA_B1_o; + + input wire FLUSH1_i; + + input wire [ 1:0] BE_A2_i, BE_B2_i; + input wire [13:0] ADDR_A2_i, ADDR_B2_i; + input wire [17:0] WDATA_A2_i, WDATA_B2_i; + output wire [17:0] RDATA_A2_o, RDATA_B2_o; + + input wire FLUSH2_i; + + TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + .RESET_ni (RESET_ni), + .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), + .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), + .CLK_A1_i (CLK_A1_i), .CLK_B1_i (CLK_B1_i), + .BE_A1_i (BE_A1_i), .BE_B1_i (BE_B1_i), + .ADDR_A1_i (ADDR_A1_i), .ADDR_B1_i (ADDR_B1_i), + .WDATA_A1_i (WDATA_A1_i), .WDATA_B1_i (WDATA_B1_i), + .RDATA_A1_o (RDATA_A1_o), .RDATA_B1_o (RDATA_B1_o), + .FLUSH1_i (FLUSH1_i), + .WEN_A2_i (WEN_A2_i), .WEN_B2_i (WEN_B2_i), + .REN_A2_i (REN_A2_i), .REN_B2_i (REN_B2_i), + .CLK_A2_i (CLK_A2_i), .CLK_B2_i (CLK_B2_i), + .BE_A2_i (BE_A2_i), .BE_B2_i (BE_B2_i), + .ADDR_A2_i (ADDR_A2_i), .ADDR_B2_i (ADDR_B2_i), + .WDATA_A2_i (WDATA_A2_i), .WDATA_B2_i (WDATA_B2_i), + .RDATA_A2_o (RDATA_A2_o), .RDATA_B2_o (RDATA_B2_o), + .FLUSH2_i (FLUSH2_i) + ); + + `ifdef SDF_SIM + specify + (negedge RESET_ni => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (negedge RESET_ni => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (negedge RESET_ni => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (negedge RESET_ni => (RDATA_B2_o +: WDATA_B2_i)) = 0; + (posedge CLK_A1_i => (RDATA_A1_o +: WDATA_A1_i)) = 0; + (posedge CLK_B1_i => (RDATA_B1_o +: WDATA_B1_i)) = 0; + (posedge CLK_A2_i => (RDATA_A2_o +: WDATA_A2_i)) = 0; + (posedge CLK_B2_i => (RDATA_B2_o +: WDATA_B2_i)) = 0; + $setuphold(posedge CLK_A1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A1_i, FLUSH1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WEN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, REN_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, BE_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, ADDR_A1_i, 0, 0); + $setuphold(posedge CLK_A1_i, WDATA_A1_i, 0, 0); + $setuphold(posedge CLK_B1_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B1_i, WEN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, REN_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, BE_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, ADDR_B1_i, 0, 0); + $setuphold(posedge CLK_B1_i, WDATA_B1_i, 0, 0); + $setuphold(posedge CLK_A2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_A2_i, FLUSH2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WEN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, REN_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, BE_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, ADDR_A2_i, 0, 0); + $setuphold(posedge CLK_A2_i, WDATA_A2_i, 0, 0); + $setuphold(posedge CLK_B2_i, RESET_ni, 0, 0); + $setuphold(posedge CLK_B2_i, WEN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, REN_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, BE_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, ADDR_B2_i, 0, 0); + $setuphold(posedge CLK_B2_i, WDATA_B2_i, 0, 0); + endspecify + `endif +endmodule +""") + +if __name__ == "__main__": + filename = "bram_types_sim.v" + if len(sys.argv) > 1: + filename = sys.argv[1] + generate(filename) diff --git a/techlibs/quicklogic/quicklogic_eqn.cc b/techlibs/quicklogic/quicklogic_eqn.cc deleted file mode 100644 index b82a1b2866e..00000000000 --- a/techlibs/quicklogic/quicklogic_eqn.cc +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright 2020-2022 F4PGA Authors - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * SPDX-License-Identifier: Apache-2.0 - * - */ - -#include "kernel/sigtools.h" -#include "kernel/yosys.h" - -USING_YOSYS_NAMESPACE -PRIVATE_NAMESPACE_BEGIN - -struct QuicklogicEqnPass : public Pass { - QuicklogicEqnPass() : Pass("quicklogic_eqn", "Quicklogic: Calculate equations for luts") {} - void help() override - { - log("\n"); - log(" quicklogic_eqn [selection]\n"); - log("\n"); - log("Calculate equations for luts since bitstream generator depends on it.\n"); - log("\n"); - } - - Const init2eqn(Const init, int inputs) - { - std::string init_bits = init.as_string(); - const char *names[] = {"I0", "I1", "I2", "I3", "I4"}; - - std::string eqn; - int width = (int)pow(2, inputs); - for (int i = 0; i < width; i++) { - if (init_bits[width - 1 - i] == '1') { - eqn += "("; - for (int j = 0; j < inputs; j++) { - if (i & (1 << j)) - eqn += names[j]; - else - eqn += std::string("~") + names[j]; - - if (j != (inputs - 1)) - eqn += "*"; - } - eqn += ")+"; - } - } - if (eqn.empty()) - return Const("0"); - eqn = eqn.substr(0, eqn.length() - 1); - return Const(eqn); - } - - void execute(std::vector args, RTLIL::Design *design) override - { - log_header(design, "Executing Quicklogic_EQN pass (calculate equations for luts).\n"); - - extra_args(args, args.size(), design); - - int cnt = 0; - for (auto module : design->selected_modules()) { - for (auto cell : module->selected_cells()) { - if (cell->type == ID(LUT1)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 1)); - cnt++; - } - if (cell->type == ID(LUT2)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 2)); - cnt++; - } - if (cell->type == ID(LUT3)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 3)); - cnt++; - } - if (cell->type == ID(LUT4)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 4)); - cnt++; - } - if (cell->type == ID(LUT5)) { - cell->setParam(ID(EQN), init2eqn(cell->getParam(ID::INIT), 5)); - cnt++; - } - } - } - log_header(design, "Updated %d of LUT* elements with equation.\n", cnt); - } -} QuicklogicEqnPass; - -PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 15ab68a3f72..d2df6bcff15 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -129,10 +129,6 @@ struct SynthQuickLogicPass : public ScriptPass { blif_file = args[++argidx]; continue; } - if (args[argidx] == "-edif" && argidx + 1 < args.size()) { - edif_file = args[++argidx]; - continue; - } if (args[argidx] == "-verilog" && argidx+1 < args.size()) { verilog_file = args[++argidx]; continue; @@ -141,15 +137,15 @@ struct SynthQuickLogicPass : public ScriptPass { abc9 = false; continue; } - if (args[argidx] == "-nocarry") { + if (args[argidx] == "-nocarry" || args[argidx] == "-no_adder") { inferAdder = false; continue; } - if (args[argidx] == "-nobram") { + if (args[argidx] == "-nobram" || args[argidx] == "-no_bram") { nobram = true; continue; } - if (args[argidx] == "-bramtypes") { + if (args[argidx] == "-bramtypes" || args[argidx] == "-bram_types") { bramTypes = true; continue; } @@ -230,61 +226,8 @@ struct SynthQuickLogicPass : public ScriptPass { run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); run("techmap -map " + lib_path + family + "/brams_final_map.v"); - if (help_mode) { - run("chtype -set TDP36K_ t:TDP36K a:", "(if -bram_types)"); - } - else if (bramTypes) { - for (int a_dwidth : {1, 2, 4, 9, 18, 36}) - for (int b_dwidth: {1, 2, 4, 9, 18, 36}) { - run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_ASYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=1 %%i a:sync_fifo=0 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_SYNC_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=0 %%i " - "a:is_fifo=1 %%i a:sync_fifo=1 %%i a:port_a_dwidth=%d %%i a:port_b_dwidth=%d %%i", - a_dwidth, b_dwidth, a_dwidth, b_dwidth)); - } - - for (int a1_dwidth : {1, 2, 4, 9, 18}) - for (int b1_dwidth: {1, 2, 4, 9, 18}) - for (int a2_dwidth : {1, 2, 4, 9, 18}) - for (int b2_dwidth: {1, 2, 4, 9, 18}) { - run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=0 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_ASYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=0 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - - run(stringf("chtype -set TDP36K_FIFO_SYNC_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=0 %%i " - "a:is_split=1 %%i a:is_fifo=1 %%i a:sync_fifo=1 %%i " - "a:port_a1_dwidth=%d %%i a:port_b1_dwidth=%d %%i a:port_a2_dwidth=%d %%i a:port_b2_dwidth=%d %%i", - a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth, a1_dwidth, b1_dwidth, a2_dwidth, b2_dwidth)); - } - - - for (int a_width : {1, 2, 4, 9, 18, 36}) - for (int b_width: {1, 2, 4, 9, 18, 36}) { - run(stringf("chtype -set TDP36K_BRAM_A_X%d_B_X%d_nonsplit t:TDP36K a:is_inferred=1 %%i " - "a:port_a_width=%d %%i a:port_b_width=%d %%i", - a_width, b_width, a_width, b_width)); - } - - for (int a1_width : {1, 2, 4, 9, 18}) - for (int b1_width: {1, 2, 4, 9, 18}) - for (int a2_width : {1, 2, 4, 9, 18}) - for (int b2_width: {1, 2, 4, 9, 18}) { - run(stringf("chtype -set TDP36K_BRAM_A1_X%d_B1_X%d_A2_X%d_B2_X%d_split t:TDP36K a:is_inferred=1 %%i " - "a:port_a1_width=%d %%i a:port_b1_width=%d %%i a:port_a2_width=%d %%i a:port_b2_width=%d %%i", - a1_width, b1_width, a2_width, b2_width, a1_width, b1_width, a2_width, b2_width)); - } + if (help_mode || bramTypes) { + run("ql_bram_types"); } } @@ -393,13 +336,6 @@ struct SynthQuickLogicPass : public ScriptPass { run(stringf("write_verilog -noattr -nohex %s", help_mode ? "" : verilog_file.c_str())); } } - - if (check_label("edif", "(if -edif)")) { - if (!edif_file.empty() || help_mode) { - run("splitnets -ports -format ()"); - run(stringf("write_edif -nogndvcc -attrprop -pvector par %s %s", top_opt.c_str(), edif_file.c_str())); - } - } } } SynthQuicklogicPass; From 20d864bbdeee0b7854e5a6816159a12b21cb4861 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 27 Nov 2023 10:35:29 +0100 Subject: [PATCH 04/39] add dsp inference --- techlibs/quicklogic/.gitignore | 1 + techlibs/quicklogic/Makefile.inc | 23 +- .../{ql-bram-merge.cc => ql_bram_merge.cc} | 0 .../{ql-bram-types.cc => ql_bram_types.cc} | 0 techlibs/quicklogic/ql_dsp_io_regs.cc | 244 + techlibs/quicklogic/ql_dsp_macc.cc | 307 + techlibs/quicklogic/ql_dsp_macc.pmg | 50 + techlibs/quicklogic/ql_dsp_simd.cc | 359 + .../quicklogic/qlf_k6n10f/dsp_final_map.v | 265 + techlibs/quicklogic/qlf_k6n10f/dsp_map.v | 147 + techlibs/quicklogic/qlf_k6n10f/dsp_sim.v | 5753 +++++++++++++++++ techlibs/quicklogic/synth_quicklogic.cc | 47 +- 12 files changed, 7189 insertions(+), 7 deletions(-) create mode 100644 techlibs/quicklogic/.gitignore rename techlibs/quicklogic/{ql-bram-merge.cc => ql_bram_merge.cc} (100%) rename techlibs/quicklogic/{ql-bram-types.cc => ql_bram_types.cc} (100%) create mode 100644 techlibs/quicklogic/ql_dsp_io_regs.cc create mode 100644 techlibs/quicklogic/ql_dsp_macc.cc create mode 100644 techlibs/quicklogic/ql_dsp_macc.pmg create mode 100644 techlibs/quicklogic/ql_dsp_simd.cc create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_map.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/dsp_sim.v diff --git a/techlibs/quicklogic/.gitignore b/techlibs/quicklogic/.gitignore new file mode 100644 index 00000000000..e52f3282f7f --- /dev/null +++ b/techlibs/quicklogic/.gitignore @@ -0,0 +1 @@ +/*_pm.h diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index df69a3fc32c..ce5ff859b2e 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -1,6 +1,20 @@ +%_pm.h: passes/pmgen/pmgen.py %.pmg + $(P) mkdir -p pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) + OBJS += techlibs/quicklogic/synth_quicklogic.o -OBJS += techlibs/quicklogic/ql-bram-merge.o -OBJS += techlibs/quicklogic/ql-bram-types.o +OBJS += techlibs/quicklogic/ql_bram_merge.o +OBJS += techlibs/quicklogic/ql_bram_types.o +OBJS += techlibs/quicklogic/ql_dsp_simd.o +OBJS += techlibs/quicklogic/ql_dsp_io_regs.o + +# -------------------------------------- + +OBJS += techlibs/quicklogic/ql_dsp_macc.o +GENFILES += techlibs/quicklogic/ql_dsp_macc_pm.h +techlibs/quicklogic/ql_dsp_macc.o: techlibs/quicklogic/ql_dsp_macc_pm.h +$(eval $(call add_extra_objs,techlibs/quicklogic/ql_dsp_macc_pm.h)) + +# -------------------------------------- $(eval $(call add_share_file,share/quicklogic/common,techlibs/quicklogic/common/cells_sim.v)) @@ -21,4 +35,7 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) \ No newline at end of file +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/ql-bram-merge.cc b/techlibs/quicklogic/ql_bram_merge.cc similarity index 100% rename from techlibs/quicklogic/ql-bram-merge.cc rename to techlibs/quicklogic/ql_bram_merge.cc diff --git a/techlibs/quicklogic/ql-bram-types.cc b/techlibs/quicklogic/ql_bram_types.cc similarity index 100% rename from techlibs/quicklogic/ql-bram-types.cc rename to techlibs/quicklogic/ql_bram_types.cc diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc new file mode 100644 index 00000000000..217a5aa5573 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -0,0 +1,244 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_REGISTER_INPUTS_ID 92 +#define MODE_BITS_OUTPUT_SELECT_START_ID 81 +#define MODE_BITS_OUTPUT_SELECT_WIDTH 3 + +// ============================================================================ + +struct QlDspIORegs : public Pass { + + const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"}; + const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; + const std::vector ports2del_mult_add = {"dly_b"}; + const std::vector ports2del_extension = {"saturate_enable", "shift_right", "round"}; + + /// Temporary SigBit to SigBit helper map. + SigMap m_SigMap; + + // .......................................... + + QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {} + + void help() override + { + log("\n"); + log(" ql_dsp_io_regs [options] [selection]\n"); + log("\n"); + log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n"); + log("on their configuration.\n"); + } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_IO_REGS pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_io_regs_pass(module); + } + } + + // Returns a pair of mask and value describing constant bit connections of + // a SigSpec + std::pair get_constant_mask_value(const RTLIL::SigSpec *sigspec) + { + uint32_t mask = 0L; + uint32_t value = 0L; + + auto sigbits = sigspec->bits(); + for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) { + auto other = m_SigMap(sigbits[i]); + + mask <<= 1; + value <<= 1; + + // A known constant + if (!other.is_wire() && other.data != RTLIL::Sx) { + mask |= 0x1; + value |= (other.data == RTLIL::S1); + } + } + + return std::make_pair(mask, value); + } + + void ql_dsp_io_regs_pass(RTLIL::Module *module) + { + // Setup the SigMap + m_SigMap.clear(); + m_SigMap.set(module); + + for (auto cell : module->cells_) { + std::string cell_type = cell.second->type.str(); + if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) { + auto dsp = cell.second; + + // If the cell does not have the "is_inferred" attribute set + // then don't touch it. + if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) { + continue; + } + + bool del_clk = true; + bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3")); + + int reg_in_i; + int out_sel_i; + + // Get DSP configuration + if (use_dsp_cfg_params) { + // Read MODE_BITS at correct indexes + auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS")); + RTLIL::Const register_inputs; + register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID); + reg_in_i = register_inputs.as_int(); + + RTLIL::Const output_select; + output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH); + out_sel_i = output_select.as_int(); + } else { + // Read dedicated configuration ports + const RTLIL::SigSpec *register_inputs; + register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs")); + if (!register_inputs) + log_error("register_inputs port not found!"); + auto reg_in_c = register_inputs->as_const(); + reg_in_i = reg_in_c.as_int(); + + const RTLIL::SigSpec *output_select; + output_select = &dsp->getPort(RTLIL::escape_id("output_select")); + if (!output_select) + log_error("output_select port not found!"); + auto out_sel_c = output_select->as_const(); + out_sel_i = out_sel_c.as_int(); + } + + // Get the feedback port + const RTLIL::SigSpec *feedback; + feedback = &dsp->getPort(RTLIL::escape_id("feedback")); + if (!feedback) + log_error("feedback port not found!"); + + // Check if feedback is or can be set to 0 which implies MACC + auto feedback_con = get_constant_mask_value(feedback); + bool have_macc = (feedback_con.second == 0x0); + // log("mask=0x%08X value=0x%08X\n", consts.first, consts.second); + // log_error("=== END HERE ===\n"); + + // Build new type name + std::string new_type = cell_type; + new_type += "_MULT"; + + if (have_macc) { + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + del_clk = false; + new_type += "ACC"; + break; + default: + break; + } + } else { + switch (out_sel_i) { + case 1: + case 2: + case 3: + case 5: + case 7: + new_type += "ADD"; + break; + default: + break; + } + } + + if (reg_in_i) { + del_clk = false; + new_type += "_REGIN"; + } + + if (out_sel_i > 3) { + del_clk = false; + new_type += "_REGOUT"; + } + + // Set new type name + dsp->type = RTLIL::IdString(new_type); + + std::vector ports2del; + + if (del_clk) + ports2del.push_back("clk"); + + switch (out_sel_i) { + case 0: + case 4: + case 6: + ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end()); + // Mark for deleton additional configuration ports + if (!use_dsp_cfg_params) { + ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end()); + } + break; + case 1: + case 2: + case 3: + case 5: + case 7: + if (have_macc) { + ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end()); + } else { + ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end()); + } + break; + } + + for (auto portname : ports2del) { + const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname)); + if (!port) + log_error("%s port not found!", portname.c_str()); + dsp->connections_.erase(RTLIL::escape_id(portname)); + } + } + } + + // Clear the sigmap + m_SigMap.clear(); + } + +} QlDspIORegs; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc new file mode 100644 index 00000000000..ca898d9d0c2 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -0,0 +1,307 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + * + */ + +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "ql_dsp_macc_pm.h" + +// ============================================================================ + +bool use_dsp_cfg_params; + +static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) +{ + auto &st = pm.st_ql_dsp_macc; + + // Reject if multiplier drives anything else than either $add or $add and + // $mux + if (st.mux == nullptr && st.mul_nusers > 2) { + return; + } + + // Determine whether the output is taken from before or after the ff + bool out_ff; + if (st.ff_d_nusers == 2 && st.ff_q_nusers == 3) { + out_ff = true; + } else if (st.ff_d_nusers == 3 && st.ff_q_nusers == 2) { + out_ff = false; + } else { + // Illegal, cannot take the two outputs simulataneously + return; + } + + // No mux, the adder can driver either the ff or the ff + output + if (st.mux == nullptr) { + if (out_ff && st.add_nusers != 2) { + return; + } + if (!out_ff && st.add_nusers != 3) { + return; + } + } + // Mux present, the adder cannot drive anything else + else { + if (st.add_nusers != 2) { + return; + } + } + + // Mux can driver either the ff or the ff + output + if (st.mux != nullptr) { + if (out_ff && st.mux_nusers != 2) { + return; + } + if (!out_ff && st.mux_nusers != 3) { + return; + } + } + + // Accept only posedge clocked FFs + if (st.ff->getParam(ID(CLK_POLARITY)).as_int() != 1) { + return; + } + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t z_width = GetSize(st.ff->getPort(ID(Q))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool(); + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_z_width; + + string cell_base_name = "dsp_t1"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + // Too narrow + return; + } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { + cell_size_name = "_10x9x32"; + tgt_a_width = 10; + tgt_b_width = 9; + tgt_z_width = 19; + } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { + cell_size_name = "_20x18x64"; + tgt_a_width = 20; + tgt_b_width = 18; + tgt_z_width = 38; + } else { + // Too wide + return; + } + + if (use_dsp_cfg_params) + cell_cfg_name = "_cfg_params"; + else + cell_cfg_name = "_cfg_ports"; + + cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; + + type = RTLIL::escape_id(cell_full_name); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str()); + + for (auto cell : {st.mul, st.add, st.mux, st.ff}) { + if (cell != nullptr) { + log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(cell->type).c_str()); + } + } + + // Build the DSP cell name + std::string name; + name += RTLIL::unescape_id(st.mul->name) + "_"; + name += RTLIL::unescape_id(st.add->name) + "_"; + if (st.mux != nullptr) { + name += RTLIL::unescape_id(st.mux->name) + "_"; + } + name += RTLIL::unescape_id(st.ff->name); + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type); + + // Set attributes + cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a; + RTLIL::SigSpec sig_b; + RTLIL::SigSpec sig_z; + + if (a_width >= b_width) { + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + } else { + sig_a = st.mul->getPort(ID(B)); + sig_b = st.mul->getPort(ID(A)); + } + + sig_z = out_ff ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, a_signed); + sig_b.extend_u0(tgt_b_width, b_signed); + cell->setPort(RTLIL::escape_id("a_i"), sig_a); + cell->setPort(RTLIL::escape_id("b_i"), sig_b); + + // Connect output data port, pad if needed + if ((size_t)GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(RTLIL::escape_id("z_o"), sig_z); + + // Connect clock, reset and enable + cell->setPort(RTLIL::escape_id("clock_i"), st.ff->getPort(ID(CLK))); + + RTLIL::SigSpec rst; + RTLIL::SigSpec ena; + + if (st.ff->hasPort(ID(ARST))) { + if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { + rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + } else { + rst = st.ff->getPort(ID(ARST)); + } + } else { + rst = RTLIL::SigSpec(RTLIL::S0); + } + + if (st.ff->hasPort(ID(EN))) { + if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { + ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + } else { + ena = st.ff->getPort(ID(EN)); + } + } else { + ena = RTLIL::SigSpec(RTLIL::S1); + } + + cell->setPort(RTLIL::escape_id("reset_i"), rst); + cell->setPort(RTLIL::escape_id("load_acc_i"), ena); + + // Insert feedback_i control logic used for clearing / loading the accumulator + if (st.mux != nullptr) { + RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + + // Depending on the mux port ordering insert inverter if needed + log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B)); + if (st.mux_ab == ID(A)) { + sig_s = pm.module->Not(NEW_ID, sig_s); + } + + // Assemble the full control signal for the feedback_i port + RTLIL::SigSpec sig_f; + sig_f.append(sig_s); + sig_f.append(RTLIL::S0); + sig_f.append(RTLIL::S0); + cell->setPort(RTLIL::escape_id("feedback_i"), sig_f); + } + // No acc clear/load + else { + cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3)); + } + + // Connect control ports + cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); + + // Connect config bits + if (use_dsp_cfg_params) { + cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0)); + cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6)); + cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0)); + cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); + } else { + cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); + } + + bool subtract = (st.add->type == RTLIL::escape_id("$sub")); + cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); + if (st.mux != nullptr) { + pm.autoremove(st.mux); + } + pm.autoremove(st.ff); +} + +struct QlDspMacc : public Pass { + + QlDspMacc() : Pass("ql_dsp_macc", "Does something") {} + + void help() override + { + log("\n"); + log(" ql_dsp_macc [options] [selection]\n"); + log("\n"); + log(" -use_dsp_cfg_params\n"); + log(" By default use DSP blocks with configuration bits available at module ports.\n"); + log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n"); + log("\n"); + } + + void clear_flags() override { use_dsp_cfg_params = false; } + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_MACC pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + if (a_Args[argidx] == "-use_dsp_cfg_params") { + use_dsp_cfg_params = true; + continue; + } + + break; + } + extra_args(a_Args, argidx, a_Design); + + for (auto module : a_Design->selected_modules()) { + ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); + } + } + +} QlDspMacc; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_macc.pmg b/techlibs/quicklogic/ql_dsp_macc.pmg new file mode 100644 index 00000000000..4cfd15a2436 --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_macc.pmg @@ -0,0 +1,50 @@ +pattern ql_dsp_macc + +state add_ba +state mux_ab + +state mul_nusers +state add_nusers +state mux_nusers +state ff_d_nusers +state ff_q_nusers + +match mul + select mul->type.in($mul) + select nusers(port(mul, \Y)) <= 3 + set mul_nusers nusers(port(mul, \Y)) +endmatch + +match add + select add->type.in($add, $sub) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(add, AB) === port(mul, \Y) + select nusers(port(add, \Y)) <= 3 + set add_nusers nusers(port(add, \Y)) + set add_ba BA +endmatch + +match mux + select mux->type.in($mux) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(mux, AB) === port(mul, \Y) + index port(mux, BA) === port(add, \Y) + select nusers(port(mux, \Y)) <= 3 + set mux_nusers nusers(port(mux, \Y)) + set mux_ab AB + optional +endmatch + +match ff + select ff->type.in($dff, $adff, $dffe, $adffe) + index port(ff, \D) === (mux == nullptr ? port(add, \Y) : port(mux, \Y)) + index port(ff, \Q) === port(add, add_ba) + set ff_d_nusers nusers(port(ff, \D)) + set ff_q_nusers nusers(port(ff, \Q)) +endmatch + +code + accept; +endcode diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc new file mode 100644 index 00000000000..5213aa1c4ac --- /dev/null +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -0,0 +1,359 @@ +/* + * Copyright 2020-2022 F4PGA Authors + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define MODE_BITS_BASE_SIZE 80 +#define MODE_BITS_EXTENSION_SIZE 13 + +// ============================================================================ + +struct QlDspSimdPass : public Pass { + + QlDspSimdPass() : Pass("ql_dsp_simd", "Infers QuickLogic k6n10f DSP pairs that can operate in SIMD mode") {} + + void help() override + { + log("\n"); + log(" ql_dsp_simd [selection]\n"); + log("\n"); + log(" This pass identifies k6n10f DSP cells with identical configuration\n"); + log(" and packs pairs of them together into other DSP cells that can\n"); + log(" perform SIMD operation.\n"); + } + + // .......................................... + + /// Describes DSP config unique to a whole DSP cell + struct DspConfig { + + // Port connections + dict connections; + + // Whether DSPs pass configuration bits through ports of parameters + bool use_cfg_params; + + // TODO: Possibly include parameters here. For now we have just + // connections. + + DspConfig() = default; + + DspConfig(const DspConfig &ref) = default; + DspConfig(DspConfig &&ref) = default; + + unsigned int hash() const { return connections.hash(); } + + bool operator==(const DspConfig &ref) const { return connections == ref.connections && use_cfg_params == ref.use_cfg_params; } + }; + + // .......................................... + + // DSP control and config ports to consider and how to map them to ports + // of the target DSP cell + const std::vector> m_DspCfgPorts = {std::make_pair("clock_i", "clk"), + std::make_pair("reset_i", "reset"), + + std::make_pair("feedback_i", "feedback"), + std::make_pair("load_acc_i", "load_acc"), + std::make_pair("unsigned_a_i", "unsigned_a"), + std::make_pair("unsigned_b_i", "unsigned_b"), + + std::make_pair("subtract_i", "subtract")}; + // For QL_DSP2 expand with configuration ports + const std::vector> m_DspCfgPorts_expand = { + std::make_pair("output_select_i", "output_select"), std::make_pair("saturate_enable_i", "saturate_enable"), + std::make_pair("shift_right_i", "shift_right"), std::make_pair("round_i", "round"), std::make_pair("register_inputs_i", "register_inputs")}; + + // For QL_DSP3 use parameters instead + const std::vector m_DspParams2Mode = {"OUTPUT_SELECT", "SATURATE_ENABLE", "SHIFT_RIGHT", "ROUND", "REGISTER_INPUTS"}; + + // DSP data ports and how to map them to ports of the target DSP cell + const std::vector> m_DspDataPorts = { + std::make_pair("a_i", "a"), std::make_pair("b_i", "b"), std::make_pair("acc_fir_i", "acc_fir"), + std::make_pair("z_o", "z"), std::make_pair("dly_b_o", "dly_b"), + }; + + // DSP parameters + const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; + + // Source DSP cell type (SISD) + const std::string m_SisdDspType = "dsp_t1_10x9x32"; + // Suffix for DSP cell with configuration parameters + const std::string m_SisdDspType_cfg_params_suffix = "_cfg_params"; + + // Target DSP cell types for the SIMD mode + const std::string m_SimdDspType_cfg_ports = "QL_DSP2"; + const std::string m_SimdDspType_cfg_params = "QL_DSP3"; + + /// Temporary SigBit to SigBit helper map. + SigMap m_SigMap; + + // .......................................... + + void execute(std::vector a_Args, RTLIL::Design *a_Design) override + { + log_header(a_Design, "Executing QL_DSP_SIMD pass.\n"); + + // Parse args + extra_args(a_Args, 1, a_Design); + + // Process modules + for (auto module : a_Design->selected_modules()) { + + // Setup the SigMap + m_SigMap.clear(); + m_SigMap.set(module); + + // Assemble DSP cell groups + dict> groups; + for (auto cell : module->selected_cells()) { + + // Check if this is a DSP cell we are looking for (type starts with m_SisdDspType) + if (strncmp(cell->type.c_str(), RTLIL::escape_id(m_SisdDspType).c_str(), RTLIL::escape_id(m_SisdDspType).size()) != 0) { + continue; + } + + // Skip if it has the (* keep *) attribute set + if (cell->has_keep_attr()) { + continue; + } + + // Add to a group + const auto key = getDspConfig(cell); + groups[key].push_back(cell); + } + + std::vector cellsToRemove; + + // Map cell pairs to the target DSP SIMD cell + for (const auto &it : groups) { + const auto &group = it.second; + const auto &config = it.first; + + bool use_cfg_params = config.use_cfg_params; + // Ensure an even number + size_t count = group.size(); + if (count & 1) + count--; + + // Map SIMD pairs + for (size_t i = 0; i < count; i += 2) { + const RTLIL::Cell *dsp_a = group[i]; + const RTLIL::Cell *dsp_b = group[i + 1]; + + std::string name = stringf("simd%ld", i / 2); + std::string SimdDspType; + + if (use_cfg_params) + SimdDspType = m_SimdDspType_cfg_params; + else + SimdDspType = m_SimdDspType_cfg_ports; + + log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(dsp_a->name).c_str(), RTLIL::unescape_id(dsp_a->type).c_str(), + RTLIL::unescape_id(dsp_b->name).c_str(), RTLIL::unescape_id(dsp_b->type).c_str(), RTLIL::unescape_id(name).c_str(), + SimdDspType.c_str()); + + // Create the new cell + RTLIL::Cell *simd = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(SimdDspType)); + + // Check if the target cell is known (important to know + // its port widths) + if (!simd->known()) { + log_error(" The target cell type '%s' is not known!", SimdDspType.c_str()); + } + + std::vector> DspCfgPorts = m_DspCfgPorts; + if (!use_cfg_params) + DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + + // Connect common ports + for (const auto &it : DspCfgPorts) { + auto sport = RTLIL::escape_id(it.first); + auto dport = RTLIL::escape_id(it.second); + + simd->setPort(dport, config.connections.at(sport)); + } + + // Connect data ports + for (const auto &it : m_DspDataPorts) { + auto sport = RTLIL::escape_id(it.first); + auto dport = RTLIL::escape_id(it.second); + + size_t width; + bool isOutput; + + std::tie(width, isOutput) = getPortInfo(simd, dport); + + auto getConnection = [&](const RTLIL::Cell *cell) { + RTLIL::SigSpec sigspec; + if (cell->hasPort(sport)) { + const auto &sig = cell->getPort(sport); + sigspec.append(sig); + } + if (sigspec.bits().size() < width / 2) { + if (isOutput) { + for (size_t i = 0; i < width / 2 - sigspec.bits().size(); ++i) { + sigspec.append(RTLIL::SigSpec()); + } + } else { + sigspec.append(RTLIL::SigSpec(RTLIL::Sx, width / 2 - sigspec.bits().size())); + } + } + return sigspec; + }; + + RTLIL::SigSpec sigspec; + sigspec.append(getConnection(dsp_a)); + sigspec.append(getConnection(dsp_b)); + simd->setPort(dport, sigspec); + } + + // Concatenate FIR coefficient parameters into the single + // MODE_BITS parameter + std::vector mode_bits; + for (const auto &it : m_DspParams) { + auto val_a = dsp_a->getParam(RTLIL::escape_id(it)); + auto val_b = dsp_b->getParam(RTLIL::escape_id(it)); + + mode_bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); + } + long unsigned int mode_bits_size = MODE_BITS_BASE_SIZE; + if (use_cfg_params) { + // Add additional config parameters if necessary + mode_bits.push_back(RTLIL::S1); // MODE_BITS[80] == F_MODE : Enable fractured mode + for (const auto &it : m_DspParams2Mode) { + log_assert(dsp_a->getParam(RTLIL::escape_id(it)) == dsp_b->getParam(RTLIL::escape_id(it))); + auto param = dsp_a->getParam(RTLIL::escape_id(it)); + if (param.size() > 1) { + mode_bits.insert(mode_bits.end(), param.bits.begin(), param.bits.end()); + } else { + mode_bits.push_back(param.bits[0]); + } + } + mode_bits_size += MODE_BITS_EXTENSION_SIZE; + } else { + // Enable the fractured mode by connecting the control + // port. + simd->setPort(RTLIL::escape_id("f_mode"), RTLIL::S1); + } + simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits)); + log_assert(mode_bits.size() == mode_bits_size); + + // Handle the "is_inferred" attribute. If one of the fragments + // is not inferred mark the whole DSP as not inferred + bool is_inferred_a = + dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; + bool is_inferred_b = + dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; + + simd->set_bool_attribute(RTLIL::escape_id("is_inferred"), is_inferred_a && is_inferred_b); + + // Mark DSP parts for removal + cellsToRemove.push_back(dsp_a); + cellsToRemove.push_back(dsp_b); + } + } + + // Remove old cells + for (const auto &cell : cellsToRemove) { + module->remove(const_cast(cell)); + } + } + + // Clear + m_SigMap.clear(); + } + + // .......................................... + + /// Looks up port width and direction in the cell definition and returns it. + /// Returns (0, false) if it cannot be determined. + std::pair getPortInfo(RTLIL::Cell *a_Cell, RTLIL::IdString a_Port) + { + if (!a_Cell->known()) { + return std::make_pair(0, false); + } + + // Get the module defining the cell (the previous condition ensures + // that the pointers are valid) + RTLIL::Module *mod = a_Cell->module->design->module(a_Cell->type); + if (mod == nullptr) { + return std::make_pair(0, false); + } + + // Get the wire representing the port + RTLIL::Wire *wire = mod->wire(a_Port); + if (wire == nullptr) { + return std::make_pair(0, false); + } + + return std::make_pair(wire->width, wire->port_output); + } + + /// Given a DSP cell populates and returns a DspConfig struct for it. + DspConfig getDspConfig(RTLIL::Cell *a_Cell) + { + DspConfig config; + + string cell_type = a_Cell->type.str(); + string suffix = m_SisdDspType_cfg_params_suffix; + + bool use_cfg_params = cell_type.size() >= suffix.size() && 0 == cell_type.compare(cell_type.size() - suffix.size(), suffix.size(), suffix); + + std::vector> DspCfgPorts = m_DspCfgPorts; + if (!use_cfg_params) + DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + + config.use_cfg_params = use_cfg_params; + + for (const auto &it : DspCfgPorts) { + auto port = RTLIL::escape_id(it.first); + + // Port unconnected + if (!a_Cell->hasPort(port)) { + config.connections[port] = RTLIL::SigSpec(RTLIL::Sx); + continue; + } + + // Get the port connection and map it to unique SigBits + const auto &orgSigSpec = a_Cell->getPort(port); + const auto &orgSigBits = orgSigSpec.bits(); + + RTLIL::SigSpec newSigSpec; + for (size_t i = 0; i < orgSigBits.size(); ++i) { + auto newSigBit = m_SigMap(orgSigBits[i]); + newSigSpec.append(newSigBit); + } + + // Store + config.connections[port] = newSigSpec; + } + + return config; + } + +} QlDspSimdPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v new file mode 100644 index 00000000000..9eae617b90f --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v @@ -0,0 +1,265 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module dsp_t1_20x18x64_cfg_ports ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 # ( + .MODE_BITS ({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b0), // No fracturation + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + + input [2:0] output_select_i, + input saturate_enable_i, + input [5:0] shift_right_i, + input round_i, + input subtract_i, + input register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP2 # ( + .MODE_BITS ({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + + .f_mode (1'b1), // Enable fractuation, Use the lower half + .output_select (output_select_i), + .saturate_enable (saturate_enable_i), + .shift_right (shift_right_i), + .round (round_i), + .subtract (subtract_i), + .register_inputs (register_inputs_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input [19:0] a_i, + input [17:0] b_i, + input [ 5:0] acc_fir_i, + output [37:0] z_o, + output [17:0] dly_b_o, + + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a (a_i), + .b (b_i), + .acc_fir (acc_fir_i), + .z (z_o), + .dly_b (dly_b_o), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input [ 9:0] a_i, + input [ 8:0] b_i, + input [ 5:0] acc_fir_i, + output [18:0] z_o, + output [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input clock_i, + input reset_i, + + input [2:0] feedback_i, + input load_acc_i, + input unsigned_a_i, + input unsigned_b_i, + input subtract_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + parameter [2:0] OUTPUT_SELECT = 3'd0; + parameter [0:0] SATURATE_ENABLE = 1'd0; + parameter [5:0] SHIFT_RIGHT = 6'd0; + parameter [0:0] ROUND = 1'd0; + parameter [0:0] REGISTER_INPUTS = 1'd0; + + wire [37:0] z; + wire [17:0] dly_b; + + QL_DSP3 # ( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) _TECHMAP_REPLACE_ ( + .a ({10'd0, a_i}), + .b ({ 9'd0, b_i}), + .acc_fir (acc_fir_i), + .z (z), + .dly_b (dly_b), + + .clk (clock_i), + .reset (reset_i), + + .feedback (feedback_i), + .load_acc (load_acc_i), + .unsigned_a (unsigned_a_i), + .unsigned_b (unsigned_b_i), + .subtract (subtract_i) + ); + + assign z_o = z[18:0]; + assign dly_b_o = dly_b_o[8:0]; + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v new file mode 100644 index 00000000000..bb9f05283e7 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v @@ -0,0 +1,147 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [19:0] a; + wire [17:0] b; + wire [37:0] z; + + assign a = (A_WIDTH == 20) ? A : + (A_SIGNED) ? {{(20 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(20 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 18) ? B : + (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{(18 - B_WIDTH){1'b0}}, B}; + + generate if (`USE_DSP_CFG_PARAMS == 0) begin + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + end else begin + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_params #( + .OUTPUT_SELECT (3'd0), + .SATURATE_ENABLE (1'b0), + .SHIFT_RIGHT (6'd0), + .ROUND (1'b0), + .REGISTER_INPUTS (1'b0) + ) TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .subtract_i (1'b0) + ); + end endgenerate + + assign Y = z; + +endmodule + +module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [ 9:0] a; + wire [ 8:0] b; + wire [18:0] z; + + assign a = (A_WIDTH == 10) ? A : + (A_SIGNED) ? {{(10 - A_WIDTH){A[A_WIDTH-1]}}, A} : + {{(10 - A_WIDTH){1'b0}}, A}; + + assign b = (B_WIDTH == 9) ? B : + (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} : + {{( 9 - B_WIDTH){1'b0}}, B}; + + generate if (`USE_DSP_CFG_PARAMS == 0) begin + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + end else begin + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_params #( + .OUTPUT_SELECT (3'd0), + .SATURATE_ENABLE (1'b0), + .SHIFT_RIGHT (6'd0), + .ROUND (1'b0), + .REGISTER_INPUTS (1'b0) + ) TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .subtract_i (1'b0) + ); + end endgenerate + + assign Y = z; + +endmodule diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v new file mode 100644 index 00000000000..05a4835e868 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v @@ -0,0 +1,5753 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`timescale 1ps/1ps + +`default_nettype none + +(* blackbox *) +module QL_DSP1 ( + input wire [19:0] a, + input wire [17:0] b, + (* clkbuf_sink *) + input wire clk0, + (* clkbuf_sink *) + input wire clk1, + input wire [ 1:0] feedback0, + input wire [ 1:0] feedback1, + input wire load_acc0, + input wire load_acc1, + input wire reset0, + input wire reset1, + output reg [37:0] z +); + parameter MODE_BITS = 27'b00000000000000000000000000; +endmodule /* QL_DSP1 */ + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// --------- Control bits in ports -------- // +// ---------------------------------------- // + +module QL_DSP2 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire saturate_enable, + input wire [5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + wire [NBITS_Z-1:0] dsp_full_z; + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [NBITS_B-1:0] dsp_full_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + assign z = f_mode ? {dsp_frac1_z, dsp_frac0_z} : dsp_full_z; + assign dly_b = f_mode ? {dsp_frac1_dly_b, dsp_frac0_dly_b} : dsp_full_dly_b; + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + // Output used when fmode == 1 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A/2), + .NBITS_B(NBITS_B/2), + .NBITS_ACC(NBITS_ACC/2), + .NBITS_Z(NBITS_Z/2) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + // Output used when fmode == 0 + dsp_t1_sim_cfg_ports #( + .NBITS_A(NBITS_A), + .NBITS_B(NBITS_B), + .NBITS_ACC(NBITS_ACC), + .NBITS_Z(NBITS_Z) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(dsp_full_z), + .dly_b_o(dsp_full_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .saturate_enable_i(saturate_enable), + .output_select_i(output_select), + .round_i(round), + .shift_right_i(shift_right), + .subtract_i(subtract), + .register_inputs_i(register_inputs), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); +endmodule + +module QL_DSP2_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .clk(1'b0), + .reset(reset), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: a * b (0) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + input wire f_mode, + input wire [2:0] output_select, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(1'b0), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: a * b (4) + .saturate_enable(1'b0), + .shift_right(6'b0), + .round(1'b0), + .subtract(1'b0), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + //.clk(1'b0), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (a[0] => z[0]) = 0; + (a[1] => z[0]) = 0; + (a[2] => z[0]) = 0; + (a[3] => z[0]) = 0; + (a[4] => z[0]) = 0; + (a[5] => z[0]) = 0; + (a[6] => z[0]) = 0; + (a[7] => z[0]) = 0; + (a[8] => z[0]) = 0; + (a[9] => z[0]) = 0; + (a[10] => z[0]) = 0; + (a[11] => z[0]) = 0; + (a[12] => z[0]) = 0; + (a[13] => z[0]) = 0; + (a[14] => z[0]) = 0; + (a[15] => z[0]) = 0; + (a[16] => z[0]) = 0; + (a[17] => z[0]) = 0; + (a[18] => z[0]) = 0; + (a[19] => z[0]) = 0; + (b[0] => z[0]) = 0; + (b[1] => z[0]) = 0; + (b[2] => z[0]) = 0; + (b[3] => z[0]) = 0; + (b[4] => z[0]) = 0; + (b[5] => z[0]) = 0; + (b[6] => z[0]) = 0; + (b[7] => z[0]) = 0; + (b[8] => z[0]) = 0; + (b[9] => z[0]) = 0; + (b[10] => z[0]) = 0; + (b[11] => z[0]) = 0; + (b[12] => z[0]) = 0; + (b[13] => z[0]) = 0; + (b[14] => z[0]) = 0; + (b[15] => z[0]) = 0; + (b[16] => z[0]) = 0; + (b[17] => z[0]) = 0; + (a[0] => z[1]) = 0; + (a[1] => z[1]) = 0; + (a[2] => z[1]) = 0; + (a[3] => z[1]) = 0; + (a[4] => z[1]) = 0; + (a[5] => z[1]) = 0; + (a[6] => z[1]) = 0; + (a[7] => z[1]) = 0; + (a[8] => z[1]) = 0; + (a[9] => z[1]) = 0; + (a[10] => z[1]) = 0; + (a[11] => z[1]) = 0; + (a[12] => z[1]) = 0; + (a[13] => z[1]) = 0; + (a[14] => z[1]) = 0; + (a[15] => z[1]) = 0; + (a[16] => z[1]) = 0; + (a[17] => z[1]) = 0; + (a[18] => z[1]) = 0; + (a[19] => z[1]) = 0; + (b[0] => z[1]) = 0; + (b[1] => z[1]) = 0; + (b[2] => z[1]) = 0; + (b[3] => z[1]) = 0; + (b[4] => z[1]) = 0; + (b[5] => z[1]) = 0; + (b[6] => z[1]) = 0; + (b[7] => z[1]) = 0; + (b[8] => z[1]) = 0; + (b[9] => z[1]) = 0; + (b[10] => z[1]) = 0; + (b[11] => z[1]) = 0; + (b[12] => z[1]) = 0; + (b[13] => z[1]) = 0; + (b[14] => z[1]) = 0; + (b[15] => z[1]) = 0; + (b[16] => z[1]) = 0; + (b[17] => z[1]) = 0; + (a[0] => z[2]) = 0; + (a[1] => z[2]) = 0; + (a[2] => z[2]) = 0; + (a[3] => z[2]) = 0; + (a[4] => z[2]) = 0; + (a[5] => z[2]) = 0; + (a[6] => z[2]) = 0; + (a[7] => z[2]) = 0; + (a[8] => z[2]) = 0; + (a[9] => z[2]) = 0; + (a[10] => z[2]) = 0; + (a[11] => z[2]) = 0; + (a[12] => z[2]) = 0; + (a[13] => z[2]) = 0; + (a[14] => z[2]) = 0; + (a[15] => z[2]) = 0; + (a[16] => z[2]) = 0; + (a[17] => z[2]) = 0; + (a[18] => z[2]) = 0; + (a[19] => z[2]) = 0; + (b[0] => z[2]) = 0; + (b[1] => z[2]) = 0; + (b[2] => z[2]) = 0; + (b[3] => z[2]) = 0; + (b[4] => z[2]) = 0; + (b[5] => z[2]) = 0; + (b[6] => z[2]) = 0; + (b[7] => z[2]) = 0; + (b[8] => z[2]) = 0; + (b[9] => z[2]) = 0; + (b[10] => z[2]) = 0; + (b[11] => z[2]) = 0; + (b[12] => z[2]) = 0; + (b[13] => z[2]) = 0; + (b[14] => z[2]) = 0; + (b[15] => z[2]) = 0; + (b[16] => z[2]) = 0; + (b[17] => z[2]) = 0; + (a[0] => z[3]) = 0; + (a[1] => z[3]) = 0; + (a[2] => z[3]) = 0; + (a[3] => z[3]) = 0; + (a[4] => z[3]) = 0; + (a[5] => z[3]) = 0; + (a[6] => z[3]) = 0; + (a[7] => z[3]) = 0; + (a[8] => z[3]) = 0; + (a[9] => z[3]) = 0; + (a[10] => z[3]) = 0; + (a[11] => z[3]) = 0; + (a[12] => z[3]) = 0; + (a[13] => z[3]) = 0; + (a[14] => z[3]) = 0; + (a[15] => z[3]) = 0; + (a[16] => z[3]) = 0; + (a[17] => z[3]) = 0; + (a[18] => z[3]) = 0; + (a[19] => z[3]) = 0; + (b[0] => z[3]) = 0; + (b[1] => z[3]) = 0; + (b[2] => z[3]) = 0; + (b[3] => z[3]) = 0; + (b[4] => z[3]) = 0; + (b[5] => z[3]) = 0; + (b[6] => z[3]) = 0; + (b[7] => z[3]) = 0; + (b[8] => z[3]) = 0; + (b[9] => z[3]) = 0; + (b[10] => z[3]) = 0; + (b[11] => z[3]) = 0; + (b[12] => z[3]) = 0; + (b[13] => z[3]) = 0; + (b[14] => z[3]) = 0; + (b[15] => z[3]) = 0; + (b[16] => z[3]) = 0; + (b[17] => z[3]) = 0; + (a[0] => z[4]) = 0; + (a[1] => z[4]) = 0; + (a[2] => z[4]) = 0; + (a[3] => z[4]) = 0; + (a[4] => z[4]) = 0; + (a[5] => z[4]) = 0; + (a[6] => z[4]) = 0; + (a[7] => z[4]) = 0; + (a[8] => z[4]) = 0; + (a[9] => z[4]) = 0; + (a[10] => z[4]) = 0; + (a[11] => z[4]) = 0; + (a[12] => z[4]) = 0; + (a[13] => z[4]) = 0; + (a[14] => z[4]) = 0; + (a[15] => z[4]) = 0; + (a[16] => z[4]) = 0; + (a[17] => z[4]) = 0; + (a[18] => z[4]) = 0; + (a[19] => z[4]) = 0; + (b[0] => z[4]) = 0; + (b[1] => z[4]) = 0; + (b[2] => z[4]) = 0; + (b[3] => z[4]) = 0; + (b[4] => z[4]) = 0; + (b[5] => z[4]) = 0; + (b[6] => z[4]) = 0; + (b[7] => z[4]) = 0; + (b[8] => z[4]) = 0; + (b[9] => z[4]) = 0; + (b[10] => z[4]) = 0; + (b[11] => z[4]) = 0; + (b[12] => z[4]) = 0; + (b[13] => z[4]) = 0; + (b[14] => z[4]) = 0; + (b[15] => z[4]) = 0; + (b[16] => z[4]) = 0; + (b[17] => z[4]) = 0; + (a[0] => z[5]) = 0; + (a[1] => z[5]) = 0; + (a[2] => z[5]) = 0; + (a[3] => z[5]) = 0; + (a[4] => z[5]) = 0; + (a[5] => z[5]) = 0; + (a[6] => z[5]) = 0; + (a[7] => z[5]) = 0; + (a[8] => z[5]) = 0; + (a[9] => z[5]) = 0; + (a[10] => z[5]) = 0; + (a[11] => z[5]) = 0; + (a[12] => z[5]) = 0; + (a[13] => z[5]) = 0; + (a[14] => z[5]) = 0; + (a[15] => z[5]) = 0; + (a[16] => z[5]) = 0; + (a[17] => z[5]) = 0; + (a[18] => z[5]) = 0; + (a[19] => z[5]) = 0; + (b[0] => z[5]) = 0; + (b[1] => z[5]) = 0; + (b[2] => z[5]) = 0; + (b[3] => z[5]) = 0; + (b[4] => z[5]) = 0; + (b[5] => z[5]) = 0; + (b[6] => z[5]) = 0; + (b[7] => z[5]) = 0; + (b[8] => z[5]) = 0; + (b[9] => z[5]) = 0; + (b[10] => z[5]) = 0; + (b[11] => z[5]) = 0; + (b[12] => z[5]) = 0; + (b[13] => z[5]) = 0; + (b[14] => z[5]) = 0; + (b[15] => z[5]) = 0; + (b[16] => z[5]) = 0; + (b[17] => z[5]) = 0; + (a[0] => z[6]) = 0; + (a[1] => z[6]) = 0; + (a[2] => z[6]) = 0; + (a[3] => z[6]) = 0; + (a[4] => z[6]) = 0; + (a[5] => z[6]) = 0; + (a[6] => z[6]) = 0; + (a[7] => z[6]) = 0; + (a[8] => z[6]) = 0; + (a[9] => z[6]) = 0; + (a[10] => z[6]) = 0; + (a[11] => z[6]) = 0; + (a[12] => z[6]) = 0; + (a[13] => z[6]) = 0; + (a[14] => z[6]) = 0; + (a[15] => z[6]) = 0; + (a[16] => z[6]) = 0; + (a[17] => z[6]) = 0; + (a[18] => z[6]) = 0; + (a[19] => z[6]) = 0; + (b[0] => z[6]) = 0; + (b[1] => z[6]) = 0; + (b[2] => z[6]) = 0; + (b[3] => z[6]) = 0; + (b[4] => z[6]) = 0; + (b[5] => z[6]) = 0; + (b[6] => z[6]) = 0; + (b[7] => z[6]) = 0; + (b[8] => z[6]) = 0; + (b[9] => z[6]) = 0; + (b[10] => z[6]) = 0; + (b[11] => z[6]) = 0; + (b[12] => z[6]) = 0; + (b[13] => z[6]) = 0; + (b[14] => z[6]) = 0; + (b[15] => z[6]) = 0; + (b[16] => z[6]) = 0; + (b[17] => z[6]) = 0; + (a[0] => z[7]) = 0; + (a[1] => z[7]) = 0; + (a[2] => z[7]) = 0; + (a[3] => z[7]) = 0; + (a[4] => z[7]) = 0; + (a[5] => z[7]) = 0; + (a[6] => z[7]) = 0; + (a[7] => z[7]) = 0; + (a[8] => z[7]) = 0; + (a[9] => z[7]) = 0; + (a[10] => z[7]) = 0; + (a[11] => z[7]) = 0; + (a[12] => z[7]) = 0; + (a[13] => z[7]) = 0; + (a[14] => z[7]) = 0; + (a[15] => z[7]) = 0; + (a[16] => z[7]) = 0; + (a[17] => z[7]) = 0; + (a[18] => z[7]) = 0; + (a[19] => z[7]) = 0; + (b[0] => z[7]) = 0; + (b[1] => z[7]) = 0; + (b[2] => z[7]) = 0; + (b[3] => z[7]) = 0; + (b[4] => z[7]) = 0; + (b[5] => z[7]) = 0; + (b[6] => z[7]) = 0; + (b[7] => z[7]) = 0; + (b[8] => z[7]) = 0; + (b[9] => z[7]) = 0; + (b[10] => z[7]) = 0; + (b[11] => z[7]) = 0; + (b[12] => z[7]) = 0; + (b[13] => z[7]) = 0; + (b[14] => z[7]) = 0; + (b[15] => z[7]) = 0; + (b[16] => z[7]) = 0; + (b[17] => z[7]) = 0; + (a[0] => z[8]) = 0; + (a[1] => z[8]) = 0; + (a[2] => z[8]) = 0; + (a[3] => z[8]) = 0; + (a[4] => z[8]) = 0; + (a[5] => z[8]) = 0; + (a[6] => z[8]) = 0; + (a[7] => z[8]) = 0; + (a[8] => z[8]) = 0; + (a[9] => z[8]) = 0; + (a[10] => z[8]) = 0; + (a[11] => z[8]) = 0; + (a[12] => z[8]) = 0; + (a[13] => z[8]) = 0; + (a[14] => z[8]) = 0; + (a[15] => z[8]) = 0; + (a[16] => z[8]) = 0; + (a[17] => z[8]) = 0; + (a[18] => z[8]) = 0; + (a[19] => z[8]) = 0; + (b[0] => z[8]) = 0; + (b[1] => z[8]) = 0; + (b[2] => z[8]) = 0; + (b[3] => z[8]) = 0; + (b[4] => z[8]) = 0; + (b[5] => z[8]) = 0; + (b[6] => z[8]) = 0; + (b[7] => z[8]) = 0; + (b[8] => z[8]) = 0; + (b[9] => z[8]) = 0; + (b[10] => z[8]) = 0; + (b[11] => z[8]) = 0; + (b[12] => z[8]) = 0; + (b[13] => z[8]) = 0; + (b[14] => z[8]) = 0; + (b[15] => z[8]) = 0; + (b[16] => z[8]) = 0; + (b[17] => z[8]) = 0; + (a[0] => z[9]) = 0; + (a[1] => z[9]) = 0; + (a[2] => z[9]) = 0; + (a[3] => z[9]) = 0; + (a[4] => z[9]) = 0; + (a[5] => z[9]) = 0; + (a[6] => z[9]) = 0; + (a[7] => z[9]) = 0; + (a[8] => z[9]) = 0; + (a[9] => z[9]) = 0; + (a[10] => z[9]) = 0; + (a[11] => z[9]) = 0; + (a[12] => z[9]) = 0; + (a[13] => z[9]) = 0; + (a[14] => z[9]) = 0; + (a[15] => z[9]) = 0; + (a[16] => z[9]) = 0; + (a[17] => z[9]) = 0; + (a[18] => z[9]) = 0; + (a[19] => z[9]) = 0; + (b[0] => z[9]) = 0; + (b[1] => z[9]) = 0; + (b[2] => z[9]) = 0; + (b[3] => z[9]) = 0; + (b[4] => z[9]) = 0; + (b[5] => z[9]) = 0; + (b[6] => z[9]) = 0; + (b[7] => z[9]) = 0; + (b[8] => z[9]) = 0; + (b[9] => z[9]) = 0; + (b[10] => z[9]) = 0; + (b[11] => z[9]) = 0; + (b[12] => z[9]) = 0; + (b[13] => z[9]) = 0; + (b[14] => z[9]) = 0; + (b[15] => z[9]) = 0; + (b[16] => z[9]) = 0; + (b[17] => z[9]) = 0; + (a[0] => z[10]) = 0; + (a[1] => z[10]) = 0; + (a[2] => z[10]) = 0; + (a[3] => z[10]) = 0; + (a[4] => z[10]) = 0; + (a[5] => z[10]) = 0; + (a[6] => z[10]) = 0; + (a[7] => z[10]) = 0; + (a[8] => z[10]) = 0; + (a[9] => z[10]) = 0; + (a[10] => z[10]) = 0; + (a[11] => z[10]) = 0; + (a[12] => z[10]) = 0; + (a[13] => z[10]) = 0; + (a[14] => z[10]) = 0; + (a[15] => z[10]) = 0; + (a[16] => z[10]) = 0; + (a[17] => z[10]) = 0; + (a[18] => z[10]) = 0; + (a[19] => z[10]) = 0; + (b[0] => z[10]) = 0; + (b[1] => z[10]) = 0; + (b[2] => z[10]) = 0; + (b[3] => z[10]) = 0; + (b[4] => z[10]) = 0; + (b[5] => z[10]) = 0; + (b[6] => z[10]) = 0; + (b[7] => z[10]) = 0; + (b[8] => z[10]) = 0; + (b[9] => z[10]) = 0; + (b[10] => z[10]) = 0; + (b[11] => z[10]) = 0; + (b[12] => z[10]) = 0; + (b[13] => z[10]) = 0; + (b[14] => z[10]) = 0; + (b[15] => z[10]) = 0; + (b[16] => z[10]) = 0; + (b[17] => z[10]) = 0; + (a[0] => z[11]) = 0; + (a[1] => z[11]) = 0; + (a[2] => z[11]) = 0; + (a[3] => z[11]) = 0; + (a[4] => z[11]) = 0; + (a[5] => z[11]) = 0; + (a[6] => z[11]) = 0; + (a[7] => z[11]) = 0; + (a[8] => z[11]) = 0; + (a[9] => z[11]) = 0; + (a[10] => z[11]) = 0; + (a[11] => z[11]) = 0; + (a[12] => z[11]) = 0; + (a[13] => z[11]) = 0; + (a[14] => z[11]) = 0; + (a[15] => z[11]) = 0; + (a[16] => z[11]) = 0; + (a[17] => z[11]) = 0; + (a[18] => z[11]) = 0; + (a[19] => z[11]) = 0; + (b[0] => z[11]) = 0; + (b[1] => z[11]) = 0; + (b[2] => z[11]) = 0; + (b[3] => z[11]) = 0; + (b[4] => z[11]) = 0; + (b[5] => z[11]) = 0; + (b[6] => z[11]) = 0; + (b[7] => z[11]) = 0; + (b[8] => z[11]) = 0; + (b[9] => z[11]) = 0; + (b[10] => z[11]) = 0; + (b[11] => z[11]) = 0; + (b[12] => z[11]) = 0; + (b[13] => z[11]) = 0; + (b[14] => z[11]) = 0; + (b[15] => z[11]) = 0; + (b[16] => z[11]) = 0; + (b[17] => z[11]) = 0; + (a[0] => z[12]) = 0; + (a[1] => z[12]) = 0; + (a[2] => z[12]) = 0; + (a[3] => z[12]) = 0; + (a[4] => z[12]) = 0; + (a[5] => z[12]) = 0; + (a[6] => z[12]) = 0; + (a[7] => z[12]) = 0; + (a[8] => z[12]) = 0; + (a[9] => z[12]) = 0; + (a[10] => z[12]) = 0; + (a[11] => z[12]) = 0; + (a[12] => z[12]) = 0; + (a[13] => z[12]) = 0; + (a[14] => z[12]) = 0; + (a[15] => z[12]) = 0; + (a[16] => z[12]) = 0; + (a[17] => z[12]) = 0; + (a[18] => z[12]) = 0; + (a[19] => z[12]) = 0; + (b[0] => z[12]) = 0; + (b[1] => z[12]) = 0; + (b[2] => z[12]) = 0; + (b[3] => z[12]) = 0; + (b[4] => z[12]) = 0; + (b[5] => z[12]) = 0; + (b[6] => z[12]) = 0; + (b[7] => z[12]) = 0; + (b[8] => z[12]) = 0; + (b[9] => z[12]) = 0; + (b[10] => z[12]) = 0; + (b[11] => z[12]) = 0; + (b[12] => z[12]) = 0; + (b[13] => z[12]) = 0; + (b[14] => z[12]) = 0; + (b[15] => z[12]) = 0; + (b[16] => z[12]) = 0; + (b[17] => z[12]) = 0; + (a[0] => z[13]) = 0; + (a[1] => z[13]) = 0; + (a[2] => z[13]) = 0; + (a[3] => z[13]) = 0; + (a[4] => z[13]) = 0; + (a[5] => z[13]) = 0; + (a[6] => z[13]) = 0; + (a[7] => z[13]) = 0; + (a[8] => z[13]) = 0; + (a[9] => z[13]) = 0; + (a[10] => z[13]) = 0; + (a[11] => z[13]) = 0; + (a[12] => z[13]) = 0; + (a[13] => z[13]) = 0; + (a[14] => z[13]) = 0; + (a[15] => z[13]) = 0; + (a[16] => z[13]) = 0; + (a[17] => z[13]) = 0; + (a[18] => z[13]) = 0; + (a[19] => z[13]) = 0; + (b[0] => z[13]) = 0; + (b[1] => z[13]) = 0; + (b[2] => z[13]) = 0; + (b[3] => z[13]) = 0; + (b[4] => z[13]) = 0; + (b[5] => z[13]) = 0; + (b[6] => z[13]) = 0; + (b[7] => z[13]) = 0; + (b[8] => z[13]) = 0; + (b[9] => z[13]) = 0; + (b[10] => z[13]) = 0; + (b[11] => z[13]) = 0; + (b[12] => z[13]) = 0; + (b[13] => z[13]) = 0; + (b[14] => z[13]) = 0; + (b[15] => z[13]) = 0; + (b[16] => z[13]) = 0; + (b[17] => z[13]) = 0; + (a[0] => z[14]) = 0; + (a[1] => z[14]) = 0; + (a[2] => z[14]) = 0; + (a[3] => z[14]) = 0; + (a[4] => z[14]) = 0; + (a[5] => z[14]) = 0; + (a[6] => z[14]) = 0; + (a[7] => z[14]) = 0; + (a[8] => z[14]) = 0; + (a[9] => z[14]) = 0; + (a[10] => z[14]) = 0; + (a[11] => z[14]) = 0; + (a[12] => z[14]) = 0; + (a[13] => z[14]) = 0; + (a[14] => z[14]) = 0; + (a[15] => z[14]) = 0; + (a[16] => z[14]) = 0; + (a[17] => z[14]) = 0; + (a[18] => z[14]) = 0; + (a[19] => z[14]) = 0; + (b[0] => z[14]) = 0; + (b[1] => z[14]) = 0; + (b[2] => z[14]) = 0; + (b[3] => z[14]) = 0; + (b[4] => z[14]) = 0; + (b[5] => z[14]) = 0; + (b[6] => z[14]) = 0; + (b[7] => z[14]) = 0; + (b[8] => z[14]) = 0; + (b[9] => z[14]) = 0; + (b[10] => z[14]) = 0; + (b[11] => z[14]) = 0; + (b[12] => z[14]) = 0; + (b[13] => z[14]) = 0; + (b[14] => z[14]) = 0; + (b[15] => z[14]) = 0; + (b[16] => z[14]) = 0; + (b[17] => z[14]) = 0; + (a[0] => z[15]) = 0; + (a[1] => z[15]) = 0; + (a[2] => z[15]) = 0; + (a[3] => z[15]) = 0; + (a[4] => z[15]) = 0; + (a[5] => z[15]) = 0; + (a[6] => z[15]) = 0; + (a[7] => z[15]) = 0; + (a[8] => z[15]) = 0; + (a[9] => z[15]) = 0; + (a[10] => z[15]) = 0; + (a[11] => z[15]) = 0; + (a[12] => z[15]) = 0; + (a[13] => z[15]) = 0; + (a[14] => z[15]) = 0; + (a[15] => z[15]) = 0; + (a[16] => z[15]) = 0; + (a[17] => z[15]) = 0; + (a[18] => z[15]) = 0; + (a[19] => z[15]) = 0; + (b[0] => z[15]) = 0; + (b[1] => z[15]) = 0; + (b[2] => z[15]) = 0; + (b[3] => z[15]) = 0; + (b[4] => z[15]) = 0; + (b[5] => z[15]) = 0; + (b[6] => z[15]) = 0; + (b[7] => z[15]) = 0; + (b[8] => z[15]) = 0; + (b[9] => z[15]) = 0; + (b[10] => z[15]) = 0; + (b[11] => z[15]) = 0; + (b[12] => z[15]) = 0; + (b[13] => z[15]) = 0; + (b[14] => z[15]) = 0; + (b[15] => z[15]) = 0; + (b[16] => z[15]) = 0; + (b[17] => z[15]) = 0; + (a[0] => z[16]) = 0; + (a[1] => z[16]) = 0; + (a[2] => z[16]) = 0; + (a[3] => z[16]) = 0; + (a[4] => z[16]) = 0; + (a[5] => z[16]) = 0; + (a[6] => z[16]) = 0; + (a[7] => z[16]) = 0; + (a[8] => z[16]) = 0; + (a[9] => z[16]) = 0; + (a[10] => z[16]) = 0; + (a[11] => z[16]) = 0; + (a[12] => z[16]) = 0; + (a[13] => z[16]) = 0; + (a[14] => z[16]) = 0; + (a[15] => z[16]) = 0; + (a[16] => z[16]) = 0; + (a[17] => z[16]) = 0; + (a[18] => z[16]) = 0; + (a[19] => z[16]) = 0; + (b[0] => z[16]) = 0; + (b[1] => z[16]) = 0; + (b[2] => z[16]) = 0; + (b[3] => z[16]) = 0; + (b[4] => z[16]) = 0; + (b[5] => z[16]) = 0; + (b[6] => z[16]) = 0; + (b[7] => z[16]) = 0; + (b[8] => z[16]) = 0; + (b[9] => z[16]) = 0; + (b[10] => z[16]) = 0; + (b[11] => z[16]) = 0; + (b[12] => z[16]) = 0; + (b[13] => z[16]) = 0; + (b[14] => z[16]) = 0; + (b[15] => z[16]) = 0; + (b[16] => z[16]) = 0; + (b[17] => z[16]) = 0; + (a[0] => z[17]) = 0; + (a[1] => z[17]) = 0; + (a[2] => z[17]) = 0; + (a[3] => z[17]) = 0; + (a[4] => z[17]) = 0; + (a[5] => z[17]) = 0; + (a[6] => z[17]) = 0; + (a[7] => z[17]) = 0; + (a[8] => z[17]) = 0; + (a[9] => z[17]) = 0; + (a[10] => z[17]) = 0; + (a[11] => z[17]) = 0; + (a[12] => z[17]) = 0; + (a[13] => z[17]) = 0; + (a[14] => z[17]) = 0; + (a[15] => z[17]) = 0; + (a[16] => z[17]) = 0; + (a[17] => z[17]) = 0; + (a[18] => z[17]) = 0; + (a[19] => z[17]) = 0; + (b[0] => z[17]) = 0; + (b[1] => z[17]) = 0; + (b[2] => z[17]) = 0; + (b[3] => z[17]) = 0; + (b[4] => z[17]) = 0; + (b[5] => z[17]) = 0; + (b[6] => z[17]) = 0; + (b[7] => z[17]) = 0; + (b[8] => z[17]) = 0; + (b[9] => z[17]) = 0; + (b[10] => z[17]) = 0; + (b[11] => z[17]) = 0; + (b[12] => z[17]) = 0; + (b[13] => z[17]) = 0; + (b[14] => z[17]) = 0; + (b[15] => z[17]) = 0; + (b[16] => z[17]) = 0; + (b[17] => z[17]) = 0; + (a[0] => z[18]) = 0; + (a[1] => z[18]) = 0; + (a[2] => z[18]) = 0; + (a[3] => z[18]) = 0; + (a[4] => z[18]) = 0; + (a[5] => z[18]) = 0; + (a[6] => z[18]) = 0; + (a[7] => z[18]) = 0; + (a[8] => z[18]) = 0; + (a[9] => z[18]) = 0; + (a[10] => z[18]) = 0; + (a[11] => z[18]) = 0; + (a[12] => z[18]) = 0; + (a[13] => z[18]) = 0; + (a[14] => z[18]) = 0; + (a[15] => z[18]) = 0; + (a[16] => z[18]) = 0; + (a[17] => z[18]) = 0; + (a[18] => z[18]) = 0; + (a[19] => z[18]) = 0; + (b[0] => z[18]) = 0; + (b[1] => z[18]) = 0; + (b[2] => z[18]) = 0; + (b[3] => z[18]) = 0; + (b[4] => z[18]) = 0; + (b[5] => z[18]) = 0; + (b[6] => z[18]) = 0; + (b[7] => z[18]) = 0; + (b[8] => z[18]) = 0; + (b[9] => z[18]) = 0; + (b[10] => z[18]) = 0; + (b[11] => z[18]) = 0; + (b[12] => z[18]) = 0; + (b[13] => z[18]) = 0; + (b[14] => z[18]) = 0; + (b[15] => z[18]) = 0; + (b[16] => z[18]) = 0; + (b[17] => z[18]) = 0; + (a[0] => z[19]) = 0; + (a[1] => z[19]) = 0; + (a[2] => z[19]) = 0; + (a[3] => z[19]) = 0; + (a[4] => z[19]) = 0; + (a[5] => z[19]) = 0; + (a[6] => z[19]) = 0; + (a[7] => z[19]) = 0; + (a[8] => z[19]) = 0; + (a[9] => z[19]) = 0; + (a[10] => z[19]) = 0; + (a[11] => z[19]) = 0; + (a[12] => z[19]) = 0; + (a[13] => z[19]) = 0; + (a[14] => z[19]) = 0; + (a[15] => z[19]) = 0; + (a[16] => z[19]) = 0; + (a[17] => z[19]) = 0; + (a[18] => z[19]) = 0; + (a[19] => z[19]) = 0; + (b[0] => z[19]) = 0; + (b[1] => z[19]) = 0; + (b[2] => z[19]) = 0; + (b[3] => z[19]) = 0; + (b[4] => z[19]) = 0; + (b[5] => z[19]) = 0; + (b[6] => z[19]) = 0; + (b[7] => z[19]) = 0; + (b[8] => z[19]) = 0; + (b[9] => z[19]) = 0; + (b[10] => z[19]) = 0; + (b[11] => z[19]) = 0; + (b[12] => z[19]) = 0; + (b[13] => z[19]) = 0; + (b[14] => z[19]) = 0; + (b[15] => z[19]) = 0; + (b[16] => z[19]) = 0; + (b[17] => z[19]) = 0; + (a[0] => z[20]) = 0; + (a[1] => z[20]) = 0; + (a[2] => z[20]) = 0; + (a[3] => z[20]) = 0; + (a[4] => z[20]) = 0; + (a[5] => z[20]) = 0; + (a[6] => z[20]) = 0; + (a[7] => z[20]) = 0; + (a[8] => z[20]) = 0; + (a[9] => z[20]) = 0; + (a[10] => z[20]) = 0; + (a[11] => z[20]) = 0; + (a[12] => z[20]) = 0; + (a[13] => z[20]) = 0; + (a[14] => z[20]) = 0; + (a[15] => z[20]) = 0; + (a[16] => z[20]) = 0; + (a[17] => z[20]) = 0; + (a[18] => z[20]) = 0; + (a[19] => z[20]) = 0; + (b[0] => z[20]) = 0; + (b[1] => z[20]) = 0; + (b[2] => z[20]) = 0; + (b[3] => z[20]) = 0; + (b[4] => z[20]) = 0; + (b[5] => z[20]) = 0; + (b[6] => z[20]) = 0; + (b[7] => z[20]) = 0; + (b[8] => z[20]) = 0; + (b[9] => z[20]) = 0; + (b[10] => z[20]) = 0; + (b[11] => z[20]) = 0; + (b[12] => z[20]) = 0; + (b[13] => z[20]) = 0; + (b[14] => z[20]) = 0; + (b[15] => z[20]) = 0; + (b[16] => z[20]) = 0; + (b[17] => z[20]) = 0; + (a[0] => z[21]) = 0; + (a[1] => z[21]) = 0; + (a[2] => z[21]) = 0; + (a[3] => z[21]) = 0; + (a[4] => z[21]) = 0; + (a[5] => z[21]) = 0; + (a[6] => z[21]) = 0; + (a[7] => z[21]) = 0; + (a[8] => z[21]) = 0; + (a[9] => z[21]) = 0; + (a[10] => z[21]) = 0; + (a[11] => z[21]) = 0; + (a[12] => z[21]) = 0; + (a[13] => z[21]) = 0; + (a[14] => z[21]) = 0; + (a[15] => z[21]) = 0; + (a[16] => z[21]) = 0; + (a[17] => z[21]) = 0; + (a[18] => z[21]) = 0; + (a[19] => z[21]) = 0; + (b[0] => z[21]) = 0; + (b[1] => z[21]) = 0; + (b[2] => z[21]) = 0; + (b[3] => z[21]) = 0; + (b[4] => z[21]) = 0; + (b[5] => z[21]) = 0; + (b[6] => z[21]) = 0; + (b[7] => z[21]) = 0; + (b[8] => z[21]) = 0; + (b[9] => z[21]) = 0; + (b[10] => z[21]) = 0; + (b[11] => z[21]) = 0; + (b[12] => z[21]) = 0; + (b[13] => z[21]) = 0; + (b[14] => z[21]) = 0; + (b[15] => z[21]) = 0; + (b[16] => z[21]) = 0; + (b[17] => z[21]) = 0; + (a[0] => z[22]) = 0; + (a[1] => z[22]) = 0; + (a[2] => z[22]) = 0; + (a[3] => z[22]) = 0; + (a[4] => z[22]) = 0; + (a[5] => z[22]) = 0; + (a[6] => z[22]) = 0; + (a[7] => z[22]) = 0; + (a[8] => z[22]) = 0; + (a[9] => z[22]) = 0; + (a[10] => z[22]) = 0; + (a[11] => z[22]) = 0; + (a[12] => z[22]) = 0; + (a[13] => z[22]) = 0; + (a[14] => z[22]) = 0; + (a[15] => z[22]) = 0; + (a[16] => z[22]) = 0; + (a[17] => z[22]) = 0; + (a[18] => z[22]) = 0; + (a[19] => z[22]) = 0; + (b[0] => z[22]) = 0; + (b[1] => z[22]) = 0; + (b[2] => z[22]) = 0; + (b[3] => z[22]) = 0; + (b[4] => z[22]) = 0; + (b[5] => z[22]) = 0; + (b[6] => z[22]) = 0; + (b[7] => z[22]) = 0; + (b[8] => z[22]) = 0; + (b[9] => z[22]) = 0; + (b[10] => z[22]) = 0; + (b[11] => z[22]) = 0; + (b[12] => z[22]) = 0; + (b[13] => z[22]) = 0; + (b[14] => z[22]) = 0; + (b[15] => z[22]) = 0; + (b[16] => z[22]) = 0; + (b[17] => z[22]) = 0; + (a[0] => z[23]) = 0; + (a[1] => z[23]) = 0; + (a[2] => z[23]) = 0; + (a[3] => z[23]) = 0; + (a[4] => z[23]) = 0; + (a[5] => z[23]) = 0; + (a[6] => z[23]) = 0; + (a[7] => z[23]) = 0; + (a[8] => z[23]) = 0; + (a[9] => z[23]) = 0; + (a[10] => z[23]) = 0; + (a[11] => z[23]) = 0; + (a[12] => z[23]) = 0; + (a[13] => z[23]) = 0; + (a[14] => z[23]) = 0; + (a[15] => z[23]) = 0; + (a[16] => z[23]) = 0; + (a[17] => z[23]) = 0; + (a[18] => z[23]) = 0; + (a[19] => z[23]) = 0; + (b[0] => z[23]) = 0; + (b[1] => z[23]) = 0; + (b[2] => z[23]) = 0; + (b[3] => z[23]) = 0; + (b[4] => z[23]) = 0; + (b[5] => z[23]) = 0; + (b[6] => z[23]) = 0; + (b[7] => z[23]) = 0; + (b[8] => z[23]) = 0; + (b[9] => z[23]) = 0; + (b[10] => z[23]) = 0; + (b[11] => z[23]) = 0; + (b[12] => z[23]) = 0; + (b[13] => z[23]) = 0; + (b[14] => z[23]) = 0; + (b[15] => z[23]) = 0; + (b[16] => z[23]) = 0; + (b[17] => z[23]) = 0; + (a[0] => z[24]) = 0; + (a[1] => z[24]) = 0; + (a[2] => z[24]) = 0; + (a[3] => z[24]) = 0; + (a[4] => z[24]) = 0; + (a[5] => z[24]) = 0; + (a[6] => z[24]) = 0; + (a[7] => z[24]) = 0; + (a[8] => z[24]) = 0; + (a[9] => z[24]) = 0; + (a[10] => z[24]) = 0; + (a[11] => z[24]) = 0; + (a[12] => z[24]) = 0; + (a[13] => z[24]) = 0; + (a[14] => z[24]) = 0; + (a[15] => z[24]) = 0; + (a[16] => z[24]) = 0; + (a[17] => z[24]) = 0; + (a[18] => z[24]) = 0; + (a[19] => z[24]) = 0; + (b[0] => z[24]) = 0; + (b[1] => z[24]) = 0; + (b[2] => z[24]) = 0; + (b[3] => z[24]) = 0; + (b[4] => z[24]) = 0; + (b[5] => z[24]) = 0; + (b[6] => z[24]) = 0; + (b[7] => z[24]) = 0; + (b[8] => z[24]) = 0; + (b[9] => z[24]) = 0; + (b[10] => z[24]) = 0; + (b[11] => z[24]) = 0; + (b[12] => z[24]) = 0; + (b[13] => z[24]) = 0; + (b[14] => z[24]) = 0; + (b[15] => z[24]) = 0; + (b[16] => z[24]) = 0; + (b[17] => z[24]) = 0; + (a[0] => z[25]) = 0; + (a[1] => z[25]) = 0; + (a[2] => z[25]) = 0; + (a[3] => z[25]) = 0; + (a[4] => z[25]) = 0; + (a[5] => z[25]) = 0; + (a[6] => z[25]) = 0; + (a[7] => z[25]) = 0; + (a[8] => z[25]) = 0; + (a[9] => z[25]) = 0; + (a[10] => z[25]) = 0; + (a[11] => z[25]) = 0; + (a[12] => z[25]) = 0; + (a[13] => z[25]) = 0; + (a[14] => z[25]) = 0; + (a[15] => z[25]) = 0; + (a[16] => z[25]) = 0; + (a[17] => z[25]) = 0; + (a[18] => z[25]) = 0; + (a[19] => z[25]) = 0; + (b[0] => z[25]) = 0; + (b[1] => z[25]) = 0; + (b[2] => z[25]) = 0; + (b[3] => z[25]) = 0; + (b[4] => z[25]) = 0; + (b[5] => z[25]) = 0; + (b[6] => z[25]) = 0; + (b[7] => z[25]) = 0; + (b[8] => z[25]) = 0; + (b[9] => z[25]) = 0; + (b[10] => z[25]) = 0; + (b[11] => z[25]) = 0; + (b[12] => z[25]) = 0; + (b[13] => z[25]) = 0; + (b[14] => z[25]) = 0; + (b[15] => z[25]) = 0; + (b[16] => z[25]) = 0; + (b[17] => z[25]) = 0; + (a[0] => z[26]) = 0; + (a[1] => z[26]) = 0; + (a[2] => z[26]) = 0; + (a[3] => z[26]) = 0; + (a[4] => z[26]) = 0; + (a[5] => z[26]) = 0; + (a[6] => z[26]) = 0; + (a[7] => z[26]) = 0; + (a[8] => z[26]) = 0; + (a[9] => z[26]) = 0; + (a[10] => z[26]) = 0; + (a[11] => z[26]) = 0; + (a[12] => z[26]) = 0; + (a[13] => z[26]) = 0; + (a[14] => z[26]) = 0; + (a[15] => z[26]) = 0; + (a[16] => z[26]) = 0; + (a[17] => z[26]) = 0; + (a[18] => z[26]) = 0; + (a[19] => z[26]) = 0; + (b[0] => z[26]) = 0; + (b[1] => z[26]) = 0; + (b[2] => z[26]) = 0; + (b[3] => z[26]) = 0; + (b[4] => z[26]) = 0; + (b[5] => z[26]) = 0; + (b[6] => z[26]) = 0; + (b[7] => z[26]) = 0; + (b[8] => z[26]) = 0; + (b[9] => z[26]) = 0; + (b[10] => z[26]) = 0; + (b[11] => z[26]) = 0; + (b[12] => z[26]) = 0; + (b[13] => z[26]) = 0; + (b[14] => z[26]) = 0; + (b[15] => z[26]) = 0; + (b[16] => z[26]) = 0; + (b[17] => z[26]) = 0; + (a[0] => z[27]) = 0; + (a[1] => z[27]) = 0; + (a[2] => z[27]) = 0; + (a[3] => z[27]) = 0; + (a[4] => z[27]) = 0; + (a[5] => z[27]) = 0; + (a[6] => z[27]) = 0; + (a[7] => z[27]) = 0; + (a[8] => z[27]) = 0; + (a[9] => z[27]) = 0; + (a[10] => z[27]) = 0; + (a[11] => z[27]) = 0; + (a[12] => z[27]) = 0; + (a[13] => z[27]) = 0; + (a[14] => z[27]) = 0; + (a[15] => z[27]) = 0; + (a[16] => z[27]) = 0; + (a[17] => z[27]) = 0; + (a[18] => z[27]) = 0; + (a[19] => z[27]) = 0; + (b[0] => z[27]) = 0; + (b[1] => z[27]) = 0; + (b[2] => z[27]) = 0; + (b[3] => z[27]) = 0; + (b[4] => z[27]) = 0; + (b[5] => z[27]) = 0; + (b[6] => z[27]) = 0; + (b[7] => z[27]) = 0; + (b[8] => z[27]) = 0; + (b[9] => z[27]) = 0; + (b[10] => z[27]) = 0; + (b[11] => z[27]) = 0; + (b[12] => z[27]) = 0; + (b[13] => z[27]) = 0; + (b[14] => z[27]) = 0; + (b[15] => z[27]) = 0; + (b[16] => z[27]) = 0; + (b[17] => z[27]) = 0; + (a[0] => z[28]) = 0; + (a[1] => z[28]) = 0; + (a[2] => z[28]) = 0; + (a[3] => z[28]) = 0; + (a[4] => z[28]) = 0; + (a[5] => z[28]) = 0; + (a[6] => z[28]) = 0; + (a[7] => z[28]) = 0; + (a[8] => z[28]) = 0; + (a[9] => z[28]) = 0; + (a[10] => z[28]) = 0; + (a[11] => z[28]) = 0; + (a[12] => z[28]) = 0; + (a[13] => z[28]) = 0; + (a[14] => z[28]) = 0; + (a[15] => z[28]) = 0; + (a[16] => z[28]) = 0; + (a[17] => z[28]) = 0; + (a[18] => z[28]) = 0; + (a[19] => z[28]) = 0; + (b[0] => z[28]) = 0; + (b[1] => z[28]) = 0; + (b[2] => z[28]) = 0; + (b[3] => z[28]) = 0; + (b[4] => z[28]) = 0; + (b[5] => z[28]) = 0; + (b[6] => z[28]) = 0; + (b[7] => z[28]) = 0; + (b[8] => z[28]) = 0; + (b[9] => z[28]) = 0; + (b[10] => z[28]) = 0; + (b[11] => z[28]) = 0; + (b[12] => z[28]) = 0; + (b[13] => z[28]) = 0; + (b[14] => z[28]) = 0; + (b[15] => z[28]) = 0; + (b[16] => z[28]) = 0; + (b[17] => z[28]) = 0; + (a[0] => z[29]) = 0; + (a[1] => z[29]) = 0; + (a[2] => z[29]) = 0; + (a[3] => z[29]) = 0; + (a[4] => z[29]) = 0; + (a[5] => z[29]) = 0; + (a[6] => z[29]) = 0; + (a[7] => z[29]) = 0; + (a[8] => z[29]) = 0; + (a[9] => z[29]) = 0; + (a[10] => z[29]) = 0; + (a[11] => z[29]) = 0; + (a[12] => z[29]) = 0; + (a[13] => z[29]) = 0; + (a[14] => z[29]) = 0; + (a[15] => z[29]) = 0; + (a[16] => z[29]) = 0; + (a[17] => z[29]) = 0; + (a[18] => z[29]) = 0; + (a[19] => z[29]) = 0; + (b[0] => z[29]) = 0; + (b[1] => z[29]) = 0; + (b[2] => z[29]) = 0; + (b[3] => z[29]) = 0; + (b[4] => z[29]) = 0; + (b[5] => z[29]) = 0; + (b[6] => z[29]) = 0; + (b[7] => z[29]) = 0; + (b[8] => z[29]) = 0; + (b[9] => z[29]) = 0; + (b[10] => z[29]) = 0; + (b[11] => z[29]) = 0; + (b[12] => z[29]) = 0; + (b[13] => z[29]) = 0; + (b[14] => z[29]) = 0; + (b[15] => z[29]) = 0; + (b[16] => z[29]) = 0; + (b[17] => z[29]) = 0; + (a[0] => z[30]) = 0; + (a[1] => z[30]) = 0; + (a[2] => z[30]) = 0; + (a[3] => z[30]) = 0; + (a[4] => z[30]) = 0; + (a[5] => z[30]) = 0; + (a[6] => z[30]) = 0; + (a[7] => z[30]) = 0; + (a[8] => z[30]) = 0; + (a[9] => z[30]) = 0; + (a[10] => z[30]) = 0; + (a[11] => z[30]) = 0; + (a[12] => z[30]) = 0; + (a[13] => z[30]) = 0; + (a[14] => z[30]) = 0; + (a[15] => z[30]) = 0; + (a[16] => z[30]) = 0; + (a[17] => z[30]) = 0; + (a[18] => z[30]) = 0; + (a[19] => z[30]) = 0; + (b[0] => z[30]) = 0; + (b[1] => z[30]) = 0; + (b[2] => z[30]) = 0; + (b[3] => z[30]) = 0; + (b[4] => z[30]) = 0; + (b[5] => z[30]) = 0; + (b[6] => z[30]) = 0; + (b[7] => z[30]) = 0; + (b[8] => z[30]) = 0; + (b[9] => z[30]) = 0; + (b[10] => z[30]) = 0; + (b[11] => z[30]) = 0; + (b[12] => z[30]) = 0; + (b[13] => z[30]) = 0; + (b[14] => z[30]) = 0; + (b[15] => z[30]) = 0; + (b[16] => z[30]) = 0; + (b[17] => z[30]) = 0; + (a[0] => z[31]) = 0; + (a[1] => z[31]) = 0; + (a[2] => z[31]) = 0; + (a[3] => z[31]) = 0; + (a[4] => z[31]) = 0; + (a[5] => z[31]) = 0; + (a[6] => z[31]) = 0; + (a[7] => z[31]) = 0; + (a[8] => z[31]) = 0; + (a[9] => z[31]) = 0; + (a[10] => z[31]) = 0; + (a[11] => z[31]) = 0; + (a[12] => z[31]) = 0; + (a[13] => z[31]) = 0; + (a[14] => z[31]) = 0; + (a[15] => z[31]) = 0; + (a[16] => z[31]) = 0; + (a[17] => z[31]) = 0; + (a[18] => z[31]) = 0; + (a[19] => z[31]) = 0; + (b[0] => z[31]) = 0; + (b[1] => z[31]) = 0; + (b[2] => z[31]) = 0; + (b[3] => z[31]) = 0; + (b[4] => z[31]) = 0; + (b[5] => z[31]) = 0; + (b[6] => z[31]) = 0; + (b[7] => z[31]) = 0; + (b[8] => z[31]) = 0; + (b[9] => z[31]) = 0; + (b[10] => z[31]) = 0; + (b[11] => z[31]) = 0; + (b[12] => z[31]) = 0; + (b[13] => z[31]) = 0; + (b[14] => z[31]) = 0; + (b[15] => z[31]) = 0; + (b[16] => z[31]) = 0; + (b[17] => z[31]) = 0; + (a[0] => z[32]) = 0; + (a[1] => z[32]) = 0; + (a[2] => z[32]) = 0; + (a[3] => z[32]) = 0; + (a[4] => z[32]) = 0; + (a[5] => z[32]) = 0; + (a[6] => z[32]) = 0; + (a[7] => z[32]) = 0; + (a[8] => z[32]) = 0; + (a[9] => z[32]) = 0; + (a[10] => z[32]) = 0; + (a[11] => z[32]) = 0; + (a[12] => z[32]) = 0; + (a[13] => z[32]) = 0; + (a[14] => z[32]) = 0; + (a[15] => z[32]) = 0; + (a[16] => z[32]) = 0; + (a[17] => z[32]) = 0; + (a[18] => z[32]) = 0; + (a[19] => z[32]) = 0; + (b[0] => z[32]) = 0; + (b[1] => z[32]) = 0; + (b[2] => z[32]) = 0; + (b[3] => z[32]) = 0; + (b[4] => z[32]) = 0; + (b[5] => z[32]) = 0; + (b[6] => z[32]) = 0; + (b[7] => z[32]) = 0; + (b[8] => z[32]) = 0; + (b[9] => z[32]) = 0; + (b[10] => z[32]) = 0; + (b[11] => z[32]) = 0; + (b[12] => z[32]) = 0; + (b[13] => z[32]) = 0; + (b[14] => z[32]) = 0; + (b[15] => z[32]) = 0; + (b[16] => z[32]) = 0; + (b[17] => z[32]) = 0; + (a[0] => z[33]) = 0; + (a[1] => z[33]) = 0; + (a[2] => z[33]) = 0; + (a[3] => z[33]) = 0; + (a[4] => z[33]) = 0; + (a[5] => z[33]) = 0; + (a[6] => z[33]) = 0; + (a[7] => z[33]) = 0; + (a[8] => z[33]) = 0; + (a[9] => z[33]) = 0; + (a[10] => z[33]) = 0; + (a[11] => z[33]) = 0; + (a[12] => z[33]) = 0; + (a[13] => z[33]) = 0; + (a[14] => z[33]) = 0; + (a[15] => z[33]) = 0; + (a[16] => z[33]) = 0; + (a[17] => z[33]) = 0; + (a[18] => z[33]) = 0; + (a[19] => z[33]) = 0; + (b[0] => z[33]) = 0; + (b[1] => z[33]) = 0; + (b[2] => z[33]) = 0; + (b[3] => z[33]) = 0; + (b[4] => z[33]) = 0; + (b[5] => z[33]) = 0; + (b[6] => z[33]) = 0; + (b[7] => z[33]) = 0; + (b[8] => z[33]) = 0; + (b[9] => z[33]) = 0; + (b[10] => z[33]) = 0; + (b[11] => z[33]) = 0; + (b[12] => z[33]) = 0; + (b[13] => z[33]) = 0; + (b[14] => z[33]) = 0; + (b[15] => z[33]) = 0; + (b[16] => z[33]) = 0; + (b[17] => z[33]) = 0; + (a[0] => z[34]) = 0; + (a[1] => z[34]) = 0; + (a[2] => z[34]) = 0; + (a[3] => z[34]) = 0; + (a[4] => z[34]) = 0; + (a[5] => z[34]) = 0; + (a[6] => z[34]) = 0; + (a[7] => z[34]) = 0; + (a[8] => z[34]) = 0; + (a[9] => z[34]) = 0; + (a[10] => z[34]) = 0; + (a[11] => z[34]) = 0; + (a[12] => z[34]) = 0; + (a[13] => z[34]) = 0; + (a[14] => z[34]) = 0; + (a[15] => z[34]) = 0; + (a[16] => z[34]) = 0; + (a[17] => z[34]) = 0; + (a[18] => z[34]) = 0; + (a[19] => z[34]) = 0; + (b[0] => z[34]) = 0; + (b[1] => z[34]) = 0; + (b[2] => z[34]) = 0; + (b[3] => z[34]) = 0; + (b[4] => z[34]) = 0; + (b[5] => z[34]) = 0; + (b[6] => z[34]) = 0; + (b[7] => z[34]) = 0; + (b[8] => z[34]) = 0; + (b[9] => z[34]) = 0; + (b[10] => z[34]) = 0; + (b[11] => z[34]) = 0; + (b[12] => z[34]) = 0; + (b[13] => z[34]) = 0; + (b[14] => z[34]) = 0; + (b[15] => z[34]) = 0; + (b[16] => z[34]) = 0; + (b[17] => z[34]) = 0; + (a[0] => z[35]) = 0; + (a[1] => z[35]) = 0; + (a[2] => z[35]) = 0; + (a[3] => z[35]) = 0; + (a[4] => z[35]) = 0; + (a[5] => z[35]) = 0; + (a[6] => z[35]) = 0; + (a[7] => z[35]) = 0; + (a[8] => z[35]) = 0; + (a[9] => z[35]) = 0; + (a[10] => z[35]) = 0; + (a[11] => z[35]) = 0; + (a[12] => z[35]) = 0; + (a[13] => z[35]) = 0; + (a[14] => z[35]) = 0; + (a[15] => z[35]) = 0; + (a[16] => z[35]) = 0; + (a[17] => z[35]) = 0; + (a[18] => z[35]) = 0; + (a[19] => z[35]) = 0; + (b[0] => z[35]) = 0; + (b[1] => z[35]) = 0; + (b[2] => z[35]) = 0; + (b[3] => z[35]) = 0; + (b[4] => z[35]) = 0; + (b[5] => z[35]) = 0; + (b[6] => z[35]) = 0; + (b[7] => z[35]) = 0; + (b[8] => z[35]) = 0; + (b[9] => z[35]) = 0; + (b[10] => z[35]) = 0; + (b[11] => z[35]) = 0; + (b[12] => z[35]) = 0; + (b[13] => z[35]) = 0; + (b[14] => z[35]) = 0; + (b[15] => z[35]) = 0; + (b[16] => z[35]) = 0; + (b[17] => z[35]) = 0; + (a[0] => z[36]) = 0; + (a[1] => z[36]) = 0; + (a[2] => z[36]) = 0; + (a[3] => z[36]) = 0; + (a[4] => z[36]) = 0; + (a[5] => z[36]) = 0; + (a[6] => z[36]) = 0; + (a[7] => z[36]) = 0; + (a[8] => z[36]) = 0; + (a[9] => z[36]) = 0; + (a[10] => z[36]) = 0; + (a[11] => z[36]) = 0; + (a[12] => z[36]) = 0; + (a[13] => z[36]) = 0; + (a[14] => z[36]) = 0; + (a[15] => z[36]) = 0; + (a[16] => z[36]) = 0; + (a[17] => z[36]) = 0; + (a[18] => z[36]) = 0; + (a[19] => z[36]) = 0; + (b[0] => z[36]) = 0; + (b[1] => z[36]) = 0; + (b[2] => z[36]) = 0; + (b[3] => z[36]) = 0; + (b[4] => z[36]) = 0; + (b[5] => z[36]) = 0; + (b[6] => z[36]) = 0; + (b[7] => z[36]) = 0; + (b[8] => z[36]) = 0; + (b[9] => z[36]) = 0; + (b[10] => z[36]) = 0; + (b[11] => z[36]) = 0; + (b[12] => z[36]) = 0; + (b[13] => z[36]) = 0; + (b[14] => z[36]) = 0; + (b[15] => z[36]) = 0; + (b[16] => z[36]) = 0; + (b[17] => z[36]) = 0; + (a[0] => z[37]) = 0; + (a[1] => z[37]) = 0; + (a[2] => z[37]) = 0; + (a[3] => z[37]) = 0; + (a[4] => z[37]) = 0; + (a[5] => z[37]) = 0; + (a[6] => z[37]) = 0; + (a[7] => z[37]) = 0; + (a[8] => z[37]) = 0; + (a[9] => z[37]) = 0; + (a[10] => z[37]) = 0; + (a[11] => z[37]) = 0; + (a[12] => z[37]) = 0; + (a[13] => z[37]) = 0; + (a[14] => z[37]) = 0; + (a[15] => z[37]) = 0; + (a[16] => z[37]) = 0; + (a[17] => z[37]) = 0; + (a[18] => z[37]) = 0; + (a[19] => z[37]) = 0; + (b[0] => z[37]) = 0; + (b[1] => z[37]) = 0; + (b[2] => z[37]) = 0; + (b[3] => z[37]) = 0; + (b[4] => z[37]) = 0; + (b[5] => z[37]) = 0; + (b[6] => z[37]) = 0; + (b[7] => z[37]) = 0; + (b[8] => z[37]) = 0; + (b[9] => z[37]) = 0; + (b[10] => z[37]) = 0; + (b[11] => z[37]) = 0; + (b[12] => z[37]) = 0; + (b[13] => z[37]) = 0; + (b[14] => z[37]) = 0; + (b[15] => z[37]) = 0; + (b[16] => z[37]) = 0; + (b[17] => z[37]) = 0; + (subtract => z[0]) = 0; + (subtract => z[1]) = 0; + (subtract => z[2]) = 0; + (subtract => z[3]) = 0; + (subtract => z[4]) = 0; + (subtract => z[5]) = 0; + (subtract => z[6]) = 0; + (subtract => z[7]) = 0; + (subtract => z[8]) = 0; + (subtract => z[9]) = 0; + (subtract => z[10]) = 0; + (subtract => z[11]) = 0; + (subtract => z[12]) = 0; + (subtract => z[13]) = 0; + (subtract => z[14]) = 0; + (subtract => z[15]) = 0; + (subtract => z[16]) = 0; + (subtract => z[17]) = 0; + (subtract => z[18]) = 0; + (subtract => z[19]) = 0; + (subtract => z[20]) = 0; + (subtract => z[21]) = 0; + (subtract => z[22]) = 0; + (subtract => z[23]) = 0; + (subtract => z[24]) = 0; + (subtract => z[25]) = 0; + (subtract => z[26]) = 0; + (subtract => z[27]) = 0; + (subtract => z[28]) = 0; + (subtract => z[29]) = 0; + (subtract => z[30]) = 0; + (subtract => z[31]) = 0; + (subtract => z[32]) = 0; + (subtract => z[33]) = 0; + (subtract => z[34]) = 0; + (subtract => z[35]) = 0; + (subtract => z[36]) = 0; + (subtract => z[37]) = 0; + (acc_fir[0] => z[0]) = 0; + (acc_fir[1] => z[0]) = 0; + (acc_fir[2] => z[0]) = 0; + (acc_fir[3] => z[0]) = 0; + (acc_fir[4] => z[0]) = 0; + (acc_fir[5] => z[0]) = 0; + (acc_fir[0] => z[1]) = 0; + (acc_fir[1] => z[1]) = 0; + (acc_fir[2] => z[1]) = 0; + (acc_fir[3] => z[1]) = 0; + (acc_fir[4] => z[1]) = 0; + (acc_fir[5] => z[1]) = 0; + (acc_fir[0] => z[2]) = 0; + (acc_fir[1] => z[2]) = 0; + (acc_fir[2] => z[2]) = 0; + (acc_fir[3] => z[2]) = 0; + (acc_fir[4] => z[2]) = 0; + (acc_fir[5] => z[2]) = 0; + (acc_fir[0] => z[3]) = 0; + (acc_fir[1] => z[3]) = 0; + (acc_fir[2] => z[3]) = 0; + (acc_fir[3] => z[3]) = 0; + (acc_fir[4] => z[3]) = 0; + (acc_fir[5] => z[3]) = 0; + (acc_fir[0] => z[4]) = 0; + (acc_fir[1] => z[4]) = 0; + (acc_fir[2] => z[4]) = 0; + (acc_fir[3] => z[4]) = 0; + (acc_fir[4] => z[4]) = 0; + (acc_fir[5] => z[4]) = 0; + (acc_fir[0] => z[5]) = 0; + (acc_fir[1] => z[5]) = 0; + (acc_fir[2] => z[5]) = 0; + (acc_fir[3] => z[5]) = 0; + (acc_fir[4] => z[5]) = 0; + (acc_fir[5] => z[5]) = 0; + (acc_fir[0] => z[6]) = 0; + (acc_fir[1] => z[6]) = 0; + (acc_fir[2] => z[6]) = 0; + (acc_fir[3] => z[6]) = 0; + (acc_fir[4] => z[6]) = 0; + (acc_fir[5] => z[6]) = 0; + (acc_fir[0] => z[7]) = 0; + (acc_fir[1] => z[7]) = 0; + (acc_fir[2] => z[7]) = 0; + (acc_fir[3] => z[7]) = 0; + (acc_fir[4] => z[7]) = 0; + (acc_fir[5] => z[7]) = 0; + (acc_fir[0] => z[8]) = 0; + (acc_fir[1] => z[8]) = 0; + (acc_fir[2] => z[8]) = 0; + (acc_fir[3] => z[8]) = 0; + (acc_fir[4] => z[8]) = 0; + (acc_fir[5] => z[8]) = 0; + (acc_fir[0] => z[9]) = 0; + (acc_fir[1] => z[9]) = 0; + (acc_fir[2] => z[9]) = 0; + (acc_fir[3] => z[9]) = 0; + (acc_fir[4] => z[9]) = 0; + (acc_fir[5] => z[9]) = 0; + (acc_fir[0] => z[10]) = 0; + (acc_fir[1] => z[10]) = 0; + (acc_fir[2] => z[10]) = 0; + (acc_fir[3] => z[10]) = 0; + (acc_fir[4] => z[10]) = 0; + (acc_fir[5] => z[10]) = 0; + (acc_fir[0] => z[11]) = 0; + (acc_fir[1] => z[11]) = 0; + (acc_fir[2] => z[11]) = 0; + (acc_fir[3] => z[11]) = 0; + (acc_fir[4] => z[11]) = 0; + (acc_fir[5] => z[11]) = 0; + (acc_fir[0] => z[12]) = 0; + (acc_fir[1] => z[12]) = 0; + (acc_fir[2] => z[12]) = 0; + (acc_fir[3] => z[12]) = 0; + (acc_fir[4] => z[12]) = 0; + (acc_fir[5] => z[12]) = 0; + (acc_fir[0] => z[13]) = 0; + (acc_fir[1] => z[13]) = 0; + (acc_fir[2] => z[13]) = 0; + (acc_fir[3] => z[13]) = 0; + (acc_fir[4] => z[13]) = 0; + (acc_fir[5] => z[13]) = 0; + (acc_fir[0] => z[14]) = 0; + (acc_fir[1] => z[14]) = 0; + (acc_fir[2] => z[14]) = 0; + (acc_fir[3] => z[14]) = 0; + (acc_fir[4] => z[14]) = 0; + (acc_fir[5] => z[14]) = 0; + (acc_fir[0] => z[15]) = 0; + (acc_fir[1] => z[15]) = 0; + (acc_fir[2] => z[15]) = 0; + (acc_fir[3] => z[15]) = 0; + (acc_fir[4] => z[15]) = 0; + (acc_fir[5] => z[15]) = 0; + (acc_fir[0] => z[16]) = 0; + (acc_fir[1] => z[16]) = 0; + (acc_fir[2] => z[16]) = 0; + (acc_fir[3] => z[16]) = 0; + (acc_fir[4] => z[16]) = 0; + (acc_fir[5] => z[16]) = 0; + (acc_fir[0] => z[17]) = 0; + (acc_fir[1] => z[17]) = 0; + (acc_fir[2] => z[17]) = 0; + (acc_fir[3] => z[17]) = 0; + (acc_fir[4] => z[17]) = 0; + (acc_fir[5] => z[17]) = 0; + (acc_fir[0] => z[18]) = 0; + (acc_fir[1] => z[18]) = 0; + (acc_fir[2] => z[18]) = 0; + (acc_fir[3] => z[18]) = 0; + (acc_fir[4] => z[18]) = 0; + (acc_fir[5] => z[18]) = 0; + (acc_fir[0] => z[19]) = 0; + (acc_fir[1] => z[19]) = 0; + (acc_fir[2] => z[19]) = 0; + (acc_fir[3] => z[19]) = 0; + (acc_fir[4] => z[19]) = 0; + (acc_fir[5] => z[19]) = 0; + (acc_fir[0] => z[20]) = 0; + (acc_fir[1] => z[20]) = 0; + (acc_fir[2] => z[20]) = 0; + (acc_fir[3] => z[20]) = 0; + (acc_fir[4] => z[20]) = 0; + (acc_fir[5] => z[20]) = 0; + (acc_fir[0] => z[21]) = 0; + (acc_fir[1] => z[21]) = 0; + (acc_fir[2] => z[21]) = 0; + (acc_fir[3] => z[21]) = 0; + (acc_fir[4] => z[21]) = 0; + (acc_fir[5] => z[21]) = 0; + (acc_fir[0] => z[22]) = 0; + (acc_fir[1] => z[22]) = 0; + (acc_fir[2] => z[22]) = 0; + (acc_fir[3] => z[22]) = 0; + (acc_fir[4] => z[22]) = 0; + (acc_fir[5] => z[22]) = 0; + (acc_fir[0] => z[23]) = 0; + (acc_fir[1] => z[23]) = 0; + (acc_fir[2] => z[23]) = 0; + (acc_fir[3] => z[23]) = 0; + (acc_fir[4] => z[23]) = 0; + (acc_fir[5] => z[23]) = 0; + (acc_fir[0] => z[24]) = 0; + (acc_fir[1] => z[24]) = 0; + (acc_fir[2] => z[24]) = 0; + (acc_fir[3] => z[24]) = 0; + (acc_fir[4] => z[24]) = 0; + (acc_fir[5] => z[24]) = 0; + (acc_fir[0] => z[25]) = 0; + (acc_fir[1] => z[25]) = 0; + (acc_fir[2] => z[25]) = 0; + (acc_fir[3] => z[25]) = 0; + (acc_fir[4] => z[25]) = 0; + (acc_fir[5] => z[25]) = 0; + (acc_fir[0] => z[26]) = 0; + (acc_fir[1] => z[26]) = 0; + (acc_fir[2] => z[26]) = 0; + (acc_fir[3] => z[26]) = 0; + (acc_fir[4] => z[26]) = 0; + (acc_fir[5] => z[26]) = 0; + (acc_fir[0] => z[27]) = 0; + (acc_fir[1] => z[27]) = 0; + (acc_fir[2] => z[27]) = 0; + (acc_fir[3] => z[27]) = 0; + (acc_fir[4] => z[27]) = 0; + (acc_fir[5] => z[27]) = 0; + (acc_fir[0] => z[28]) = 0; + (acc_fir[1] => z[28]) = 0; + (acc_fir[2] => z[28]) = 0; + (acc_fir[3] => z[28]) = 0; + (acc_fir[4] => z[28]) = 0; + (acc_fir[5] => z[28]) = 0; + (acc_fir[0] => z[29]) = 0; + (acc_fir[1] => z[29]) = 0; + (acc_fir[2] => z[29]) = 0; + (acc_fir[3] => z[29]) = 0; + (acc_fir[4] => z[29]) = 0; + (acc_fir[5] => z[29]) = 0; + (acc_fir[0] => z[30]) = 0; + (acc_fir[1] => z[30]) = 0; + (acc_fir[2] => z[30]) = 0; + (acc_fir[3] => z[30]) = 0; + (acc_fir[4] => z[30]) = 0; + (acc_fir[5] => z[30]) = 0; + (acc_fir[0] => z[31]) = 0; + (acc_fir[1] => z[31]) = 0; + (acc_fir[2] => z[31]) = 0; + (acc_fir[3] => z[31]) = 0; + (acc_fir[4] => z[31]) = 0; + (acc_fir[5] => z[31]) = 0; + (acc_fir[0] => z[32]) = 0; + (acc_fir[1] => z[32]) = 0; + (acc_fir[2] => z[32]) = 0; + (acc_fir[3] => z[32]) = 0; + (acc_fir[4] => z[32]) = 0; + (acc_fir[5] => z[32]) = 0; + (acc_fir[0] => z[33]) = 0; + (acc_fir[1] => z[33]) = 0; + (acc_fir[2] => z[33]) = 0; + (acc_fir[3] => z[33]) = 0; + (acc_fir[4] => z[33]) = 0; + (acc_fir[5] => z[33]) = 0; + (acc_fir[0] => z[34]) = 0; + (acc_fir[1] => z[34]) = 0; + (acc_fir[2] => z[34]) = 0; + (acc_fir[3] => z[34]) = 0; + (acc_fir[4] => z[34]) = 0; + (acc_fir[5] => z[34]) = 0; + (acc_fir[0] => z[35]) = 0; + (acc_fir[1] => z[35]) = 0; + (acc_fir[2] => z[35]) = 0; + (acc_fir[3] => z[35]) = 0; + (acc_fir[4] => z[35]) = 0; + (acc_fir[5] => z[35]) = 0; + (acc_fir[0] => z[36]) = 0; + (acc_fir[1] => z[36]) = 0; + (acc_fir[2] => z[36]) = 0; + (acc_fir[3] => z[36]) = 0; + (acc_fir[4] => z[36]) = 0; + (acc_fir[5] => z[36]) = 0; + (acc_fir[0] => z[37]) = 0; + (acc_fir[1] => z[37]) = 0; + (acc_fir[2] => z[37]) = 0; + (acc_fir[3] => z[37]) = 0; + (acc_fir[4] => z[37]) = 0; + (acc_fir[5] => z[37]) = 0; + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCin (2, 3) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .dly_b(), + .z(z), + + .f_mode(f_mode), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCin (6, 7) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + $setuphold(posedge clk, acc_fir, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire load_acc, + input wire [ 2:0] feedback, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // unregistered output: ACCout (1) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // unregistered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module QL_DSP2_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + + input wire f_mode, + input wire [ 2:0] output_select, + input wire saturate_enable, + input wire [ 5:0] shift_right, + input wire round, + input wire subtract, + input wire register_inputs +); + + parameter [79:0] MODE_BITS = 80'd0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a), + .b(b), + .acc_fir(6'b0), + .z(z), + .dly_b(), + + .f_mode(f_mode), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + + .output_select(output_select), // registered output: ACCout (5) + .saturate_enable(saturate_enable), + .shift_right(shift_right), + .round(round), + .subtract(subtract), + .register_inputs(register_inputs) // registered inputs + ); + +`ifdef SDF_SIM + specify + (posedge clk => (z +: a)) = 0; + (posedge clk => (z +: b)) = 0; + $setuphold(posedge clk, a, 0, 0); + $setuphold(posedge clk, b, 0, 0); + $setuphold(posedge clk, feedback, 0, 0); + $setuphold(posedge clk, load_acc, 0, 0); + $setuphold(posedge clk, subtract, 0, 0); + endspecify +`endif + +endmodule + +module dsp_t1_20x18x64_cfg_ports ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [19:0] COEFF_0 = 20'd0; + parameter [19:0] COEFF_1 = 20'd0; + parameter [19:0] COEFF_2 = 20'd0; + parameter [19:0] COEFF_3 = 20'd0; + + QL_DSP2 #( + .MODE_BITS({COEFF_3, COEFF_2, COEFF_1, COEFF_0}) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .f_mode(1'b0), // 20x18x64 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_ports ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire [ 2:0] output_select_i, + input wire saturate_enable_i, + input wire [ 5:0] shift_right_i, + input wire round_i, + input wire subtract_i, + input wire register_inputs_i +); + + parameter [9:0] COEFF_0 = 10'd0; + parameter [9:0] COEFF_1 = 10'd0; + parameter [9:0] COEFF_2 = 10'd0; + parameter [9:0] COEFF_3 = 10'd0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP2 #( + .MODE_BITS({10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0}) + ) dsp ( + .a({10'd0, a_i}), + .b({9'd0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .f_mode(1'b1), // 10x9x32 DSP + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + + .saturate_enable(saturate_enable_i), + .output_select(output_select_i), + .round(round_i), + .shift_right(shift_right_i), + .subtract(subtract_i), + .register_inputs(register_inputs_i) + ); +endmodule + +module dsp_t1_sim_cfg_ports # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire saturate_enable_i, + input wire [2:0] output_select_i, + input wire round_i, + input wire [5:0] shift_right_i, + input wire subtract_i, + input wire register_inputs_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= shift_right_i; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = register_inputs_i ? r_a : a_i; + wire [NBITS_B-1:0] b = register_inputs_i ? r_b : b_i; + + wire [5:0] acc_fir = register_inputs_i ? r_acc_fir : acc_fir_i; + wire unsigned_a = register_inputs_i ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = register_inputs_i ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = register_inputs_i ? r_feedback : feedback_i; + wire load_acc = register_inputs_i ? r_load_acc : load_acc_i; + wire subtract = register_inputs_i ? r_subtract : subtract_i; + wire sat = register_inputs_i ? r_sat : saturate_enable_i; + wire rnd = register_inputs_i ? r_rnd : round_i; + + // Shift right control + wire [5:0] shift_d1 = register_inputs_i ? r_shift_d1 : shift_right_i; + wire [5:0] shift_d2 = output_select_i[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (output_select_i[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (shift_right_i != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (shift_right_i - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> shift_right_i) : + (acc_rnd >>> shift_right_i); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (output_select_i == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (output_select_i == 3'h0) ? z0 : + (output_select_i == 3'h1) ? z2 : + (output_select_i == 3'h2) ? z2 : + (output_select_i == 3'h3) ? z2 : + (output_select_i == 3'h4) ? z1 : + (output_select_i == 3'h5) ? z1 : + (output_select_i == 3'h6) ? z1 : + z1; // if output_select_i == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule + + + +// ---------------------------------------- // +// ----- DSP cells simulation modules ----- // +// ------ Control bits in parameters ------ // +// ---------------------------------------- // + +module QL_DSP3 ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + input wire [ 5:0] acc_fir, + output wire [37:0] z, + output wire [17:0] dly_b, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + localparam NBITS_ACC = 64; + localparam NBITS_A = 20; + localparam NBITS_B = 18; + localparam NBITS_Z = 38; + + // Fractured + generate if(F_MODE == 1'b1) begin + + wire [(NBITS_Z/2)-1:0] dsp_frac0_z; + wire [(NBITS_Z/2)-1:0] dsp_frac1_z; + + wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; + wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A/2), + .NBITS_B (NBITS_B/2), + .NBITS_ACC (NBITS_ACC/2), + .NBITS_Z (NBITS_Z/2), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_frac0 ( + .a_i(a[(NBITS_A/2)-1:0]), + .b_i(b[(NBITS_B/2)-1:0]), + .z_o(dsp_frac0_z), + .dly_b_o(dsp_frac0_dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), + .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), + .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), + .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) + ); + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A/2), + .NBITS_B (NBITS_B/2), + .NBITS_ACC (NBITS_ACC/2), + .NBITS_Z (NBITS_Z/2), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_frac1 ( + .a_i(a[NBITS_A-1:NBITS_A/2]), + .b_i(b[NBITS_B-1:NBITS_B/2]), + .z_o(dsp_frac1_z), + .dly_b_o(dsp_frac1_dly_b), + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), + .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), + .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), + .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) + ); + + assign z = {dsp_frac1_z, dsp_frac0_z}; + assign dly_b = {dsp_frac1_dly_b, dsp_frac0_dly_b}; + + // Whole + end else begin + + dsp_t1_sim_cfg_params #( + .NBITS_A (NBITS_A), + .NBITS_B (NBITS_B), + .NBITS_ACC (NBITS_ACC), + .NBITS_Z (NBITS_Z), + .OUTPUT_SELECT (OUTPUT_SELECT), + .SATURATE_ENABLE (SATURATE_ENABLE), + .SHIFT_RIGHT (SHIFT_RIGHT), + .ROUND (ROUND), + .REGISTER_INPUTS (REGISTER_INPUTS) + ) dsp_full ( + .a_i(a), + .b_i(b), + .z_o(z), + .dly_b_o(dly_b), + + .acc_fir_i(acc_fir), + .feedback_i(feedback), + .load_acc_i(load_acc), + + .unsigned_a_i(unsigned_a), + .unsigned_b_i(unsigned_b), + + .clock_i(clk), + .s_reset(reset), + + .subtract_i(subtract), + .coef_0_i(COEFF_0), + .coef_1_i(COEFF_1), + .coef_2_i(COEFF_2), + .coef_3_i(COEFF_3) + ); + + end endgenerate + +endmodule + +module QL_DSP3_MULT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [2:0] feedback, + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .reset(reset), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b) + ); +endmodule + +module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + wire [37:0] dly_b_o; + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // registered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [2:0] feedback, + + input wire unsigned_a, + input wire unsigned_b +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset) + ); +endmodule + +module QL_DSP3_MULTADD ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTADD_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire [ 5:0] acc_fir, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .acc_fir(acc_fir), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGIN ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module QL_DSP3_MULTACC_REGIN_REGOUT ( + input wire [19:0] a, + input wire [17:0] b, + output wire [37:0] z, + + (* clkbuf_sink *) + input wire clk, + input wire reset, + + input wire [ 2:0] feedback, + input wire load_acc, + input wire unsigned_a, + input wire unsigned_b, + input wire subtract +); + + parameter [92:0] MODE_BITS = 93'b0; + + localparam [19:0] COEFF_0 = MODE_BITS[19:0]; + localparam [19:0] COEFF_1 = MODE_BITS[39:20]; + localparam [19:0] COEFF_2 = MODE_BITS[59:40]; + localparam [19:0] COEFF_3 = MODE_BITS[79:60]; + + localparam [0:0] F_MODE = MODE_BITS[80]; + localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; + localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; + localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; + localparam [0:0] ROUND = MODE_BITS[91]; + localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; + + QL_DSP3 #( + .MODE_BITS({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + F_MODE, + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a), + .b(b), + .z(z), + + .feedback(feedback), + .load_acc(load_acc), + + .unsigned_a(unsigned_a), + .unsigned_b(unsigned_b), + + .clk(clk), + .reset(reset), + .subtract(subtract) + ); +endmodule + +module dsp_t1_20x18x64_cfg_params ( + input wire [19:0] a_i, + input wire [17:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [37:0] z_o, + output wire [17:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + input wire subtract_i +); + + parameter [19:0] COEFF_0 = 20'b0; + parameter [19:0] COEFF_1 = 20'b0; + parameter [19:0] COEFF_2 = 20'b0; + parameter [19:0] COEFF_3 = 20'b0; + + parameter [2:0] OUTPUT_SELECT = 3'b0; + parameter [0:0] SATURATE_ENABLE = 1'b0; + parameter [5:0] SHIFT_RIGHT = 6'b0; + parameter [0:0] ROUND = 1'b0; + parameter [0:0] REGISTER_INPUTS = 1'b0; + + QL_DSP3 #( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b0, // Not fractured + COEFF_3, + COEFF_2, + COEFF_1, + COEFF_0 + }) + ) dsp ( + .a(a_i), + .b(b_i), + .z(z_o), + .dly_b(dly_b_o), + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + .subtract(subtract_i) + ); +endmodule + +module dsp_t1_10x9x32_cfg_params ( + input wire [ 9:0] a_i, + input wire [ 8:0] b_i, + input wire [ 5:0] acc_fir_i, + output wire [18:0] z_o, + output wire [ 8:0] dly_b_o, + + (* clkbuf_sink *) + input wire clock_i, + input wire reset_i, + + input wire [ 2:0] feedback_i, + input wire load_acc_i, + input wire unsigned_a_i, + input wire unsigned_b_i, + input wire subtract_i +); + + parameter [9:0] COEFF_0 = 10'b0; + parameter [9:0] COEFF_1 = 10'b0; + parameter [9:0] COEFF_2 = 10'b0; + parameter [9:0] COEFF_3 = 10'b0; + + parameter [2:0] OUTPUT_SELECT = 3'b0; + parameter [0:0] SATURATE_ENABLE = 1'b0; + parameter [5:0] SHIFT_RIGHT = 6'b0; + parameter [0:0] ROUND = 1'b0; + parameter [0:0] REGISTER_INPUTS = 1'b0; + + wire [18:0] z_rem; + wire [8:0] dly_b_rem; + + QL_DSP3 #( + .MODE_BITS ({ + REGISTER_INPUTS, + ROUND, + SHIFT_RIGHT, + SATURATE_ENABLE, + OUTPUT_SELECT, + 1'b1, // Fractured + 10'd0, COEFF_3, + 10'd0, COEFF_2, + 10'd0, COEFF_1, + 10'd0, COEFF_0 + }) + ) dsp ( + .a({10'b0, a_i}), + .b({9'b0, b_i}), + .z({z_rem, z_o}), + .dly_b({dly_b_rem, dly_b_o}), + + .acc_fir(acc_fir_i), + .feedback(feedback_i), + .load_acc(load_acc_i), + + .unsigned_a(unsigned_a_i), + .unsigned_b(unsigned_b_i), + + .clk(clock_i), + .reset(reset_i), + .subtract(subtract_i) + ); +endmodule + +module dsp_t1_sim_cfg_params # ( + parameter NBITS_ACC = 64, + parameter NBITS_A = 20, + parameter NBITS_B = 18, + parameter NBITS_Z = 38, + + parameter [2:0] OUTPUT_SELECT = 3'b0, + parameter [0:0] SATURATE_ENABLE = 1'b0, + parameter [5:0] SHIFT_RIGHT = 6'b0, + parameter [0:0] ROUND = 1'b0, + parameter [0:0] REGISTER_INPUTS = 1'b0 +)( + input wire [NBITS_A-1:0] a_i, + input wire [NBITS_B-1:0] b_i, + output wire [NBITS_Z-1:0] z_o, + output reg [NBITS_B-1:0] dly_b_o, + + input wire [5:0] acc_fir_i, + input wire [2:0] feedback_i, + input wire load_acc_i, + + input wire unsigned_a_i, + input wire unsigned_b_i, + + input wire clock_i, + input wire s_reset, + + input wire subtract_i, + input wire [NBITS_A-1:0] coef_0_i, + input wire [NBITS_A-1:0] coef_1_i, + input wire [NBITS_A-1:0] coef_2_i, + input wire [NBITS_A-1:0] coef_3_i +); + +// FIXME: The version of Icarus Verilog from Conda seems not to recognize the +// $error macro. Disable this sanity check for now because of that. + + // Input registers + reg [NBITS_A-1:0] r_a; + reg [NBITS_B-1:0] r_b; + reg [5:0] r_acc_fir; + reg r_unsigned_a; + reg r_unsigned_b; + reg r_load_acc; + reg [2:0] r_feedback; + reg [5:0] r_shift_d1; + reg [5:0] r_shift_d2; + reg r_subtract; + reg r_sat; + reg r_rnd; + reg [NBITS_ACC-1:0] acc; + + initial begin + r_a <= 0; + r_b <= 0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + end + + always @(posedge clock_i or posedge s_reset) begin + if (s_reset) begin + + r_a <= 'h0; + r_b <= 'h0; + + r_acc_fir <= 0; + r_unsigned_a <= 0; + r_unsigned_b <= 0; + r_feedback <= 0; + r_shift_d1 <= 0; + r_shift_d2 <= 0; + r_subtract <= 0; + r_load_acc <= 0; + r_sat <= 0; + r_rnd <= 0; + + end else begin + + r_a <= a_i; + r_b <= b_i; + + r_acc_fir <= acc_fir_i; + r_unsigned_a <= unsigned_a_i; + r_unsigned_b <= unsigned_b_i; + r_feedback <= feedback_i; + r_shift_d1 <= SHIFT_RIGHT; + r_shift_d2 <= r_shift_d1; + r_subtract <= subtract_i; + r_load_acc <= load_acc_i; + r_sat <= r_sat; + r_rnd <= r_rnd; + + end + end + + // Registered / non-registered input path select + wire [NBITS_A-1:0] a = REGISTER_INPUTS ? r_a : a_i; + wire [NBITS_B-1:0] b = REGISTER_INPUTS ? r_b : b_i; + + wire [5:0] acc_fir = REGISTER_INPUTS ? r_acc_fir : acc_fir_i; + wire unsigned_a = REGISTER_INPUTS ? r_unsigned_a : unsigned_a_i; + wire unsigned_b = REGISTER_INPUTS ? r_unsigned_b : unsigned_b_i; + wire [2:0] feedback = REGISTER_INPUTS ? r_feedback : feedback_i; + wire load_acc = REGISTER_INPUTS ? r_load_acc : load_acc_i; + wire subtract = REGISTER_INPUTS ? r_subtract : subtract_i; + wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE; + wire rnd = REGISTER_INPUTS ? r_rnd : ROUND; + + // Shift right control + wire [5:0] shift_d1 = REGISTER_INPUTS ? r_shift_d1 : SHIFT_RIGHT; + wire [5:0] shift_d2 = OUTPUT_SELECT[1] ? shift_d1 : r_shift_d2; + + // Multiplier + wire unsigned_mode = unsigned_a & unsigned_b; + wire [NBITS_A-1:0] mult_a; + assign mult_a = (feedback == 3'h0) ? a : + (feedback == 3'h1) ? a : + (feedback == 3'h2) ? a : + (feedback == 3'h3) ? acc[NBITS_A-1:0] : + (feedback == 3'h4) ? coef_0_i : + (feedback == 3'h5) ? coef_1_i : + (feedback == 3'h6) ? coef_2_i : + coef_3_i; // if feedback == 3'h7 + + wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; + + wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; + wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; + wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; + wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; + + wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; + wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); + + wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? + (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); + + // Sign extension + wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? + {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : + {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; + + // Adder + wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : + {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; + + wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; + wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : + (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); + + wire [NBITS_ACC-1:0] add_o = add_a + add_b; + + // Accumulator + initial acc <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) acc <= 'h0; + else begin + if (load_acc) + acc <= add_o; + else + acc <= acc; + end + + // Adder/accumulator output selection + wire [NBITS_ACC-1:0] acc_out = (OUTPUT_SELECT[1]) ? add_o : acc; + + // Round, shift, saturate + wire [NBITS_ACC-1:0] acc_rnd = (rnd && (SHIFT_RIGHT != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (SHIFT_RIGHT - 1))) : + acc_out; + + wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> SHIFT_RIGHT) : + (acc_rnd >>> SHIFT_RIGHT); + + wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; + + wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || + (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : + {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; + + wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; + + // Output signals + wire [NBITS_Z-1:0] z0; + reg [NBITS_Z-1:0] z1; + wire [NBITS_Z-1:0] z2; + + assign z0 = mult_xtnd[NBITS_Z-1:0]; + assign z2 = acc_sat[NBITS_Z-1:0]; + + initial z1 <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + z1 <= 0; + else begin + z1 <= (OUTPUT_SELECT == 3'b100) ? z0 : z2; + end + + // Output mux + assign z_o = (OUTPUT_SELECT == 3'h0) ? z0 : + (OUTPUT_SELECT == 3'h1) ? z2 : + (OUTPUT_SELECT == 3'h2) ? z2 : + (OUTPUT_SELECT == 3'h3) ? z2 : + (OUTPUT_SELECT == 3'h4) ? z1 : + (OUTPUT_SELECT == 3'h5) ? z1 : + (OUTPUT_SELECT == 3'h6) ? z1 : + z1; // if OUTPUT_SELECT == 3'h7 + + // B input delayed passthrough + initial dly_b_o <= 0; + + always @(posedge clock_i or posedge s_reset) + if (s_reset) + dly_b_o <= 0; + else + dly_b_o <= b_i; + +endmodule diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index d2df6bcff15..9692091909d 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -46,6 +46,15 @@ struct SynthQuickLogicPass : public ScriptPass { log(" - pp3: PolarPro 3 \n"); log(" - qlf_k6n10f: K6N10f\n"); log("\n"); + log(" -nodsp\n"); + log(" do not use dsp_t1_* to implement multipliers and associated logic\n"); + log(" (qlf_k6n10f only).\n"); + log("\n"); + log(" -use_dsp_cfg_params\n"); + log(" By default use DSP blocks with configuration bits available at module\n"); + log(" ports. Specifying this forces usage of DSP block with configuration\n"); + log(" bits available as module parameters.\n"); + log("\n"); log(" -nocarry\n"); log(" do not use adder_carry cells in output netlist.\n"); log("\n"); @@ -74,7 +83,7 @@ struct SynthQuickLogicPass : public ScriptPass { } string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; - bool abc9, inferAdder, nobram, bramTypes; + bool abc9, inferAdder, nobram, bramTypes, dsp; void clear_flags() override { @@ -89,6 +98,7 @@ struct SynthQuickLogicPass : public ScriptPass { nobram = false; bramTypes = false; lib_path = "+/quicklogic/"; + dsp = true; } void set_scratchpad_defaults(RTLIL::Design *design) { @@ -149,6 +159,14 @@ struct SynthQuickLogicPass : public ScriptPass { bramTypes = true; continue; } + if (args[argidx] == "-nodsp" || args[argidx] == "-no_dsp") { + dsp = false; + continue; + } + if (args[argidx] == "-use_dsp_cfg_params") { + use_dsp_cfg_params = " -use_dsp_cfg_params"; + continue; + } break; } extra_args(args, argidx, design); @@ -184,6 +202,8 @@ struct SynthQuickLogicPass : public ScriptPass { read_simlibs += stringf(" %sqlf_k6n10f/brams_sim.v", lib_path.c_str()); if (bramTypes) read_simlibs += stringf(" %sqlf_k6n10f/bram_types_sim.v", lib_path.c_str()); + if (dsp) + read_simlibs += stringf(" %sqlf_k6n10f/dsp_sim.v", lib_path.c_str()); } run(read_simlibs); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt.c_str())); @@ -208,6 +228,24 @@ struct SynthQuickLogicPass : public ScriptPass { run("share"); } + if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)") + && ((dsp && family == "qlf_k6n10f") || help_mode)) { + run("wreduce t:$mul"); + run("ql_dsp_macc" + use_dsp_cfg_params); + + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); + run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); + run("chtype -set $mul t:$__soft_mul"); + + if (use_dsp_cfg_params.empty()) + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); + else + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); + run("ql_dsp_simd"); + run("techmap -map " + lib_path + family + "/dsp_final_map.v"); + run("ql_dsp_io_regs"); + } + if (check_label("coarse")) { run("techmap -map +/cmp2lut.v -D LUT_WIDTH=4"); run("opt_expr"); @@ -219,15 +257,16 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } - if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") && (help_mode || family == "qlf_k6n10f")) { + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)")) { + if(family == "qlf_k6n10f" || help_mode) run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); run("techmap -map " + lib_path + family + "/brams_final_map.v"); - if (help_mode || bramTypes) { - run("ql_bram_types"); + if (bramTypes || help_mode) { + run("ql_bram_types", "(if -bramtypes)"); } } From b80b1ab8b6d80caa98c5af88e494d931072a4129 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Mon, 18 Sep 2023 12:45:06 +0200 Subject: [PATCH 05/39] merge brams_final_map.v into brams_map.v --- techlibs/quicklogic/Makefile.inc | 1 - .../quicklogic/qlf_k6n10f/brams_final_map.v | 1464 ----------------- techlibs/quicklogic/qlf_k6n10f/brams_map.v | 1449 ++++++++++++++++ techlibs/quicklogic/synth_quicklogic.cc | 1 - 4 files changed, 1449 insertions(+), 1466 deletions(-) delete mode 100644 techlibs/quicklogic/qlf_k6n10f/brams_final_map.v diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index ce5ff859b2e..852a8a77a88 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -31,7 +31,6 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_map.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_final_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/brams_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/cells_sim.v)) diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v deleted file mode 100644 index 43f5dc95e94..00000000000 --- a/techlibs/quicklogic/qlf_k6n10f/brams_final_map.v +++ /dev/null @@ -1,1464 +0,0 @@ -// Copyright 2020-2022 F4PGA Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 - -module BRAM2x18_SP ( - RESET_ni, - - WEN1_i, - REN1_i, - WR1_CLK_i, - RD1_CLK_i, - WR1_BE_i, - WR1_ADDR_i, - RD1_ADDR_i, - WDATA1_i, - RDATA1_o, - - WEN2_i, - REN2_i, - WR2_CLK_i, - RD2_CLK_i, - WR2_BE_i, - WR2_ADDR_i, - RD2_ADDR_i, - WDATA2_i, - RDATA2_o -); - -parameter WR1_ADDR_WIDTH = 10; -parameter RD1_ADDR_WIDTH = 10; -parameter WR1_DATA_WIDTH = 18; -parameter RD1_DATA_WIDTH = 18; -parameter BE1_WIDTH = 2; - -parameter WR2_ADDR_WIDTH = 10; -parameter RD2_ADDR_WIDTH = 10; -parameter WR2_DATA_WIDTH = 18; -parameter RD2_DATA_WIDTH = 18; -parameter BE2_WIDTH = 2; - -input wire RESET_ni; - -input wire WEN1_i; -input wire REN1_i; -input wire WR1_CLK_i; -input wire RD1_CLK_i; -input wire [BE1_WIDTH-1:0] WR1_BE_i; -input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; -input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; -input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; -output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; - -input wire WEN2_i; -input wire REN2_i; -input wire WR2_CLK_i; -input wire RD2_CLK_i; -input wire [BE2_WIDTH-1:0] WR2_BE_i; -input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; -input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; -input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; -output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; - -// Fixed mode settings -localparam [ 0:0] SYNC_FIFO1_i = 1'd0; -localparam [ 0:0] FMODE1_i = 1'd0; -localparam [ 0:0] POWERDN1_i = 1'd0; -localparam [ 0:0] SLEEP1_i = 1'd0; -localparam [ 0:0] PROTECT1_i = 1'd0; -localparam [11:0] UPAE1_i = 12'd10; -localparam [11:0] UPAF1_i = 12'd10; - -localparam [ 0:0] SYNC_FIFO2_i = 1'd0; -localparam [ 0:0] FMODE2_i = 1'd0; -localparam [ 0:0] POWERDN2_i = 1'd0; -localparam [ 0:0] SLEEP2_i = 1'd0; -localparam [ 0:0] PROTECT2_i = 1'd0; -localparam [10:0] UPAE2_i = 11'd10; -localparam [10:0] UPAF2_i = 11'd10; - -// Width mode function -function [2:0] mode; -input integer width; -case (width) -1: mode = 3'b101; -2: mode = 3'b110; -4: mode = 3'b100; -8,9: mode = 3'b001; -16, 18: mode = 3'b010; -32, 36: mode = 3'b011; -default: mode = 3'b000; -endcase -endfunction - -function integer rwmode; -input integer rwwidth; -case (rwwidth) -1: rwmode = 1; -2: rwmode = 2; -4: rwmode = 4; -8,9: rwmode = 9; -16, 18: rwmode = 18; -default: rwmode = 18; -endcase -endfunction - -wire REN_A1_i; -wire REN_A2_i; - -wire REN_B1_i; -wire REN_B2_i; - -wire WEN_A1_i; -wire WEN_A2_i; - -wire WEN_B1_i; -wire WEN_B2_i; - -wire [1:0] BE_A1_i; -wire [1:0] BE_A2_i; - -wire [1:0] BE_B1_i; -wire [1:0] BE_B2_i; - -wire [14:0] ADDR_A1_i; -wire [13:0] ADDR_A2_i; - -wire [14:0] ADDR_B1_i; -wire [13:0] ADDR_B2_i; - -wire [17:0] WDATA_A1_i; -wire [17:0] WDATA_A2_i; - -wire [17:0] WDATA_B1_i; -wire [17:0] WDATA_B2_i; - -wire [17:0] RDATA_A1_o; -wire [17:0] RDATA_A2_o; - -wire [17:0] RDATA_B1_o; -wire [17:0] RDATA_B2_o; - -wire [1:0] WR1_BE; -wire [1:0] WR2_BE; - -wire [17:0] PORT_B1_RDATA; -wire [17:0] PORT_A1_WDATA; - -wire [17:0] PORT_B2_RDATA; -wire [17:0] PORT_A2_WDATA; - -wire [13:0] WR1_ADDR_INT; -wire [13:0] RD1_ADDR_INT; - -wire [13:0] WR2_ADDR_INT; -wire [13:0] RD2_ADDR_INT; - -wire [13:0] PORT_A1_ADDR; -wire [13:0] PORT_B1_ADDR; - -wire [13:0] PORT_A2_ADDR; -wire [13:0] PORT_B2_ADDR; - - -// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) -localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); -localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); -localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); -localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - -localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); -localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); -localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); -localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - -localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); -localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); -localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); -localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - -generate - if (WR1_ADDR_WIDTH == 14) begin - assign WR1_ADDR_INT = WR1_ADDR_i; - end else begin - assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; - assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; - end -endgenerate - -case (WR1_DATA_WIDTH) - 1: begin - assign PORT_A1_ADDR = WR1_ADDR_INT; - end - 2: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 1; - end - 4: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A1_ADDR = WR1_ADDR_INT << 4; - end - default: begin - assign PORT_A1_ADDR = WR1_ADDR_INT; - end -endcase - -generate - if (RD1_ADDR_WIDTH == 14) begin - assign RD1_ADDR_INT = RD1_ADDR_i; - end else begin - assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; - assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; - end -endgenerate - -case (RD1_DATA_WIDTH) - 1: begin - assign PORT_B1_ADDR = RD1_ADDR_INT; - end - 2: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 1; - end - 4: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B1_ADDR = RD1_ADDR_INT << 4; - end - default: begin - assign PORT_B1_ADDR = RD1_ADDR_INT; - end -endcase - -generate - if (WR2_ADDR_WIDTH == 14) begin - assign WR2_ADDR_INT = WR2_ADDR_i; - end else begin - assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; - assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; - end -endgenerate - -case (WR2_DATA_WIDTH) - 1: begin - assign PORT_A2_ADDR = WR2_ADDR_INT; - end - 2: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 1; - end - 4: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A2_ADDR = WR2_ADDR_INT << 4; - end - default: begin - assign PORT_A2_ADDR = WR2_ADDR_INT; - end -endcase - -generate - if (RD2_ADDR_WIDTH == 14) begin - assign RD2_ADDR_INT = RD2_ADDR_i; - end else begin - assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; - assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; - end -endgenerate - -case (RD2_DATA_WIDTH) - 1: begin - assign PORT_B2_ADDR = RD2_ADDR_INT; - end - 2: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 1; - end - 4: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B2_ADDR = RD2_ADDR_INT << 4; - end - default: begin - assign PORT_B2_ADDR = RD2_ADDR_INT; - end -endcase - -case (BE1_WIDTH) - 2: begin - assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; - end - default: begin - assign WR1_BE[1:BE1_WIDTH] = 0; - assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; - end -endcase - -case (BE2_WIDTH) - 2: begin - assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; - end - default: begin - assign WR2_BE[1:BE2_WIDTH] = 0; - assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; - end -endcase - -assign REN_A1_i = 1'b0; -assign WEN_A1_i = WEN1_i; -assign BE_A1_i = WR1_BE; -assign REN_A2_i = 1'b0; -assign WEN_A2_i = WEN2_i; -assign BE_A2_i = WR2_BE; - -assign REN_B1_i = REN1_i; -assign WEN_B1_i = 1'b0; -assign BE_B1_i = 4'h0; -assign REN_B2_i = REN2_i; -assign WEN_B2_i = 1'b0; -assign BE_B2_i = 4'h0; - -generate - if (WR1_DATA_WIDTH == 18) begin - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; - assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; - end -endgenerate - -assign WDATA_A1_i = PORT_A1_WDATA[17:0]; -assign WDATA_B1_i = 18'h0; - -generate - if (RD1_DATA_WIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end -endgenerate - -assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; - -generate - if (WR2_DATA_WIDTH == 18) begin - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; - assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; - end -endgenerate - -assign WDATA_A2_i = PORT_A2_WDATA[17:0]; -assign WDATA_B2_i = 18'h0; - -generate - if (RD2_DATA_WIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end -endgenerate - -assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; - -defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i -}; - -(* is_inferred = 0 *) -(* is_split = 0 *) -(* is_fifo = 0 *) -(* port_a_dwidth = PORT_A1_WRWIDTH *) -(* port_b_dwidth = PORT_B1_WRWIDTH *) -TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - - .CLK_A1_i(WR1_CLK_i), - .ADDR_A1_i({1'b0,PORT_A1_ADDR}), - .WEN_A1_i(WEN_A1_i), - .BE_A1_i(BE_A1_i), - .WDATA_A1_i(WDATA_A1_i), - .REN_A1_i(REN_A1_i), - .RDATA_A1_o(RDATA_A1_o), - - .CLK_A2_i(WR2_CLK_i), - .ADDR_A2_i(PORT_A2_ADDR), - .WEN_A2_i(WEN_A2_i), - .BE_A2_i(BE_A2_i), - .WDATA_A2_i(WDATA_A2_i), - .REN_A2_i(REN_A2_i), - .RDATA_A2_o(RDATA_A2_o), - - .CLK_B1_i(RD1_CLK_i), - .ADDR_B1_i({1'b0,PORT_B1_ADDR}), - .WEN_B1_i(WEN_B1_i), - .BE_B1_i(BE_B1_i), - .WDATA_B1_i(WDATA_B1_i), - .REN_B1_i(REN_B1_i), - .RDATA_B1_o(RDATA_B1_o), - - .CLK_B2_i(RD2_CLK_i), - .ADDR_B2_i(PORT_B2_ADDR), - .WEN_B2_i(WEN_B2_i), - .BE_B2_i(BE_B2_i), - .WDATA_B2_i(WDATA_B2_i), - .REN_B2_i(REN_B2_i), - .RDATA_B2_o(RDATA_B2_o), - - .FLUSH1_i(1'b0), - .FLUSH2_i(1'b0) -); - -endmodule - -module BRAM2x18_dP ( - PORT_A1_CLK_i, - PORT_A1_WEN_i, - PORT_A1_WR_BE_i, - PORT_A1_REN_i, - PORT_A1_ADDR_i, - PORT_A1_WR_DATA_i, - PORT_A1_RD_DATA_o, - - PORT_B1_CLK_i, - PORT_B1_WEN_i, - PORT_B1_WR_BE_i, - PORT_B1_REN_i, - PORT_B1_ADDR_i, - PORT_B1_WR_DATA_i, - PORT_B1_RD_DATA_o, - - PORT_A2_CLK_i, - PORT_A2_WEN_i, - PORT_A2_WR_BE_i, - PORT_A2_REN_i, - PORT_A2_ADDR_i, - PORT_A2_WR_DATA_i, - PORT_A2_RD_DATA_o, - - PORT_B2_CLK_i, - PORT_B2_WEN_i, - PORT_B2_WR_BE_i, - PORT_B2_REN_i, - PORT_B2_ADDR_i, - PORT_B2_WR_DATA_i, - PORT_B2_RD_DATA_o -); - -parameter PORT_A1_AWIDTH = 10; -parameter PORT_A1_DWIDTH = 18; -parameter PORT_A1_WR_BE_WIDTH = 2; - -parameter PORT_B1_AWIDTH = 10; -parameter PORT_B1_DWIDTH = 18; -parameter PORT_B1_WR_BE_WIDTH = 2; - -parameter PORT_A2_AWIDTH = 10; -parameter PORT_A2_DWIDTH = 18; -parameter PORT_A2_WR_BE_WIDTH = 2; - -parameter PORT_B2_AWIDTH = 10; -parameter PORT_B2_DWIDTH = 18; -parameter PORT_B2_WR_BE_WIDTH = 2; - -input PORT_A1_CLK_i; -input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; -input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; -input PORT_A1_WEN_i; -input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; -input PORT_A1_REN_i; -output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; - -input PORT_B1_CLK_i; -input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; -input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; -input PORT_B1_WEN_i; -input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; -input PORT_B1_REN_i; -output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; - -input PORT_A2_CLK_i; -input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; -input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; -input PORT_A2_WEN_i; -input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; -input PORT_A2_REN_i; -output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; - -input PORT_B2_CLK_i; -input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; -input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; -input PORT_B2_WEN_i; -input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; -input PORT_B2_REN_i; -output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; - - -// Fixed mode settings -localparam [ 0:0] SYNC_FIFO1_i = 1'd0; -localparam [ 0:0] FMODE1_i = 1'd0; -localparam [ 0:0] POWERDN1_i = 1'd0; -localparam [ 0:0] SLEEP1_i = 1'd0; -localparam [ 0:0] PROTECT1_i = 1'd0; -localparam [11:0] UPAE1_i = 12'd10; -localparam [11:0] UPAF1_i = 12'd10; - -localparam [ 0:0] SYNC_FIFO2_i = 1'd0; -localparam [ 0:0] FMODE2_i = 1'd0; -localparam [ 0:0] POWERDN2_i = 1'd0; -localparam [ 0:0] SLEEP2_i = 1'd0; -localparam [ 0:0] PROTECT2_i = 1'd0; -localparam [10:0] UPAE2_i = 11'd10; -localparam [10:0] UPAF2_i = 11'd10; - -// Width mode function -function [2:0] mode; -input integer width; -case (width) -1: mode = 3'b101; -2: mode = 3'b110; -4: mode = 3'b100; -8,9: mode = 3'b001; -16, 18: mode = 3'b010; -32, 36: mode = 3'b011; -default: mode = 3'b000; -endcase -endfunction - -function integer rwmode; -input integer rwwidth; -case (rwwidth) -1: rwmode = 1; -2: rwmode = 2; -4: rwmode = 4; -8,9: rwmode = 9; -16, 18: rwmode = 18; -default: rwmode = 18; -endcase -endfunction - -wire REN_A1_i; -wire REN_A2_i; - -wire REN_B1_i; -wire REN_B2_i; - -wire WEN_A1_i; -wire WEN_A2_i; - -wire WEN_B1_i; -wire WEN_B2_i; - -wire [1:0] BE_A1_i; -wire [1:0] BE_A2_i; - -wire [1:0] BE_B1_i; -wire [1:0] BE_B2_i; - -wire [14:0] ADDR_A1_i; -wire [13:0] ADDR_A2_i; - -wire [14:0] ADDR_B1_i; -wire [13:0] ADDR_B2_i; - -wire [17:0] WDATA_A1_i; -wire [17:0] WDATA_A2_i; - -wire [17:0] WDATA_B1_i; -wire [17:0] WDATA_B2_i; - -wire [17:0] RDATA_A1_o; -wire [17:0] RDATA_A2_o; - -wire [17:0] RDATA_B1_o; -wire [17:0] RDATA_B2_o; - -wire [1:0] PORT_A1_WR_BE; -wire [1:0] PORT_B1_WR_BE; - -wire [1:0] PORT_A2_WR_BE; -wire [1:0] PORT_B2_WR_BE; - -wire [17:0] PORT_B1_WDATA; -wire [17:0] PORT_B1_RDATA; -wire [17:0] PORT_A1_WDATA; -wire [17:0] PORT_A1_RDATA; - -wire [17:0] PORT_B2_WDATA; -wire [17:0] PORT_B2_RDATA; -wire [17:0] PORT_A2_WDATA; -wire [17:0] PORT_A2_RDATA; - -wire [13:0] PORT_A1_ADDR_INT; -wire [13:0] PORT_B1_ADDR_INT; - -wire [13:0] PORT_A2_ADDR_INT; -wire [13:0] PORT_B2_ADDR_INT; - -wire [13:0] PORT_A1_ADDR; -wire [13:0] PORT_B1_ADDR; - -wire [13:0] PORT_A2_ADDR; -wire [13:0] PORT_B2_ADDR; - -wire PORT_A1_CLK; -wire PORT_B1_CLK; - -wire PORT_A2_CLK; -wire PORT_B2_CLK; - -// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) -localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); -localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); -localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); -localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); - -localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); -localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); -localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); -localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); - -localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); -localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); -localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); -localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); - -assign PORT_A1_CLK = PORT_A1_CLK_i; -assign PORT_B1_CLK = PORT_B1_CLK_i; - -assign PORT_A2_CLK = PORT_A2_CLK_i; -assign PORT_B2_CLK = PORT_B2_CLK_i; - -generate - if (PORT_A1_AWIDTH == 14) begin - assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; - end else begin - assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; - assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; - end -endgenerate - -case (PORT_A1_DWIDTH) - 1: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT; - end - 2: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; - end - 4: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; - end - default: begin - assign PORT_A1_ADDR = PORT_A1_ADDR_INT; - end -endcase - -generate - if (PORT_B1_AWIDTH == 14) begin - assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; - end else begin - assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; - assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; - end -endgenerate - -case (PORT_B1_DWIDTH) - 1: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT; - end - 2: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; - end - 4: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; - end - default: begin - assign PORT_B1_ADDR = PORT_B1_ADDR_INT; - end -endcase - -generate - if (PORT_A2_AWIDTH == 14) begin - assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; - end else begin - assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; - assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; - end -endgenerate - -case (PORT_A2_DWIDTH) - 1: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT; - end - 2: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; - end - 4: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; - end - default: begin - assign PORT_A2_ADDR = PORT_A2_ADDR_INT; - end -endcase - -generate - if (PORT_B2_AWIDTH == 14) begin - assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; - end else begin - assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; - assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; - end -endgenerate - -case (PORT_B2_DWIDTH) - 1: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT; - end - 2: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; - end - 4: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; - end - 8, 9: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; - end - 16, 18: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; - end - default: begin - assign PORT_B2_ADDR = PORT_B2_ADDR_INT; - end -endcase - -case (PORT_A1_WR_BE_WIDTH) - 2: begin - assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; - assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; - end -endcase - -case (PORT_B1_WR_BE_WIDTH) - 2: begin - assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; - assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; - end -endcase - -case (PORT_A2_WR_BE_WIDTH) - 2: begin - assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; - assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; - end -endcase - -case (PORT_B2_WR_BE_WIDTH) - 2: begin - assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; - end - default: begin - assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; - assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; - end -endcase - -assign REN_A1_i = PORT_A1_REN_i; -assign WEN_A1_i = PORT_A1_WEN_i; -assign BE_A1_i = PORT_A1_WR_BE; - -assign REN_A2_i = PORT_A2_REN_i; -assign WEN_A2_i = PORT_A2_WEN_i; -assign BE_A2_i = PORT_A2_WR_BE; - -assign REN_B1_i = PORT_B1_REN_i; -assign WEN_B1_i = PORT_B1_WEN_i; -assign BE_B1_i = PORT_B1_WR_BE; - -assign REN_B2_i = PORT_B2_REN_i; -assign WEN_B2_i = PORT_B2_WEN_i; -assign BE_B2_i = PORT_B2_WR_BE; - -generate - if (PORT_A1_DWIDTH == 18) begin - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end else if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; - end else begin - assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; - assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_A1_i = PORT_A1_WDATA; - -generate - if (PORT_A2_DWIDTH == 18) begin - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end else if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; - end else begin - assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; - assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_A2_i = PORT_A2_WDATA; - -generate - if (PORT_A1_DWIDTH == 9) begin - assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; - end else begin - assign PORT_A1_RDATA = RDATA_A1_o; - end -endgenerate - -assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; - -generate - if (PORT_A2_DWIDTH == 9) begin - assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; - end else begin - assign PORT_A2_RDATA = RDATA_A2_o; - end -endgenerate - -assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; - -generate - if (PORT_B1_DWIDTH == 18) begin - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end else if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; - end else begin - assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; - assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_B1_i = PORT_B1_WDATA; - -generate - if (PORT_B2_DWIDTH == 18) begin - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end else if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; - end else begin - assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; - assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; - end -endgenerate - -assign WDATA_B2_i = PORT_B2_WDATA; - -generate - if (PORT_B1_DWIDTH == 9) begin - assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; - end else begin - assign PORT_B1_RDATA = RDATA_B1_o; - end -endgenerate - -assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; - -generate - if (PORT_B2_DWIDTH == 9) begin - assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; - end else begin - assign PORT_B2_RDATA = RDATA_B2_o; - end -endgenerate - -assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; - -defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i -}; - -(* is_inferred = 0 *) -(* is_split = 0 *) -(* is_fifo = 0 *) -(* port_a_dwidth = PORT_A1_WRWIDTH *) -(* port_b_dwidth = PORT_B1_WRWIDTH *) -TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - - .CLK_A1_i(PORT_A1_CLK), - .ADDR_A1_i({1'b0,PORT_A1_ADDR}), - .WEN_A1_i(WEN_A1_i), - .BE_A1_i(BE_A1_i), - .WDATA_A1_i(WDATA_A1_i), - .REN_A1_i(REN_A1_i), - .RDATA_A1_o(RDATA_A1_o), - - .CLK_A2_i(PORT_A2_CLK), - .ADDR_A2_i(PORT_A2_ADDR), - .WEN_A2_i(WEN_A2_i), - .BE_A2_i(BE_A2_i), - .WDATA_A2_i(WDATA_A2_i), - .REN_A2_i(REN_A2_i), - .RDATA_A2_o(RDATA_A2_o), - - .CLK_B1_i(PORT_B1_CLK), - .ADDR_B1_i({1'b0,PORT_B1_ADDR}), - .WEN_B1_i(WEN_B1_i), - .BE_B1_i(BE_B1_i), - .WDATA_B1_i(WDATA_B1_i), - .REN_B1_i(REN_B1_i), - .RDATA_B1_o(RDATA_B1_o), - - .CLK_B2_i(PORT_B2_CLK), - .ADDR_B2_i(PORT_B2_ADDR), - .WEN_B2_i(WEN_B2_i), - .BE_B2_i(BE_B2_i), - .WDATA_B2_i(WDATA_B2_i), - .REN_B2_i(REN_B2_i), - .RDATA_B2_o(RDATA_B2_o), - - .FLUSH1_i(1'b0), - .FLUSH2_i(1'b0) -); - -endmodule - - -module BRAM2x18_SFIFO ( - DIN1, - PUSH1, - POP1, - CLK1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - CLK2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 -); - - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input CLK1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input CLK2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd1; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd1; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - assign Push_Clk1 = CLK1; - assign Pop_Clk1 = CLK1; - assign Push_Clk2 = CLK2; - assign Pop_Clk2 = CLK2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i - }; - - (* is_fifo = 1 *) - (* sync_fifo = 1 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - .WDATA_A1_i(in_reg1[17:0]), - .WDATA_A2_i(in_reg2[17:0]), - .RDATA_A1_o(fifo1_flags), - .RDATA_A2_o(fifo2_flags), - .ADDR_A1_i(14'h0), - .ADDR_A2_i(14'h0), - .CLK_A1_i(Push_Clk1), - .CLK_A2_i(Push_Clk2), - .REN_A1_i(1'b1), - .REN_A2_i(1'b1), - .WEN_A1_i(PUSH1), - .WEN_A2_i(PUSH2), - .BE_A1_i(2'b11), - .BE_A2_i(2'b11), - - .WDATA_B1_i(18'h0), - .WDATA_B2_i(18'h0), - .RDATA_B1_o(out_reg1[17:0]), - .RDATA_B2_o(out_reg2[17:0]), - .ADDR_B1_i(14'h0), - .ADDR_B2_i(14'h0), - .CLK_B1_i(Pop_Clk1), - .CLK_B2_i(Pop_Clk2), - .REN_B1_i(POP1), - .REN_B2_i(POP2), - .WEN_B1_i(1'b0), - .WEN_B2_i(1'b0), - .BE_B1_i(2'b11), - .BE_B2_i(2'b11), - - .FLUSH1_i(Async_Flush1), - .FLUSH2_i(Async_Flush2) - ); - -endmodule - - -module BRAM2x18_AFIFO ( - DIN1, - PUSH1, - POP1, - Push_Clk1, - Pop_Clk1, - Async_Flush1, - Overrun_Error1, - Full_Watermark1, - Almost_Full1, - Full1, - Underrun_Error1, - Empty_Watermark1, - Almost_Empty1, - Empty1, - DOUT1, - - DIN2, - PUSH2, - POP2, - Push_Clk2, - Pop_Clk2, - Async_Flush2, - Overrun_Error2, - Full_Watermark2, - Almost_Full2, - Full2, - Underrun_Error2, - Empty_Watermark2, - Almost_Empty2, - Empty2, - DOUT2 -); - - parameter WR1_DATA_WIDTH = 18; - parameter RD1_DATA_WIDTH = 18; - - parameter WR2_DATA_WIDTH = 18; - parameter RD2_DATA_WIDTH = 18; - - parameter UPAE_DBITS1 = 12'd10; - parameter UPAF_DBITS1 = 12'd10; - - parameter UPAE_DBITS2 = 11'd10; - parameter UPAF_DBITS2 = 11'd10; - - input Push_Clk1, Pop_Clk1; - input PUSH1, POP1; - input [WR1_DATA_WIDTH-1:0] DIN1; - input Async_Flush1; - output [RD1_DATA_WIDTH-1:0] DOUT1; - output Almost_Full1, Almost_Empty1; - output Full1, Empty1; - output Full_Watermark1, Empty_Watermark1; - output Overrun_Error1, Underrun_Error1; - - input Push_Clk2, Pop_Clk2; - input PUSH2, POP2; - input [WR2_DATA_WIDTH-1:0] DIN2; - input Async_Flush2; - output [RD2_DATA_WIDTH-1:0] DOUT2; - output Almost_Full2, Almost_Empty2; - output Full2, Empty2; - output Full_Watermark2, Empty_Watermark2; - output Overrun_Error2, Underrun_Error2; - - // Fixed mode settings - localparam [ 0:0] SYNC_FIFO1_i = 1'd0; - localparam [ 0:0] FMODE1_i = 1'd1; - localparam [ 0:0] POWERDN1_i = 1'd0; - localparam [ 0:0] SLEEP1_i = 1'd0; - localparam [ 0:0] PROTECT1_i = 1'd0; - localparam [11:0] UPAE1_i = UPAE_DBITS1; - localparam [11:0] UPAF1_i = UPAF_DBITS1; - - localparam [ 0:0] SYNC_FIFO2_i = 1'd0; - localparam [ 0:0] FMODE2_i = 1'd1; - localparam [ 0:0] POWERDN2_i = 1'd0; - localparam [ 0:0] SLEEP2_i = 1'd0; - localparam [ 0:0] PROTECT2_i = 1'd0; - localparam [10:0] UPAE2_i = UPAE_DBITS2; - localparam [10:0] UPAF2_i = UPAF_DBITS2; - - // Width mode function - function [2:0] mode; - input integer width; - case (width) - 1: mode = 3'b101; - 2: mode = 3'b110; - 4: mode = 3'b100; - 8,9: mode = 3'b001; - 16, 18: mode = 3'b010; - 32, 36: mode = 3'b011; - default: mode = 3'b000; - endcase - endfunction - - function integer rwmode; - input integer rwwidth; - case (rwwidth) - 1: rwmode = 1; - 2: rwmode = 2; - 4: rwmode = 4; - 8,9: rwmode = 9; - 16, 18: rwmode = 18; - default: rwmode = 18; - endcase - endfunction - - wire [17:0] in_reg1; - wire [17:0] out_reg1; - wire [17:0] fifo1_flags; - - wire [17:0] in_reg2; - wire [17:0] out_reg2; - wire [17:0] fifo2_flags; - - wire Push_Clk1, Pop_Clk1; - wire Push_Clk2, Pop_Clk2; - - assign Overrun_Error1 = fifo1_flags[0]; - assign Full_Watermark1 = fifo1_flags[1]; - assign Almost_Full1 = fifo1_flags[2]; - assign Full1 = fifo1_flags[3]; - assign Underrun_Error1 = fifo1_flags[4]; - assign Empty_Watermark1 = fifo1_flags[5]; - assign Almost_Empty1 = fifo1_flags[6]; - assign Empty1 = fifo1_flags[7]; - - assign Overrun_Error2 = fifo2_flags[0]; - assign Full_Watermark2 = fifo2_flags[1]; - assign Almost_Full2 = fifo2_flags[2]; - assign Full2 = fifo2_flags[3]; - assign Underrun_Error2 = fifo2_flags[4]; - assign Empty_Watermark2 = fifo2_flags[5]; - assign Almost_Empty2 = fifo2_flags[6]; - assign Empty2 = fifo2_flags[7]; - - localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); - localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); - localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); - - localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); - localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); - localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); - - localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); - localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); - localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); - localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); - - generate - if (WR1_DATA_WIDTH == 18) begin - assign in_reg1[17:0] = DIN1[17:0]; - end else if (WR1_DATA_WIDTH == 9) begin - assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; - end else begin - assign in_reg1[17:WR1_DATA_WIDTH] = 0; - assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD1_DATA_WIDTH == 9) begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; - end else begin - assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (WR2_DATA_WIDTH == 18) begin - assign in_reg2[17:0] = DIN2[17:0]; - end else if (WR2_DATA_WIDTH == 9) begin - assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; - end else begin - assign in_reg2[17:WR2_DATA_WIDTH] = 0; - assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; - end - endgenerate - - generate - if (RD2_DATA_WIDTH == 9) begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; - end else begin - assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; - end - endgenerate - - defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, - UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, - UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i - }; - - (* is_fifo = 1 *) - (* sync_fifo = 0 *) - (* is_split = 0 *) - (* is_inferred = 0 *) - (* port_a_dwidth = PORT_A1_WRWIDTH *) - (* port_b_dwidth = PORT_B1_WRWIDTH *) - TDP36K _TECHMAP_REPLACE_ ( - .RESET_ni(1'b1), - .WDATA_A1_i(in_reg1[17:0]), - .WDATA_A2_i(in_reg2[17:0]), - .RDATA_A1_o(fifo1_flags), - .RDATA_A2_o(fifo2_flags), - .ADDR_A1_i(14'h0), - .ADDR_A2_i(14'h0), - .CLK_A1_i(Push_Clk1), - .CLK_A2_i(Push_Clk2), - .REN_A1_i(1'b1), - .REN_A2_i(1'b1), - .WEN_A1_i(PUSH1), - .WEN_A2_i(PUSH2), - .BE_A1_i(2'b11), - .BE_A2_i(2'b11), - - .WDATA_B1_i(18'h0), - .WDATA_B2_i(18'h0), - .RDATA_B1_o(out_reg1[17:0]), - .RDATA_B2_o(out_reg2[17:0]), - .ADDR_B1_i(14'h0), - .ADDR_B2_i(14'h0), - .CLK_B1_i(Pop_Clk1), - .CLK_B2_i(Pop_Clk2), - .REN_B1_i(POP1), - .REN_B2_i(POP2), - .WEN_B1_i(1'b0), - .WEN_B2_i(1'b0), - .BE_B1_i(2'b11), - .BE_B2_i(2'b11), - - .FLUSH1_i(Async_Flush1), - .FLUSH2_i(Async_Flush2) - ); - -endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_map.v b/techlibs/quicklogic/qlf_k6n10f/brams_map.v index 82bbceeff52..ba6382a2395 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_map.v @@ -2836,4 +2836,1453 @@ module AFIFO_18K_X2_BLK ( .FLUSH2_i(Async_Flush2) ); +endmodule + +module BRAM2x18_SP ( + RESET_ni, + + WEN1_i, + REN1_i, + WR1_CLK_i, + RD1_CLK_i, + WR1_BE_i, + WR1_ADDR_i, + RD1_ADDR_i, + WDATA1_i, + RDATA1_o, + + WEN2_i, + REN2_i, + WR2_CLK_i, + RD2_CLK_i, + WR2_BE_i, + WR2_ADDR_i, + RD2_ADDR_i, + WDATA2_i, + RDATA2_o +); + +parameter WR1_ADDR_WIDTH = 10; +parameter RD1_ADDR_WIDTH = 10; +parameter WR1_DATA_WIDTH = 18; +parameter RD1_DATA_WIDTH = 18; +parameter BE1_WIDTH = 2; + +parameter WR2_ADDR_WIDTH = 10; +parameter RD2_ADDR_WIDTH = 10; +parameter WR2_DATA_WIDTH = 18; +parameter RD2_DATA_WIDTH = 18; +parameter BE2_WIDTH = 2; + +input wire RESET_ni; + +input wire WEN1_i; +input wire REN1_i; +input wire WR1_CLK_i; +input wire RD1_CLK_i; +input wire [BE1_WIDTH-1:0] WR1_BE_i; +input wire [WR1_ADDR_WIDTH-1 :0] WR1_ADDR_i; +input wire [RD1_ADDR_WIDTH-1 :0] RD1_ADDR_i; +input wire [WR1_DATA_WIDTH-1 :0] WDATA1_i; +output wire [RD1_DATA_WIDTH-1 :0] RDATA1_o; + +input wire WEN2_i; +input wire REN2_i; +input wire WR2_CLK_i; +input wire RD2_CLK_i; +input wire [BE2_WIDTH-1:0] WR2_BE_i; +input wire [WR2_ADDR_WIDTH-1 :0] WR2_ADDR_i; +input wire [RD2_ADDR_WIDTH-1 :0] RD2_ADDR_i; +input wire [WR2_DATA_WIDTH-1 :0] WDATA2_i; +output wire [RD2_DATA_WIDTH-1 :0] RDATA2_o; + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] WR1_BE; +wire [1:0] WR2_BE; + +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; + +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; + +wire [13:0] WR1_ADDR_INT; +wire [13:0] RD1_ADDR_INT; + +wire [13:0] WR2_ADDR_INT; +wire [13:0] RD2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); +localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); +localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); +localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); +localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); +localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); +localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); +localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + +generate + if (WR1_ADDR_WIDTH == 14) begin + assign WR1_ADDR_INT = WR1_ADDR_i; + end else begin + assign WR1_ADDR_INT[13:WR1_ADDR_WIDTH] = 0; + assign WR1_ADDR_INT[WR1_ADDR_WIDTH-1:0] = WR1_ADDR_i; + end +endgenerate + +case (WR1_DATA_WIDTH) + 1: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = WR1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = WR1_ADDR_INT; + end +endcase + +generate + if (RD1_ADDR_WIDTH == 14) begin + assign RD1_ADDR_INT = RD1_ADDR_i; + end else begin + assign RD1_ADDR_INT[13:RD1_ADDR_WIDTH] = 0; + assign RD1_ADDR_INT[RD1_ADDR_WIDTH-1:0] = RD1_ADDR_i; + end +endgenerate + +case (RD1_DATA_WIDTH) + 1: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = RD1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = RD1_ADDR_INT; + end +endcase + +generate + if (WR2_ADDR_WIDTH == 14) begin + assign WR2_ADDR_INT = WR2_ADDR_i; + end else begin + assign WR2_ADDR_INT[13:WR2_ADDR_WIDTH] = 0; + assign WR2_ADDR_INT[WR2_ADDR_WIDTH-1:0] = WR2_ADDR_i; + end +endgenerate + +case (WR2_DATA_WIDTH) + 1: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = WR2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = WR2_ADDR_INT; + end +endcase + +generate + if (RD2_ADDR_WIDTH == 14) begin + assign RD2_ADDR_INT = RD2_ADDR_i; + end else begin + assign RD2_ADDR_INT[13:RD2_ADDR_WIDTH] = 0; + assign RD2_ADDR_INT[RD2_ADDR_WIDTH-1:0] = RD2_ADDR_i; + end +endgenerate + +case (RD2_DATA_WIDTH) + 1: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = RD2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = RD2_ADDR_INT; + end +endcase + +case (BE1_WIDTH) + 2: begin + assign WR1_BE = WR1_BE_i[BE1_WIDTH-1 :0]; + end + default: begin + assign WR1_BE[1:BE1_WIDTH] = 0; + assign WR1_BE[BE1_WIDTH-1 :0] = WR1_BE_i[BE1_WIDTH-1 :0]; + end +endcase + +case (BE2_WIDTH) + 2: begin + assign WR2_BE = WR2_BE_i[BE2_WIDTH-1 :0]; + end + default: begin + assign WR2_BE[1:BE2_WIDTH] = 0; + assign WR2_BE[BE2_WIDTH-1 :0] = WR2_BE_i[BE2_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = 1'b0; +assign WEN_A1_i = WEN1_i; +assign BE_A1_i = WR1_BE; +assign REN_A2_i = 1'b0; +assign WEN_A2_i = WEN2_i; +assign BE_A2_i = WR2_BE; + +assign REN_B1_i = REN1_i; +assign WEN_B1_i = 1'b0; +assign BE_B1_i = 4'h0; +assign REN_B2_i = REN2_i; +assign WEN_B2_i = 1'b0; +assign BE_B2_i = 4'h0; + +generate + if (WR1_DATA_WIDTH == 18) begin + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, WDATA1_i[8], 8'h0, WDATA1_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:WR1_DATA_WIDTH] = 0; + assign PORT_A1_WDATA[WR1_DATA_WIDTH-1:0] = WDATA1_i[WR1_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA[17:0]; +assign WDATA_B1_i = 18'h0; + +generate + if (RD1_DATA_WIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign RDATA1_o = PORT_B1_RDATA[RD1_DATA_WIDTH-1:0]; + +generate + if (WR2_DATA_WIDTH == 18) begin + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, WDATA2_i[8], 8'h0, WDATA2_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:WR2_DATA_WIDTH] = 0; + assign PORT_A2_WDATA[WR2_DATA_WIDTH-1:0] = WDATA2_i[WR2_DATA_WIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA[17:0]; +assign WDATA_B2_i = 18'h0; + +generate + if (RD2_DATA_WIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign RDATA2_o = PORT_B2_RDATA[RD2_DATA_WIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(WR1_CLK_i), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(WR2_CLK_i), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(RD1_CLK_i), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(RD2_CLK_i), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + +module BRAM2x18_dP ( + PORT_A1_CLK_i, + PORT_A1_WEN_i, + PORT_A1_WR_BE_i, + PORT_A1_REN_i, + PORT_A1_ADDR_i, + PORT_A1_WR_DATA_i, + PORT_A1_RD_DATA_o, + + PORT_B1_CLK_i, + PORT_B1_WEN_i, + PORT_B1_WR_BE_i, + PORT_B1_REN_i, + PORT_B1_ADDR_i, + PORT_B1_WR_DATA_i, + PORT_B1_RD_DATA_o, + + PORT_A2_CLK_i, + PORT_A2_WEN_i, + PORT_A2_WR_BE_i, + PORT_A2_REN_i, + PORT_A2_ADDR_i, + PORT_A2_WR_DATA_i, + PORT_A2_RD_DATA_o, + + PORT_B2_CLK_i, + PORT_B2_WEN_i, + PORT_B2_WR_BE_i, + PORT_B2_REN_i, + PORT_B2_ADDR_i, + PORT_B2_WR_DATA_i, + PORT_B2_RD_DATA_o +); + +parameter PORT_A1_AWIDTH = 10; +parameter PORT_A1_DWIDTH = 18; +parameter PORT_A1_WR_BE_WIDTH = 2; + +parameter PORT_B1_AWIDTH = 10; +parameter PORT_B1_DWIDTH = 18; +parameter PORT_B1_WR_BE_WIDTH = 2; + +parameter PORT_A2_AWIDTH = 10; +parameter PORT_A2_DWIDTH = 18; +parameter PORT_A2_WR_BE_WIDTH = 2; + +parameter PORT_B2_AWIDTH = 10; +parameter PORT_B2_DWIDTH = 18; +parameter PORT_B2_WR_BE_WIDTH = 2; + +input PORT_A1_CLK_i; +input [PORT_A1_AWIDTH-1:0] PORT_A1_ADDR_i; +input [PORT_A1_DWIDTH-1:0] PORT_A1_WR_DATA_i; +input PORT_A1_WEN_i; +input [PORT_A1_WR_BE_WIDTH-1:0] PORT_A1_WR_BE_i; +input PORT_A1_REN_i; +output [PORT_A1_DWIDTH-1:0] PORT_A1_RD_DATA_o; + +input PORT_B1_CLK_i; +input [PORT_B1_AWIDTH-1:0] PORT_B1_ADDR_i; +input [PORT_B1_DWIDTH-1:0] PORT_B1_WR_DATA_i; +input PORT_B1_WEN_i; +input [PORT_B1_WR_BE_WIDTH-1:0] PORT_B1_WR_BE_i; +input PORT_B1_REN_i; +output [PORT_B1_DWIDTH-1:0] PORT_B1_RD_DATA_o; + +input PORT_A2_CLK_i; +input [PORT_A2_AWIDTH-1:0] PORT_A2_ADDR_i; +input [PORT_A2_DWIDTH-1:0] PORT_A2_WR_DATA_i; +input PORT_A2_WEN_i; +input [PORT_A2_WR_BE_WIDTH-1:0] PORT_A2_WR_BE_i; +input PORT_A2_REN_i; +output [PORT_A2_DWIDTH-1:0] PORT_A2_RD_DATA_o; + +input PORT_B2_CLK_i; +input [PORT_B2_AWIDTH-1:0] PORT_B2_ADDR_i; +input [PORT_B2_DWIDTH-1:0] PORT_B2_WR_DATA_i; +input PORT_B2_WEN_i; +input [PORT_B2_WR_BE_WIDTH-1:0] PORT_B2_WR_BE_i; +input PORT_B2_REN_i; +output [PORT_B2_DWIDTH-1:0] PORT_B2_RD_DATA_o; + + +// Fixed mode settings +localparam [ 0:0] SYNC_FIFO1_i = 1'd0; +localparam [ 0:0] FMODE1_i = 1'd0; +localparam [ 0:0] POWERDN1_i = 1'd0; +localparam [ 0:0] SLEEP1_i = 1'd0; +localparam [ 0:0] PROTECT1_i = 1'd0; +localparam [11:0] UPAE1_i = 12'd10; +localparam [11:0] UPAF1_i = 12'd10; + +localparam [ 0:0] SYNC_FIFO2_i = 1'd0; +localparam [ 0:0] FMODE2_i = 1'd0; +localparam [ 0:0] POWERDN2_i = 1'd0; +localparam [ 0:0] SLEEP2_i = 1'd0; +localparam [ 0:0] PROTECT2_i = 1'd0; +localparam [10:0] UPAE2_i = 11'd10; +localparam [10:0] UPAF2_i = 11'd10; + +// Width mode function +function [2:0] mode; +input integer width; +case (width) +1: mode = 3'b101; +2: mode = 3'b110; +4: mode = 3'b100; +8,9: mode = 3'b001; +16, 18: mode = 3'b010; +32, 36: mode = 3'b011; +default: mode = 3'b000; +endcase +endfunction + +function integer rwmode; +input integer rwwidth; +case (rwwidth) +1: rwmode = 1; +2: rwmode = 2; +4: rwmode = 4; +8,9: rwmode = 9; +16, 18: rwmode = 18; +default: rwmode = 18; +endcase +endfunction + +wire REN_A1_i; +wire REN_A2_i; + +wire REN_B1_i; +wire REN_B2_i; + +wire WEN_A1_i; +wire WEN_A2_i; + +wire WEN_B1_i; +wire WEN_B2_i; + +wire [1:0] BE_A1_i; +wire [1:0] BE_A2_i; + +wire [1:0] BE_B1_i; +wire [1:0] BE_B2_i; + +wire [14:0] ADDR_A1_i; +wire [13:0] ADDR_A2_i; + +wire [14:0] ADDR_B1_i; +wire [13:0] ADDR_B2_i; + +wire [17:0] WDATA_A1_i; +wire [17:0] WDATA_A2_i; + +wire [17:0] WDATA_B1_i; +wire [17:0] WDATA_B2_i; + +wire [17:0] RDATA_A1_o; +wire [17:0] RDATA_A2_o; + +wire [17:0] RDATA_B1_o; +wire [17:0] RDATA_B2_o; + +wire [1:0] PORT_A1_WR_BE; +wire [1:0] PORT_B1_WR_BE; + +wire [1:0] PORT_A2_WR_BE; +wire [1:0] PORT_B2_WR_BE; + +wire [17:0] PORT_B1_WDATA; +wire [17:0] PORT_B1_RDATA; +wire [17:0] PORT_A1_WDATA; +wire [17:0] PORT_A1_RDATA; + +wire [17:0] PORT_B2_WDATA; +wire [17:0] PORT_B2_RDATA; +wire [17:0] PORT_A2_WDATA; +wire [17:0] PORT_A2_RDATA; + +wire [13:0] PORT_A1_ADDR_INT; +wire [13:0] PORT_B1_ADDR_INT; + +wire [13:0] PORT_A2_ADDR_INT; +wire [13:0] PORT_B2_ADDR_INT; + +wire [13:0] PORT_A1_ADDR; +wire [13:0] PORT_B1_ADDR; + +wire [13:0] PORT_A2_ADDR; +wire [13:0] PORT_B2_ADDR; + +wire PORT_A1_CLK; +wire PORT_B1_CLK; + +wire PORT_A2_CLK; +wire PORT_B2_CLK; + +// Set port width mode (In non-split mode A2/B2 is not active. Set same values anyway to match previous behavior.) +localparam [ 2:0] RMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] WMODE_A1_i = mode(PORT_A1_DWIDTH); +localparam [ 2:0] RMODE_A2_i = mode(PORT_A2_DWIDTH); +localparam [ 2:0] WMODE_A2_i = mode(PORT_A2_DWIDTH); + +localparam [ 2:0] RMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] WMODE_B1_i = mode(PORT_B1_DWIDTH); +localparam [ 2:0] RMODE_B2_i = mode(PORT_B2_DWIDTH); +localparam [ 2:0] WMODE_B2_i = mode(PORT_B2_DWIDTH); + +localparam PORT_A1_WRWIDTH = rwmode(PORT_A1_DWIDTH); +localparam PORT_B1_WRWIDTH = rwmode(PORT_B1_DWIDTH); +localparam PORT_A2_WRWIDTH = rwmode(PORT_A2_DWIDTH); +localparam PORT_B2_WRWIDTH = rwmode(PORT_B2_DWIDTH); + +assign PORT_A1_CLK = PORT_A1_CLK_i; +assign PORT_B1_CLK = PORT_B1_CLK_i; + +assign PORT_A2_CLK = PORT_A2_CLK_i; +assign PORT_B2_CLK = PORT_B2_CLK_i; + +generate + if (PORT_A1_AWIDTH == 14) begin + assign PORT_A1_ADDR_INT = PORT_A1_ADDR_i; + end else begin + assign PORT_A1_ADDR_INT[13:PORT_A1_AWIDTH] = 0; + assign PORT_A1_ADDR_INT[PORT_A1_AWIDTH-1:0] = PORT_A1_ADDR_i; + end +endgenerate + +case (PORT_A1_DWIDTH) + 1: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end + 2: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 1; + end + 4: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT << 4; + end + default: begin + assign PORT_A1_ADDR = PORT_A1_ADDR_INT; + end +endcase + +generate + if (PORT_B1_AWIDTH == 14) begin + assign PORT_B1_ADDR_INT = PORT_B1_ADDR_i; + end else begin + assign PORT_B1_ADDR_INT[13:PORT_B1_AWIDTH] = 0; + assign PORT_B1_ADDR_INT[PORT_B1_AWIDTH-1:0] = PORT_B1_ADDR_i; + end +endgenerate + +case (PORT_B1_DWIDTH) + 1: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end + 2: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 1; + end + 4: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT << 4; + end + default: begin + assign PORT_B1_ADDR = PORT_B1_ADDR_INT; + end +endcase + +generate + if (PORT_A2_AWIDTH == 14) begin + assign PORT_A2_ADDR_INT = PORT_A2_ADDR_i; + end else begin + assign PORT_A2_ADDR_INT[13:PORT_A2_AWIDTH] = 0; + assign PORT_A2_ADDR_INT[PORT_A2_AWIDTH-1:0] = PORT_A2_ADDR_i; + end +endgenerate + +case (PORT_A2_DWIDTH) + 1: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end + 2: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 1; + end + 4: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT << 4; + end + default: begin + assign PORT_A2_ADDR = PORT_A2_ADDR_INT; + end +endcase + +generate + if (PORT_B2_AWIDTH == 14) begin + assign PORT_B2_ADDR_INT = PORT_B2_ADDR_i; + end else begin + assign PORT_B2_ADDR_INT[13:PORT_B2_AWIDTH] = 0; + assign PORT_B2_ADDR_INT[PORT_B2_AWIDTH-1:0] = PORT_B2_ADDR_i; + end +endgenerate + +case (PORT_B2_DWIDTH) + 1: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end + 2: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 1; + end + 4: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 2; + end + 8, 9: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 3; + end + 16, 18: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT << 4; + end + default: begin + assign PORT_B2_ADDR = PORT_B2_ADDR_INT; + end +endcase + +case (PORT_A1_WR_BE_WIDTH) + 2: begin + assign PORT_A1_WR_BE = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A1_WR_BE[1:PORT_A1_WR_BE_WIDTH] = 0; + assign PORT_A1_WR_BE[PORT_A1_WR_BE_WIDTH-1 :0] = PORT_A1_WR_BE_i[PORT_A1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B1_WR_BE_WIDTH) + 2: begin + assign PORT_B1_WR_BE = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B1_WR_BE[1:PORT_B1_WR_BE_WIDTH] = 0; + assign PORT_B1_WR_BE[PORT_B1_WR_BE_WIDTH-1 :0] = PORT_B1_WR_BE_i[PORT_B1_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_A2_WR_BE_WIDTH) + 2: begin + assign PORT_A2_WR_BE = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_A2_WR_BE[1:PORT_A2_WR_BE_WIDTH] = 0; + assign PORT_A2_WR_BE[PORT_A2_WR_BE_WIDTH-1 :0] = PORT_A2_WR_BE_i[PORT_A2_WR_BE_WIDTH-1 :0]; + end +endcase + +case (PORT_B2_WR_BE_WIDTH) + 2: begin + assign PORT_B2_WR_BE = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end + default: begin + assign PORT_B2_WR_BE[1:PORT_B2_WR_BE_WIDTH] = 0; + assign PORT_B2_WR_BE[PORT_B2_WR_BE_WIDTH-1 :0] = PORT_B2_WR_BE_i[PORT_B2_WR_BE_WIDTH-1 :0]; + end +endcase + +assign REN_A1_i = PORT_A1_REN_i; +assign WEN_A1_i = PORT_A1_WEN_i; +assign BE_A1_i = PORT_A1_WR_BE; + +assign REN_A2_i = PORT_A2_REN_i; +assign WEN_A2_i = PORT_A2_WEN_i; +assign BE_A2_i = PORT_A2_WR_BE; + +assign REN_B1_i = PORT_B1_REN_i; +assign WEN_B1_i = PORT_B1_WEN_i; +assign BE_B1_i = PORT_B1_WR_BE; + +assign REN_B2_i = PORT_B2_REN_i; +assign WEN_B2_i = PORT_B2_WEN_i; +assign BE_B2_i = PORT_B2_WR_BE; + +generate + if (PORT_A1_DWIDTH == 18) begin + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end else if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_WDATA = {1'b0, PORT_A1_WR_DATA_i[8], 8'h0, PORT_A1_WR_DATA_i[7:0]}; + end else begin + assign PORT_A1_WDATA[17:PORT_A1_DWIDTH] = 0; + assign PORT_A1_WDATA[PORT_A1_DWIDTH-1:0] = PORT_A1_WR_DATA_i[PORT_A1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A1_i = PORT_A1_WDATA; + +generate + if (PORT_A2_DWIDTH == 18) begin + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end else if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_WDATA = {1'b0, PORT_A2_WR_DATA_i[8], 8'h0, PORT_A2_WR_DATA_i[7:0]}; + end else begin + assign PORT_A2_WDATA[17:PORT_A2_DWIDTH] = 0; + assign PORT_A2_WDATA[PORT_A2_DWIDTH-1:0] = PORT_A2_WR_DATA_i[PORT_A2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_A2_i = PORT_A2_WDATA; + +generate + if (PORT_A1_DWIDTH == 9) begin + assign PORT_A1_RDATA = { 9'h0, RDATA_A1_o[16], RDATA_A1_o[7:0]}; + end else begin + assign PORT_A1_RDATA = RDATA_A1_o; + end +endgenerate + +assign PORT_A1_RD_DATA_o = PORT_A1_RDATA[PORT_A1_DWIDTH-1:0]; + +generate + if (PORT_A2_DWIDTH == 9) begin + assign PORT_A2_RDATA = { 9'h0, RDATA_A2_o[16], RDATA_A2_o[7:0]}; + end else begin + assign PORT_A2_RDATA = RDATA_A2_o; + end +endgenerate + +assign PORT_A2_RD_DATA_o = PORT_A2_RDATA[PORT_A2_DWIDTH-1:0]; + +generate + if (PORT_B1_DWIDTH == 18) begin + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end else if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_WDATA = {1'b0, PORT_B1_WR_DATA_i[8], 8'h0, PORT_B1_WR_DATA_i[7:0]}; + end else begin + assign PORT_B1_WDATA[17:PORT_B1_DWIDTH] = 0; + assign PORT_B1_WDATA[PORT_B1_DWIDTH-1:0] = PORT_B1_WR_DATA_i[PORT_B1_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B1_i = PORT_B1_WDATA; + +generate + if (PORT_B2_DWIDTH == 18) begin + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end else if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_WDATA = {1'b0, PORT_B2_WR_DATA_i[8], 8'h0, PORT_B2_WR_DATA_i[7:0]}; + end else begin + assign PORT_B2_WDATA[17:PORT_B2_DWIDTH] = 0; + assign PORT_B2_WDATA[PORT_B2_DWIDTH-1:0] = PORT_B2_WR_DATA_i[PORT_B2_DWIDTH-1:0]; + end +endgenerate + +assign WDATA_B2_i = PORT_B2_WDATA; + +generate + if (PORT_B1_DWIDTH == 9) begin + assign PORT_B1_RDATA = { 9'h0, RDATA_B1_o[16], RDATA_B1_o[7:0]}; + end else begin + assign PORT_B1_RDATA = RDATA_B1_o; + end +endgenerate + +assign PORT_B1_RD_DATA_o = PORT_B1_RDATA[PORT_B1_DWIDTH-1:0]; + +generate + if (PORT_B2_DWIDTH == 9) begin + assign PORT_B2_RDATA = { 9'h0, RDATA_B2_o[16], RDATA_B2_o[7:0]}; + end else begin + assign PORT_B2_RDATA = RDATA_B2_o; + end +endgenerate + +assign PORT_B2_RD_DATA_o = PORT_B2_RDATA[PORT_B2_DWIDTH-1:0]; + +defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i +}; + +(* is_inferred = 0 *) +(* is_split = 0 *) +(* is_fifo = 0 *) +(* port_a_dwidth = PORT_A1_WRWIDTH *) +(* port_b_dwidth = PORT_B1_WRWIDTH *) +TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + + .CLK_A1_i(PORT_A1_CLK), + .ADDR_A1_i({1'b0,PORT_A1_ADDR}), + .WEN_A1_i(WEN_A1_i), + .BE_A1_i(BE_A1_i), + .WDATA_A1_i(WDATA_A1_i), + .REN_A1_i(REN_A1_i), + .RDATA_A1_o(RDATA_A1_o), + + .CLK_A2_i(PORT_A2_CLK), + .ADDR_A2_i(PORT_A2_ADDR), + .WEN_A2_i(WEN_A2_i), + .BE_A2_i(BE_A2_i), + .WDATA_A2_i(WDATA_A2_i), + .REN_A2_i(REN_A2_i), + .RDATA_A2_o(RDATA_A2_o), + + .CLK_B1_i(PORT_B1_CLK), + .ADDR_B1_i({1'b0,PORT_B1_ADDR}), + .WEN_B1_i(WEN_B1_i), + .BE_B1_i(BE_B1_i), + .WDATA_B1_i(WDATA_B1_i), + .REN_B1_i(REN_B1_i), + .RDATA_B1_o(RDATA_B1_o), + + .CLK_B2_i(PORT_B2_CLK), + .ADDR_B2_i(PORT_B2_ADDR), + .WEN_B2_i(WEN_B2_i), + .BE_B2_i(BE_B2_i), + .WDATA_B2_i(WDATA_B2_i), + .REN_B2_i(REN_B2_i), + .RDATA_B2_o(RDATA_B2_o), + + .FLUSH1_i(1'b0), + .FLUSH2_i(1'b0) +); + +endmodule + + +module BRAM2x18_SFIFO ( + DIN1, + PUSH1, + POP1, + CLK1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + CLK2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input CLK1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input CLK2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd1; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd1; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + assign Push_Clk1 = CLK1; + assign Pop_Clk1 = CLK1; + assign Push_Clk2 = CLK2; + assign Pop_Clk2 = CLK2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 1 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + +endmodule + + +module BRAM2x18_AFIFO ( + DIN1, + PUSH1, + POP1, + Push_Clk1, + Pop_Clk1, + Async_Flush1, + Overrun_Error1, + Full_Watermark1, + Almost_Full1, + Full1, + Underrun_Error1, + Empty_Watermark1, + Almost_Empty1, + Empty1, + DOUT1, + + DIN2, + PUSH2, + POP2, + Push_Clk2, + Pop_Clk2, + Async_Flush2, + Overrun_Error2, + Full_Watermark2, + Almost_Full2, + Full2, + Underrun_Error2, + Empty_Watermark2, + Almost_Empty2, + Empty2, + DOUT2 +); + + parameter WR1_DATA_WIDTH = 18; + parameter RD1_DATA_WIDTH = 18; + + parameter WR2_DATA_WIDTH = 18; + parameter RD2_DATA_WIDTH = 18; + + parameter UPAE_DBITS1 = 12'd10; + parameter UPAF_DBITS1 = 12'd10; + + parameter UPAE_DBITS2 = 11'd10; + parameter UPAF_DBITS2 = 11'd10; + + input Push_Clk1, Pop_Clk1; + input PUSH1, POP1; + input [WR1_DATA_WIDTH-1:0] DIN1; + input Async_Flush1; + output [RD1_DATA_WIDTH-1:0] DOUT1; + output Almost_Full1, Almost_Empty1; + output Full1, Empty1; + output Full_Watermark1, Empty_Watermark1; + output Overrun_Error1, Underrun_Error1; + + input Push_Clk2, Pop_Clk2; + input PUSH2, POP2; + input [WR2_DATA_WIDTH-1:0] DIN2; + input Async_Flush2; + output [RD2_DATA_WIDTH-1:0] DOUT2; + output Almost_Full2, Almost_Empty2; + output Full2, Empty2; + output Full_Watermark2, Empty_Watermark2; + output Overrun_Error2, Underrun_Error2; + + // Fixed mode settings + localparam [ 0:0] SYNC_FIFO1_i = 1'd0; + localparam [ 0:0] FMODE1_i = 1'd1; + localparam [ 0:0] POWERDN1_i = 1'd0; + localparam [ 0:0] SLEEP1_i = 1'd0; + localparam [ 0:0] PROTECT1_i = 1'd0; + localparam [11:0] UPAE1_i = UPAE_DBITS1; + localparam [11:0] UPAF1_i = UPAF_DBITS1; + + localparam [ 0:0] SYNC_FIFO2_i = 1'd0; + localparam [ 0:0] FMODE2_i = 1'd1; + localparam [ 0:0] POWERDN2_i = 1'd0; + localparam [ 0:0] SLEEP2_i = 1'd0; + localparam [ 0:0] PROTECT2_i = 1'd0; + localparam [10:0] UPAE2_i = UPAE_DBITS2; + localparam [10:0] UPAF2_i = UPAF_DBITS2; + + // Width mode function + function [2:0] mode; + input integer width; + case (width) + 1: mode = 3'b101; + 2: mode = 3'b110; + 4: mode = 3'b100; + 8,9: mode = 3'b001; + 16, 18: mode = 3'b010; + 32, 36: mode = 3'b011; + default: mode = 3'b000; + endcase + endfunction + + function integer rwmode; + input integer rwwidth; + case (rwwidth) + 1: rwmode = 1; + 2: rwmode = 2; + 4: rwmode = 4; + 8,9: rwmode = 9; + 16, 18: rwmode = 18; + default: rwmode = 18; + endcase + endfunction + + wire [17:0] in_reg1; + wire [17:0] out_reg1; + wire [17:0] fifo1_flags; + + wire [17:0] in_reg2; + wire [17:0] out_reg2; + wire [17:0] fifo2_flags; + + wire Push_Clk1, Pop_Clk1; + wire Push_Clk2, Pop_Clk2; + + assign Overrun_Error1 = fifo1_flags[0]; + assign Full_Watermark1 = fifo1_flags[1]; + assign Almost_Full1 = fifo1_flags[2]; + assign Full1 = fifo1_flags[3]; + assign Underrun_Error1 = fifo1_flags[4]; + assign Empty_Watermark1 = fifo1_flags[5]; + assign Almost_Empty1 = fifo1_flags[6]; + assign Empty1 = fifo1_flags[7]; + + assign Overrun_Error2 = fifo2_flags[0]; + assign Full_Watermark2 = fifo2_flags[1]; + assign Almost_Full2 = fifo2_flags[2]; + assign Full2 = fifo2_flags[3]; + assign Underrun_Error2 = fifo2_flags[4]; + assign Empty_Watermark2 = fifo2_flags[5]; + assign Almost_Empty2 = fifo2_flags[6]; + assign Empty2 = fifo2_flags[7]; + + localparam [ 2:0] RMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] WMODE_A1_i = mode(WR1_DATA_WIDTH); + localparam [ 2:0] RMODE_A2_i = mode(WR2_DATA_WIDTH); + localparam [ 2:0] WMODE_A2_i = mode(WR2_DATA_WIDTH); + + localparam [ 2:0] RMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] WMODE_B1_i = mode(RD1_DATA_WIDTH); + localparam [ 2:0] RMODE_B2_i = mode(RD2_DATA_WIDTH); + localparam [ 2:0] WMODE_B2_i = mode(RD2_DATA_WIDTH); + + localparam PORT_A1_WRWIDTH = rwmode(WR1_DATA_WIDTH); + localparam PORT_B1_WRWIDTH = rwmode(RD1_DATA_WIDTH); + localparam PORT_A2_WRWIDTH = rwmode(WR2_DATA_WIDTH); + localparam PORT_B2_WRWIDTH = rwmode(RD2_DATA_WIDTH); + + generate + if (WR1_DATA_WIDTH == 18) begin + assign in_reg1[17:0] = DIN1[17:0]; + end else if (WR1_DATA_WIDTH == 9) begin + assign in_reg1[17:0] = {1'b0, DIN1[8], 8'h0, DIN1[7:0]}; + end else begin + assign in_reg1[17:WR1_DATA_WIDTH] = 0; + assign in_reg1[WR1_DATA_WIDTH-1:0] = DIN1[WR1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD1_DATA_WIDTH == 9) begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = {out_reg1[16], out_reg1[7:0]}; + end else begin + assign DOUT1[RD1_DATA_WIDTH-1:0] = out_reg1[RD1_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (WR2_DATA_WIDTH == 18) begin + assign in_reg2[17:0] = DIN2[17:0]; + end else if (WR2_DATA_WIDTH == 9) begin + assign in_reg2[17:0] = {1'b0, DIN2[8], 8'h0, DIN2[7:0]}; + end else begin + assign in_reg2[17:WR2_DATA_WIDTH] = 0; + assign in_reg2[WR2_DATA_WIDTH-1:0] = DIN2[WR2_DATA_WIDTH-1:0]; + end + endgenerate + + generate + if (RD2_DATA_WIDTH == 9) begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = {out_reg2[16], out_reg2[7:0]}; + end else begin + assign DOUT2[RD2_DATA_WIDTH-1:0] = out_reg2[RD2_DATA_WIDTH-1:0]; + end + endgenerate + + defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b1, + UPAF2_i, UPAE2_i, PROTECT2_i, SLEEP2_i, POWERDN2_i, FMODE2_i, WMODE_B2_i, WMODE_A2_i, RMODE_B2_i, RMODE_A2_i, SYNC_FIFO2_i, + UPAF1_i, UPAE1_i, PROTECT1_i, SLEEP1_i, POWERDN1_i, FMODE1_i, WMODE_B1_i, WMODE_A1_i, RMODE_B1_i, RMODE_A1_i, SYNC_FIFO1_i + }; + + (* is_fifo = 1 *) + (* sync_fifo = 0 *) + (* is_split = 0 *) + (* is_inferred = 0 *) + (* port_a_dwidth = PORT_A1_WRWIDTH *) + (* port_b_dwidth = PORT_B1_WRWIDTH *) + TDP36K _TECHMAP_REPLACE_ ( + .RESET_ni(1'b1), + .WDATA_A1_i(in_reg1[17:0]), + .WDATA_A2_i(in_reg2[17:0]), + .RDATA_A1_o(fifo1_flags), + .RDATA_A2_o(fifo2_flags), + .ADDR_A1_i(14'h0), + .ADDR_A2_i(14'h0), + .CLK_A1_i(Push_Clk1), + .CLK_A2_i(Push_Clk2), + .REN_A1_i(1'b1), + .REN_A2_i(1'b1), + .WEN_A1_i(PUSH1), + .WEN_A2_i(PUSH2), + .BE_A1_i(2'b11), + .BE_A2_i(2'b11), + + .WDATA_B1_i(18'h0), + .WDATA_B2_i(18'h0), + .RDATA_B1_o(out_reg1[17:0]), + .RDATA_B2_o(out_reg2[17:0]), + .ADDR_B1_i(14'h0), + .ADDR_B2_i(14'h0), + .CLK_B1_i(Pop_Clk1), + .CLK_B2_i(Pop_Clk2), + .REN_B1_i(POP1), + .REN_B2_i(POP2), + .WEN_B1_i(1'b0), + .WEN_B2_i(1'b0), + .BE_B1_i(2'b11), + .BE_B2_i(2'b11), + + .FLUSH1_i(Async_Flush1), + .FLUSH2_i(Async_Flush2) + ); + endmodule \ No newline at end of file diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 9692091909d..0a85749482e 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -263,7 +263,6 @@ struct SynthQuickLogicPass : public ScriptPass { run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); - run("techmap -map " + lib_path + family + "/brams_final_map.v"); if (bramTypes || help_mode) { run("ql_bram_types", "(if -bramtypes)"); From 4bb4fd358ebd3d0be60ca79d847b9927e98a4da3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Fri, 29 Sep 2023 14:31:06 +0200 Subject: [PATCH 06/39] ql_k6n10f: Remove support for parameter-configured DSP variety --- techlibs/quicklogic/ql_dsp_macc.cc | 40 +- techlibs/quicklogic/qlf_k6n10f/dsp_map.v | 123 +-- techlibs/quicklogic/qlf_k6n10f/dsp_sim.v | 1226 ---------------------- techlibs/quicklogic/synth_quicklogic.cc | 18 +- 4 files changed, 49 insertions(+), 1358 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index ca898d9d0c2..602fbf3cc1a 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -27,8 +27,6 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ -bool use_dsp_cfg_params; - static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) { auto &st = pm.st_ql_dsp_macc; @@ -122,11 +120,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) return; } - if (use_dsp_cfg_params) - cell_cfg_name = "_cfg_params"; - else - cell_cfg_name = "_cfg_ports"; - + cell_cfg_name = "_cfg_ports"; // TODO: remove cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; type = RTLIL::escape_id(cell_full_name); @@ -237,21 +231,12 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); // Connect config bits - if (use_dsp_cfg_params) { - cell->setParam(RTLIL::escape_id("SATURATE_ENABLE"), RTLIL::Const(RTLIL::S0)); - cell->setParam(RTLIL::escape_id("SHIFT_RIGHT"), RTLIL::Const(RTLIL::S0, 6)); - cell->setParam(RTLIL::escape_id("ROUND"), RTLIL::Const(RTLIL::S0)); - cell->setParam(RTLIL::escape_id("REGISTER_INPUTS"), RTLIL::Const(RTLIL::S0)); - // 3 - output post acc; 1 - output pre acc - cell->setParam(RTLIL::escape_id("OUTPUT_SELECT"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); - } else { - cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); - cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); - // 3 - output post acc; 1 - output pre acc - cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); - } + cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); bool subtract = (st.add->type == RTLIL::escape_id("$sub")); cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); @@ -274,25 +259,14 @@ struct QlDspMacc : public Pass { log("\n"); log(" ql_dsp_macc [options] [selection]\n"); log("\n"); - log(" -use_dsp_cfg_params\n"); - log(" By default use DSP blocks with configuration bits available at module ports.\n"); - log(" Specifying this forces usage of DSP block with configuration bits available as module parameters\n"); - log("\n"); } - void clear_flags() override { use_dsp_cfg_params = false; } - void execute(std::vector a_Args, RTLIL::Design *a_Design) override { log_header(a_Design, "Executing QL_DSP_MACC pass.\n"); size_t argidx; for (argidx = 1; argidx < a_Args.size(); argidx++) { - if (a_Args[argidx] == "-use_dsp_cfg_params") { - use_dsp_cfg_params = true; - continue; - } - break; } extra_args(a_Args, argidx, a_Design); diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v index bb9f05283e7..127145b71a9 100644 --- a/techlibs/quicklogic/qlf_k6n10f/dsp_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_map.v @@ -33,48 +33,25 @@ module \$__QL_MUL20X18 (input [19:0] A, input [17:0] B, output [37:0] Y); (B_SIGNED) ? {{(18 - B_WIDTH){B[B_WIDTH-1]}}, B} : {{(18 - B_WIDTH){1'b0}}, B}; - generate if (`USE_DSP_CFG_PARAMS == 0) begin - (* is_inferred=1 *) - dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .output_select_i (3'd0), - .saturate_enable_i (1'b0), - .shift_right_i (6'd0), - .round_i (1'b0), - .subtract_i (1'b0), - .register_inputs_i (1'b0) - ); - end else begin - (* is_inferred=1 *) - dsp_t1_20x18x64_cfg_params #( - .OUTPUT_SELECT (3'd0), - .SATURATE_ENABLE (1'b0), - .SHIFT_RIGHT (6'd0), - .ROUND (1'b0), - .REGISTER_INPUTS (1'b0) - ) TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .subtract_i (1'b0) - ); - end endgenerate + (* is_inferred=1 *) + dsp_t1_20x18x64_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); assign Y = z; @@ -99,48 +76,26 @@ module \$__QL_MUL10X9 (input [9:0] A, input [8:0] B, output [18:0] Y); (B_SIGNED) ? {{( 9 - B_WIDTH){B[B_WIDTH-1]}}, B} : {{( 9 - B_WIDTH){1'b0}}, B}; - generate if (`USE_DSP_CFG_PARAMS == 0) begin - (* is_inferred=1 *) - dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .output_select_i (3'd0), - .saturate_enable_i (1'b0), - .shift_right_i (6'd0), - .round_i (1'b0), - .subtract_i (1'b0), - .register_inputs_i (1'b0) - ); - end else begin - (* is_inferred=1 *) - dsp_t1_10x9x32_cfg_params #( - .OUTPUT_SELECT (3'd0), - .SATURATE_ENABLE (1'b0), - .SHIFT_RIGHT (6'd0), - .ROUND (1'b0), - .REGISTER_INPUTS (1'b0) - ) TECHMAP_REPLACE_ ( - .a_i (a), - .b_i (b), - .acc_fir_i (6'd0), - .z_o (z), - - .feedback_i (3'd0), - .load_acc_i (1'b0), - .unsigned_a_i (!A_SIGNED), - .unsigned_b_i (!B_SIGNED), - - .subtract_i (1'b0) - ); - end endgenerate + (* is_inferred=1 *) + dsp_t1_10x9x32_cfg_ports _TECHMAP_REPLACE_ ( + .a_i (a), + .b_i (b), + .acc_fir_i (6'd0), + .z_o (z), + + .feedback_i (3'd0), + .load_acc_i (1'b0), + .unsigned_a_i (!A_SIGNED), + .unsigned_b_i (!B_SIGNED), + + .output_select_i (3'd0), + .saturate_enable_i (1'b0), + .shift_right_i (6'd0), + .round_i (1'b0), + .subtract_i (1'b0), + .register_inputs_i (1'b0) + ); + assign Y = z; diff --git a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v index 05a4835e868..5f43b322912 100644 --- a/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v @@ -4525,1229 +4525,3 @@ module dsp_t1_sim_cfg_ports # ( dly_b_o <= b_i; endmodule - - - -// ---------------------------------------- // -// ----- DSP cells simulation modules ----- // -// ------ Control bits in parameters ------ // -// ---------------------------------------- // - -module QL_DSP3 ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - input wire [ 5:0] acc_fir, - output wire [37:0] z, - output wire [17:0] dly_b, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - localparam NBITS_ACC = 64; - localparam NBITS_A = 20; - localparam NBITS_B = 18; - localparam NBITS_Z = 38; - - // Fractured - generate if(F_MODE == 1'b1) begin - - wire [(NBITS_Z/2)-1:0] dsp_frac0_z; - wire [(NBITS_Z/2)-1:0] dsp_frac1_z; - - wire [(NBITS_B/2)-1:0] dsp_frac0_dly_b; - wire [(NBITS_B/2)-1:0] dsp_frac1_dly_b; - - dsp_t1_sim_cfg_params #( - .NBITS_A (NBITS_A/2), - .NBITS_B (NBITS_B/2), - .NBITS_ACC (NBITS_ACC/2), - .NBITS_Z (NBITS_Z/2), - .OUTPUT_SELECT (OUTPUT_SELECT), - .SATURATE_ENABLE (SATURATE_ENABLE), - .SHIFT_RIGHT (SHIFT_RIGHT), - .ROUND (ROUND), - .REGISTER_INPUTS (REGISTER_INPUTS) - ) dsp_frac0 ( - .a_i(a[(NBITS_A/2)-1:0]), - .b_i(b[(NBITS_B/2)-1:0]), - .z_o(dsp_frac0_z), - .dly_b_o(dsp_frac0_dly_b), - - .acc_fir_i(acc_fir), - .feedback_i(feedback), - .load_acc_i(load_acc), - - .unsigned_a_i(unsigned_a), - .unsigned_b_i(unsigned_b), - - .clock_i(clk), - .s_reset(reset), - - .subtract_i(subtract), - .coef_0_i(COEFF_0[(NBITS_A/2)-1:0]), - .coef_1_i(COEFF_1[(NBITS_A/2)-1:0]), - .coef_2_i(COEFF_2[(NBITS_A/2)-1:0]), - .coef_3_i(COEFF_3[(NBITS_A/2)-1:0]) - ); - - dsp_t1_sim_cfg_params #( - .NBITS_A (NBITS_A/2), - .NBITS_B (NBITS_B/2), - .NBITS_ACC (NBITS_ACC/2), - .NBITS_Z (NBITS_Z/2), - .OUTPUT_SELECT (OUTPUT_SELECT), - .SATURATE_ENABLE (SATURATE_ENABLE), - .SHIFT_RIGHT (SHIFT_RIGHT), - .ROUND (ROUND), - .REGISTER_INPUTS (REGISTER_INPUTS) - ) dsp_frac1 ( - .a_i(a[NBITS_A-1:NBITS_A/2]), - .b_i(b[NBITS_B-1:NBITS_B/2]), - .z_o(dsp_frac1_z), - .dly_b_o(dsp_frac1_dly_b), - .acc_fir_i(acc_fir), - .feedback_i(feedback), - .load_acc_i(load_acc), - - .unsigned_a_i(unsigned_a), - .unsigned_b_i(unsigned_b), - - .clock_i(clk), - .s_reset(reset), - - .subtract_i(subtract), - .coef_0_i(COEFF_0[NBITS_A-1:NBITS_A/2]), - .coef_1_i(COEFF_1[NBITS_A-1:NBITS_A/2]), - .coef_2_i(COEFF_2[NBITS_A-1:NBITS_A/2]), - .coef_3_i(COEFF_3[NBITS_A-1:NBITS_A/2]) - ); - - assign z = {dsp_frac1_z, dsp_frac0_z}; - assign dly_b = {dsp_frac1_dly_b, dsp_frac0_dly_b}; - - // Whole - end else begin - - dsp_t1_sim_cfg_params #( - .NBITS_A (NBITS_A), - .NBITS_B (NBITS_B), - .NBITS_ACC (NBITS_ACC), - .NBITS_Z (NBITS_Z), - .OUTPUT_SELECT (OUTPUT_SELECT), - .SATURATE_ENABLE (SATURATE_ENABLE), - .SHIFT_RIGHT (SHIFT_RIGHT), - .ROUND (ROUND), - .REGISTER_INPUTS (REGISTER_INPUTS) - ) dsp_full ( - .a_i(a), - .b_i(b), - .z_o(z), - .dly_b_o(dly_b), - - .acc_fir_i(acc_fir), - .feedback_i(feedback), - .load_acc_i(load_acc), - - .unsigned_a_i(unsigned_a), - .unsigned_b_i(unsigned_b), - - .clock_i(clk), - .s_reset(reset), - - .subtract_i(subtract), - .coef_0_i(COEFF_0), - .coef_1_i(COEFF_1), - .coef_2_i(COEFF_2), - .coef_3_i(COEFF_3) - ); - - end endgenerate - -endmodule - -module QL_DSP3_MULT ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - input wire reset, - - input wire [2:0] feedback, - input wire unsigned_a, - input wire unsigned_b -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .reset(reset), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b) - ); -endmodule - -module QL_DSP3_MULT_REGIN ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - - input wire unsigned_a, - input wire unsigned_b -); - - wire [37:0] dly_b_o; - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // unregistered output: a * b (0) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // registered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset) - ); -endmodule - -module QL_DSP3_MULT_REGOUT ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - - input wire unsigned_a, - input wire unsigned_b -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset) - ); -endmodule - -module QL_DSP3_MULT_REGIN_REGOUT ( // TODO: Name subject to change - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [2:0] feedback, - - input wire unsigned_a, - input wire unsigned_b -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; // registered output: a * b (4) - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; // unregistered inputs - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset) - ); -endmodule - -module QL_DSP3_MULTADD ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTADD_REGIN ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTADD_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTADD_REGIN_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire [ 5:0] acc_fir, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .acc_fir(acc_fir), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC_REGIN ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module QL_DSP3_MULTACC_REGIN_REGOUT ( - input wire [19:0] a, - input wire [17:0] b, - output wire [37:0] z, - - (* clkbuf_sink *) - input wire clk, - input wire reset, - - input wire [ 2:0] feedback, - input wire load_acc, - input wire unsigned_a, - input wire unsigned_b, - input wire subtract -); - - parameter [92:0] MODE_BITS = 93'b0; - - localparam [19:0] COEFF_0 = MODE_BITS[19:0]; - localparam [19:0] COEFF_1 = MODE_BITS[39:20]; - localparam [19:0] COEFF_2 = MODE_BITS[59:40]; - localparam [19:0] COEFF_3 = MODE_BITS[79:60]; - - localparam [0:0] F_MODE = MODE_BITS[80]; - localparam [2:0] OUTPUT_SELECT = MODE_BITS[83:81]; - localparam [0:0] SATURATE_ENABLE = MODE_BITS[84]; - localparam [5:0] SHIFT_RIGHT = MODE_BITS[90:85]; - localparam [0:0] ROUND = MODE_BITS[91]; - localparam [0:0] REGISTER_INPUTS = MODE_BITS[92]; - - QL_DSP3 #( - .MODE_BITS({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - F_MODE, - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a), - .b(b), - .z(z), - - .feedback(feedback), - .load_acc(load_acc), - - .unsigned_a(unsigned_a), - .unsigned_b(unsigned_b), - - .clk(clk), - .reset(reset), - .subtract(subtract) - ); -endmodule - -module dsp_t1_20x18x64_cfg_params ( - input wire [19:0] a_i, - input wire [17:0] b_i, - input wire [ 5:0] acc_fir_i, - output wire [37:0] z_o, - output wire [17:0] dly_b_o, - - (* clkbuf_sink *) - input wire clock_i, - input wire reset_i, - - input wire [ 2:0] feedback_i, - input wire load_acc_i, - input wire unsigned_a_i, - input wire unsigned_b_i, - input wire subtract_i -); - - parameter [19:0] COEFF_0 = 20'b0; - parameter [19:0] COEFF_1 = 20'b0; - parameter [19:0] COEFF_2 = 20'b0; - parameter [19:0] COEFF_3 = 20'b0; - - parameter [2:0] OUTPUT_SELECT = 3'b0; - parameter [0:0] SATURATE_ENABLE = 1'b0; - parameter [5:0] SHIFT_RIGHT = 6'b0; - parameter [0:0] ROUND = 1'b0; - parameter [0:0] REGISTER_INPUTS = 1'b0; - - QL_DSP3 #( - .MODE_BITS ({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - 1'b0, // Not fractured - COEFF_3, - COEFF_2, - COEFF_1, - COEFF_0 - }) - ) dsp ( - .a(a_i), - .b(b_i), - .z(z_o), - .dly_b(dly_b_o), - - .acc_fir(acc_fir_i), - .feedback(feedback_i), - .load_acc(load_acc_i), - - .unsigned_a(unsigned_a_i), - .unsigned_b(unsigned_b_i), - - .clk(clock_i), - .reset(reset_i), - .subtract(subtract_i) - ); -endmodule - -module dsp_t1_10x9x32_cfg_params ( - input wire [ 9:0] a_i, - input wire [ 8:0] b_i, - input wire [ 5:0] acc_fir_i, - output wire [18:0] z_o, - output wire [ 8:0] dly_b_o, - - (* clkbuf_sink *) - input wire clock_i, - input wire reset_i, - - input wire [ 2:0] feedback_i, - input wire load_acc_i, - input wire unsigned_a_i, - input wire unsigned_b_i, - input wire subtract_i -); - - parameter [9:0] COEFF_0 = 10'b0; - parameter [9:0] COEFF_1 = 10'b0; - parameter [9:0] COEFF_2 = 10'b0; - parameter [9:0] COEFF_3 = 10'b0; - - parameter [2:0] OUTPUT_SELECT = 3'b0; - parameter [0:0] SATURATE_ENABLE = 1'b0; - parameter [5:0] SHIFT_RIGHT = 6'b0; - parameter [0:0] ROUND = 1'b0; - parameter [0:0] REGISTER_INPUTS = 1'b0; - - wire [18:0] z_rem; - wire [8:0] dly_b_rem; - - QL_DSP3 #( - .MODE_BITS ({ - REGISTER_INPUTS, - ROUND, - SHIFT_RIGHT, - SATURATE_ENABLE, - OUTPUT_SELECT, - 1'b1, // Fractured - 10'd0, COEFF_3, - 10'd0, COEFF_2, - 10'd0, COEFF_1, - 10'd0, COEFF_0 - }) - ) dsp ( - .a({10'b0, a_i}), - .b({9'b0, b_i}), - .z({z_rem, z_o}), - .dly_b({dly_b_rem, dly_b_o}), - - .acc_fir(acc_fir_i), - .feedback(feedback_i), - .load_acc(load_acc_i), - - .unsigned_a(unsigned_a_i), - .unsigned_b(unsigned_b_i), - - .clk(clock_i), - .reset(reset_i), - .subtract(subtract_i) - ); -endmodule - -module dsp_t1_sim_cfg_params # ( - parameter NBITS_ACC = 64, - parameter NBITS_A = 20, - parameter NBITS_B = 18, - parameter NBITS_Z = 38, - - parameter [2:0] OUTPUT_SELECT = 3'b0, - parameter [0:0] SATURATE_ENABLE = 1'b0, - parameter [5:0] SHIFT_RIGHT = 6'b0, - parameter [0:0] ROUND = 1'b0, - parameter [0:0] REGISTER_INPUTS = 1'b0 -)( - input wire [NBITS_A-1:0] a_i, - input wire [NBITS_B-1:0] b_i, - output wire [NBITS_Z-1:0] z_o, - output reg [NBITS_B-1:0] dly_b_o, - - input wire [5:0] acc_fir_i, - input wire [2:0] feedback_i, - input wire load_acc_i, - - input wire unsigned_a_i, - input wire unsigned_b_i, - - input wire clock_i, - input wire s_reset, - - input wire subtract_i, - input wire [NBITS_A-1:0] coef_0_i, - input wire [NBITS_A-1:0] coef_1_i, - input wire [NBITS_A-1:0] coef_2_i, - input wire [NBITS_A-1:0] coef_3_i -); - -// FIXME: The version of Icarus Verilog from Conda seems not to recognize the -// $error macro. Disable this sanity check for now because of that. - - // Input registers - reg [NBITS_A-1:0] r_a; - reg [NBITS_B-1:0] r_b; - reg [5:0] r_acc_fir; - reg r_unsigned_a; - reg r_unsigned_b; - reg r_load_acc; - reg [2:0] r_feedback; - reg [5:0] r_shift_d1; - reg [5:0] r_shift_d2; - reg r_subtract; - reg r_sat; - reg r_rnd; - reg [NBITS_ACC-1:0] acc; - - initial begin - r_a <= 0; - r_b <= 0; - - r_acc_fir <= 0; - r_unsigned_a <= 0; - r_unsigned_b <= 0; - r_feedback <= 0; - r_shift_d1 <= 0; - r_shift_d2 <= 0; - r_subtract <= 0; - r_load_acc <= 0; - r_sat <= 0; - r_rnd <= 0; - end - - always @(posedge clock_i or posedge s_reset) begin - if (s_reset) begin - - r_a <= 'h0; - r_b <= 'h0; - - r_acc_fir <= 0; - r_unsigned_a <= 0; - r_unsigned_b <= 0; - r_feedback <= 0; - r_shift_d1 <= 0; - r_shift_d2 <= 0; - r_subtract <= 0; - r_load_acc <= 0; - r_sat <= 0; - r_rnd <= 0; - - end else begin - - r_a <= a_i; - r_b <= b_i; - - r_acc_fir <= acc_fir_i; - r_unsigned_a <= unsigned_a_i; - r_unsigned_b <= unsigned_b_i; - r_feedback <= feedback_i; - r_shift_d1 <= SHIFT_RIGHT; - r_shift_d2 <= r_shift_d1; - r_subtract <= subtract_i; - r_load_acc <= load_acc_i; - r_sat <= r_sat; - r_rnd <= r_rnd; - - end - end - - // Registered / non-registered input path select - wire [NBITS_A-1:0] a = REGISTER_INPUTS ? r_a : a_i; - wire [NBITS_B-1:0] b = REGISTER_INPUTS ? r_b : b_i; - - wire [5:0] acc_fir = REGISTER_INPUTS ? r_acc_fir : acc_fir_i; - wire unsigned_a = REGISTER_INPUTS ? r_unsigned_a : unsigned_a_i; - wire unsigned_b = REGISTER_INPUTS ? r_unsigned_b : unsigned_b_i; - wire [2:0] feedback = REGISTER_INPUTS ? r_feedback : feedback_i; - wire load_acc = REGISTER_INPUTS ? r_load_acc : load_acc_i; - wire subtract = REGISTER_INPUTS ? r_subtract : subtract_i; - wire sat = REGISTER_INPUTS ? r_sat : SATURATE_ENABLE; - wire rnd = REGISTER_INPUTS ? r_rnd : ROUND; - - // Shift right control - wire [5:0] shift_d1 = REGISTER_INPUTS ? r_shift_d1 : SHIFT_RIGHT; - wire [5:0] shift_d2 = OUTPUT_SELECT[1] ? shift_d1 : r_shift_d2; - - // Multiplier - wire unsigned_mode = unsigned_a & unsigned_b; - wire [NBITS_A-1:0] mult_a; - assign mult_a = (feedback == 3'h0) ? a : - (feedback == 3'h1) ? a : - (feedback == 3'h2) ? a : - (feedback == 3'h3) ? acc[NBITS_A-1:0] : - (feedback == 3'h4) ? coef_0_i : - (feedback == 3'h5) ? coef_1_i : - (feedback == 3'h6) ? coef_2_i : - coef_3_i; // if feedback == 3'h7 - - wire [NBITS_B-1:0] mult_b = (feedback == 2'h2) ? {NBITS_B{1'b0}} : b; - - wire [NBITS_A-1:0] mult_sgn_a = mult_a[NBITS_A-1]; - wire [NBITS_A-1:0] mult_mag_a = (mult_sgn_a && !unsigned_a) ? (~mult_a + 1) : mult_a; - wire [NBITS_B-1:0] mult_sgn_b = mult_b[NBITS_B-1]; - wire [NBITS_B-1:0] mult_mag_b = (mult_sgn_b && !unsigned_b) ? (~mult_b + 1) : mult_b; - - wire [NBITS_A+NBITS_B-1:0] mult_mag = mult_mag_a * mult_mag_b; - wire mult_sgn = (mult_sgn_a && !unsigned_a) ^ (mult_sgn_b && !unsigned_b); - - wire [NBITS_A+NBITS_B-1:0] mult = (unsigned_a && unsigned_b) ? - (mult_a * mult_b) : (mult_sgn ? (~mult_mag + 1) : mult_mag); - - // Sign extension - wire [NBITS_ACC-1:0] mult_xtnd = unsigned_mode ? - {{(NBITS_ACC-NBITS_A-NBITS_B){1'b0}}, mult[NBITS_A+NBITS_B-1:0]} : - {{(NBITS_ACC-NBITS_A-NBITS_B){mult[NBITS_A+NBITS_B-1]}}, mult[NBITS_A+NBITS_B-1:0]}; - - // Adder - wire [NBITS_ACC-1:0] acc_fir_int = unsigned_a ? {{(NBITS_ACC-NBITS_A){1'b0}}, a} : - {{(NBITS_ACC-NBITS_A){a[NBITS_A-1]}}, a} ; - - wire [NBITS_ACC-1:0] add_a = (subtract) ? (~mult_xtnd + 1) : mult_xtnd; - wire [NBITS_ACC-1:0] add_b = (feedback_i == 3'h0) ? acc : - (feedback_i == 3'h1) ? {{NBITS_ACC}{1'b0}} : (acc_fir_int << acc_fir); - - wire [NBITS_ACC-1:0] add_o = add_a + add_b; - - // Accumulator - initial acc <= 0; - - always @(posedge clock_i or posedge s_reset) - if (s_reset) acc <= 'h0; - else begin - if (load_acc) - acc <= add_o; - else - acc <= acc; - end - - // Adder/accumulator output selection - wire [NBITS_ACC-1:0] acc_out = (OUTPUT_SELECT[1]) ? add_o : acc; - - // Round, shift, saturate - wire [NBITS_ACC-1:0] acc_rnd = (rnd && (SHIFT_RIGHT != 0)) ? (acc_out + ({{(NBITS_ACC-1){1'b0}}, 1'b1} << (SHIFT_RIGHT - 1))) : - acc_out; - - wire [NBITS_ACC-1:0] acc_shr = (unsigned_mode) ? (acc_rnd >> SHIFT_RIGHT) : - (acc_rnd >>> SHIFT_RIGHT); - - wire [NBITS_ACC-1:0] acc_sat_u = (acc_shr[NBITS_ACC-1:NBITS_Z] != 0) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{NBITS_Z{1'b1}}} : - {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}}; - - wire [NBITS_ACC-1:0] acc_sat_s = ((|acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b0) || - (&acc_shr[NBITS_ACC-1:NBITS_Z-1] == 1'b1)) ? {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_Z-1:0]}} : - {{(NBITS_ACC-NBITS_Z){1'b0}},{acc_shr[NBITS_ACC-1],{NBITS_Z-1{~acc_shr[NBITS_ACC-1]}}}}; - - wire [NBITS_ACC-1:0] acc_sat = (sat) ? ((unsigned_mode) ? acc_sat_u : acc_sat_s) : acc_shr; - - // Output signals - wire [NBITS_Z-1:0] z0; - reg [NBITS_Z-1:0] z1; - wire [NBITS_Z-1:0] z2; - - assign z0 = mult_xtnd[NBITS_Z-1:0]; - assign z2 = acc_sat[NBITS_Z-1:0]; - - initial z1 <= 0; - - always @(posedge clock_i or posedge s_reset) - if (s_reset) - z1 <= 0; - else begin - z1 <= (OUTPUT_SELECT == 3'b100) ? z0 : z2; - end - - // Output mux - assign z_o = (OUTPUT_SELECT == 3'h0) ? z0 : - (OUTPUT_SELECT == 3'h1) ? z2 : - (OUTPUT_SELECT == 3'h2) ? z2 : - (OUTPUT_SELECT == 3'h3) ? z2 : - (OUTPUT_SELECT == 3'h4) ? z1 : - (OUTPUT_SELECT == 3'h5) ? z1 : - (OUTPUT_SELECT == 3'h6) ? z1 : - z1; // if OUTPUT_SELECT == 3'h7 - - // B input delayed passthrough - initial dly_b_o <= 0; - - always @(posedge clock_i or posedge s_reset) - if (s_reset) - dly_b_o <= 0; - else - dly_b_o <= b_i; - -endmodule diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 0a85749482e..101dff66597 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -50,11 +50,6 @@ struct SynthQuickLogicPass : public ScriptPass { log(" do not use dsp_t1_* to implement multipliers and associated logic\n"); log(" (qlf_k6n10f only).\n"); log("\n"); - log(" -use_dsp_cfg_params\n"); - log(" By default use DSP blocks with configuration bits available at module\n"); - log(" ports. Specifying this forces usage of DSP block with configuration\n"); - log(" bits available as module parameters.\n"); - log("\n"); log(" -nocarry\n"); log(" do not use adder_carry cells in output netlist.\n"); log("\n"); @@ -163,10 +158,6 @@ struct SynthQuickLogicPass : public ScriptPass { dsp = false; continue; } - if (args[argidx] == "-use_dsp_cfg_params") { - use_dsp_cfg_params = " -use_dsp_cfg_params"; - continue; - } break; } extra_args(args, argidx, design); @@ -231,16 +222,13 @@ struct SynthQuickLogicPass : public ScriptPass { if (check_label("map_dsp", "(for qlf_k6n10f, skip if -nodsp)") && ((dsp && family == "qlf_k6n10f") || help_mode)) { run("wreduce t:$mul"); - run("ql_dsp_macc" + use_dsp_cfg_params); + run("ql_dsp_macc"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18"); run("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9"); run("chtype -set $mul t:$__soft_mul"); - - if (use_dsp_cfg_params.empty()) - run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); - else - run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=1"); + + run("techmap -map " + lib_path + family + "/dsp_map.v -D USE_DSP_CFG_PARAMS=0"); run("ql_dsp_simd"); run("techmap -map " + lib_path + family + "/dsp_final_map.v"); run("ql_dsp_io_regs"); From 7d738b07dacd4c73e82966dc0053862c4b31973a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 2 Oct 2023 14:40:10 +0200 Subject: [PATCH 07/39] ql_dsp_*: Clean up Clean up the code up to Yosys standards. Drop detection of QL_DSP2_MULTADD in io_regs since those cells can't be inferred with the current flow anyway. --- techlibs/quicklogic/ql_dsp_io_regs.cc | 252 +++++++++----------------- techlibs/quicklogic/ql_dsp_simd.cc | 233 ++++++++---------------- 2 files changed, 157 insertions(+), 328 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc index 217a5aa5573..efb1ad4d5f3 100644 --- a/techlibs/quicklogic/ql_dsp_io_regs.cc +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -30,26 +30,24 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ struct QlDspIORegs : public Pass { - - const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b"}; + const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b", + "saturate_enable", "shift_right", "round"}; const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; - const std::vector ports2del_mult_add = {"dly_b"}; - const std::vector ports2del_extension = {"saturate_enable", "shift_right", "round"}; - /// Temporary SigBit to SigBit helper map. - SigMap m_SigMap; + SigMap sigmap; // .......................................... - QlDspIORegs() : Pass("ql_dsp_io_regs", "Changes types of QL_DSP2/QL_DSP3 depending on their configuration.") {} + QlDspIORegs() : Pass("ql_dsp_io_regs", "change types of QL_DSP2 depending on configuration") {} void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" ql_dsp_io_regs [options] [selection]\n"); log("\n"); - log("Looks for QL_DSP2/QL_DSP3 cells and changes their types depending\n"); - log("on their configuration.\n"); + log("This pass looks for QL_DSP2 cells and changes their cell type depending on their\n"); + log("configuration.\n"); } void execute(std::vector a_Args, RTLIL::Design *a_Design) override @@ -67,178 +65,92 @@ struct QlDspIORegs : public Pass { } } - // Returns a pair of mask and value describing constant bit connections of - // a SigSpec - std::pair get_constant_mask_value(const RTLIL::SigSpec *sigspec) - { - uint32_t mask = 0L; - uint32_t value = 0L; - - auto sigbits = sigspec->bits(); - for (ssize_t i = (sigbits.size() - 1); i >= 0; --i) { - auto other = m_SigMap(sigbits[i]); - - mask <<= 1; - value <<= 1; - - // A known constant - if (!other.is_wire() && other.data != RTLIL::Sx) { - mask |= 0x1; - value |= (other.data == RTLIL::S1); - } - } - - return std::make_pair(mask, value); - } - void ql_dsp_io_regs_pass(RTLIL::Module *module) { - // Setup the SigMap - m_SigMap.clear(); - m_SigMap.set(module); - - for (auto cell : module->cells_) { - std::string cell_type = cell.second->type.str(); - if (cell_type == RTLIL::escape_id("QL_DSP2") || cell_type == RTLIL::escape_id("QL_DSP3")) { - auto dsp = cell.second; - - // If the cell does not have the "is_inferred" attribute set - // then don't touch it. - if (!dsp->has_attribute(RTLIL::escape_id("is_inferred")) || dsp->get_bool_attribute(RTLIL::escape_id("is_inferred")) == false) { - continue; - } - - bool del_clk = true; - bool use_dsp_cfg_params = (cell_type == RTLIL::escape_id("QL_DSP3")); - - int reg_in_i; - int out_sel_i; - - // Get DSP configuration - if (use_dsp_cfg_params) { - // Read MODE_BITS at correct indexes - auto mode_bits = &dsp->getParam(RTLIL::escape_id("MODE_BITS")); - RTLIL::Const register_inputs; - register_inputs = mode_bits->bits.at(MODE_BITS_REGISTER_INPUTS_ID); - reg_in_i = register_inputs.as_int(); - - RTLIL::Const output_select; - output_select = mode_bits->extract(MODE_BITS_OUTPUT_SELECT_START_ID, MODE_BITS_OUTPUT_SELECT_WIDTH); - out_sel_i = output_select.as_int(); - } else { - // Read dedicated configuration ports - const RTLIL::SigSpec *register_inputs; - register_inputs = &dsp->getPort(RTLIL::escape_id("register_inputs")); - if (!register_inputs) - log_error("register_inputs port not found!"); - auto reg_in_c = register_inputs->as_const(); - reg_in_i = reg_in_c.as_int(); - - const RTLIL::SigSpec *output_select; - output_select = &dsp->getPort(RTLIL::escape_id("output_select")); - if (!output_select) - log_error("output_select port not found!"); - auto out_sel_c = output_select->as_const(); - out_sel_i = out_sel_c.as_int(); - } - - // Get the feedback port - const RTLIL::SigSpec *feedback; - feedback = &dsp->getPort(RTLIL::escape_id("feedback")); - if (!feedback) - log_error("feedback port not found!"); - - // Check if feedback is or can be set to 0 which implies MACC - auto feedback_con = get_constant_mask_value(feedback); - bool have_macc = (feedback_con.second == 0x0); - // log("mask=0x%08X value=0x%08X\n", consts.first, consts.second); - // log_error("=== END HERE ===\n"); - - // Build new type name - std::string new_type = cell_type; - new_type += "_MULT"; - - if (have_macc) { - switch (out_sel_i) { - case 1: - case 2: - case 3: - case 5: - case 7: - del_clk = false; - new_type += "ACC"; - break; - default: - break; - } - } else { - switch (out_sel_i) { - case 1: - case 2: - case 3: - case 5: - case 7: - new_type += "ADD"; - break; - default: - break; - } - } - - if (reg_in_i) { - del_clk = false; - new_type += "_REGIN"; - } - - if (out_sel_i > 3) { - del_clk = false; - new_type += "_REGOUT"; - } - - // Set new type name - dsp->type = RTLIL::IdString(new_type); - - std::vector ports2del; - - if (del_clk) - ports2del.push_back("clk"); - - switch (out_sel_i) { - case 0: - case 4: - case 6: - ports2del.insert(ports2del.end(), ports2del_mult.begin(), ports2del_mult.end()); - // Mark for deleton additional configuration ports - if (!use_dsp_cfg_params) { - ports2del.insert(ports2del.end(), ports2del_extension.begin(), ports2del_extension.end()); - } - break; + sigmap.set(module); + + for (auto cell : module->cells()) { + if (cell->type != ID(QL_DSP2)) + continue; + + // If the cell does not have the "is_inferred" attribute set + // then don't touch it. + if (!cell->get_bool_attribute(ID(is_inferred))) + continue; + + // Get DSP configuration + for (auto cfg_port : {ID(register_inputs), ID(output_select)}) + if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const()) + log_error("Missing or non-constant '%s' port on DSP cell %s\n", + log_id(cfg_port), log_id(cell)); + int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); + int out_sel_i = sigmap(cell->getPort(ID(output_select))).as_int(); + + // Get the feedback port + if (!cell->hasPort(ID(feedback))) + log_error("Missing 'feedback' port on %s", log_id(cell)); + SigSpec feedback = sigmap(cell->getPort(ID(feedback))); + + // Check the top two bits on 'feedback' to be constant zero. + // That's what we are expecting from inference. + if (feedback.extract(1, 2) != SigSpec(0, 2)) + log_error("Unexpected feedback configuration on %s\n", log_id(cell)); + + // Build new type name + std::string new_type = "QL_DSP2_MULT"; + + // Decide if we should be deleting the clock port + bool del_clk = true; + + switch (out_sel_i) { case 1: case 2: case 3: case 5: case 7: - if (have_macc) { - ports2del.insert(ports2del.end(), ports2del_mult_acc.begin(), ports2del_mult_acc.end()); - } else { - ports2del.insert(ports2del.end(), ports2del_mult_add.begin(), ports2del_mult_add.end()); - } + del_clk = false; + new_type += "ACC"; + break; + default: break; - } - - for (auto portname : ports2del) { - const RTLIL::SigSpec *port = &dsp->getPort(RTLIL::escape_id(portname)); - if (!port) - log_error("%s port not found!", portname.c_str()); - dsp->connections_.erase(RTLIL::escape_id(portname)); - } } - } - // Clear the sigmap - m_SigMap.clear(); - } + if (reg_in_i) { + del_clk = false; + new_type += "_REGIN"; + } + + if (out_sel_i > 3) { + del_clk = false; + new_type += "_REGOUT"; + } + // Set new type name + cell->type = RTLIL::IdString(new_type); + + std::vector ports2del; + + if (del_clk) + cell->unsetPort(ID(clk)); + + switch (out_sel_i) { + case 0: + case 4: + case 6: + for (auto port : ports2del_mult) + cell->unsetPort(port); + break; + case 1: + case 2: + case 3: + case 5: + case 7: + for (auto port : ports2del_mult_acc) + cell->unsetPort(port); + break; + } + } + } } QlDspIORegs; PRIVATE_NAMESPACE_END diff --git a/techlibs/quicklogic/ql_dsp_simd.cc b/techlibs/quicklogic/ql_dsp_simd.cc index 5213aa1c4ac..153f3995f64 100644 --- a/techlibs/quicklogic/ql_dsp_simd.cc +++ b/techlibs/quicklogic/ql_dsp_simd.cc @@ -24,39 +24,30 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#define MODE_BITS_BASE_SIZE 80 -#define MODE_BITS_EXTENSION_SIZE 13 // ============================================================================ struct QlDspSimdPass : public Pass { - QlDspSimdPass() : Pass("ql_dsp_simd", "Infers QuickLogic k6n10f DSP pairs that can operate in SIMD mode") {} + QlDspSimdPass() : Pass("ql_dsp_simd", "merge QuickLogic K6N10f DSP pairs to operate in SIMD mode") {} void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); log(" ql_dsp_simd [selection]\n"); log("\n"); - log(" This pass identifies k6n10f DSP cells with identical configuration\n"); - log(" and packs pairs of them together into other DSP cells that can\n"); - log(" perform SIMD operation.\n"); + log("This pass identifies K6N10f DSP cells with identical configuration and pack pairs\n"); + log("of them together into other DSP cells that can perform SIMD operation.\n"); } // .......................................... /// Describes DSP config unique to a whole DSP cell struct DspConfig { - // Port connections dict connections; - // Whether DSPs pass configuration bits through ports of parameters - bool use_cfg_params; - - // TODO: Possibly include parameters here. For now we have just - // connections. - DspConfig() = default; DspConfig(const DspConfig &ref) = default; @@ -64,50 +55,50 @@ struct QlDspSimdPass : public Pass { unsigned int hash() const { return connections.hash(); } - bool operator==(const DspConfig &ref) const { return connections == ref.connections && use_cfg_params == ref.use_cfg_params; } + bool operator==(const DspConfig &ref) const { return connections == ref.connections; } }; // .......................................... // DSP control and config ports to consider and how to map them to ports // of the target DSP cell - const std::vector> m_DspCfgPorts = {std::make_pair("clock_i", "clk"), - std::make_pair("reset_i", "reset"), - - std::make_pair("feedback_i", "feedback"), - std::make_pair("load_acc_i", "load_acc"), - std::make_pair("unsigned_a_i", "unsigned_a"), - std::make_pair("unsigned_b_i", "unsigned_b"), - - std::make_pair("subtract_i", "subtract")}; - // For QL_DSP2 expand with configuration ports - const std::vector> m_DspCfgPorts_expand = { - std::make_pair("output_select_i", "output_select"), std::make_pair("saturate_enable_i", "saturate_enable"), - std::make_pair("shift_right_i", "shift_right"), std::make_pair("round_i", "round"), std::make_pair("register_inputs_i", "register_inputs")}; + const std::vector> m_DspCfgPorts = { + std::make_pair(ID(clock_i), ID(clk)), + std::make_pair(ID(reset_i), ID(reset)), + std::make_pair(ID(feedback_i), ID(feedback)), + std::make_pair(ID(load_acc_i), ID(load_acc)), + std::make_pair(ID(unsigned_a_i), ID(unsigned_a)), + std::make_pair(ID(unsigned_b_i), ID(unsigned_b)), + std::make_pair(ID(subtract_i), ID(subtract)), + std::make_pair(ID(output_select_i), ID(output_select)), + std::make_pair(ID(saturate_enable_i), ID(saturate_enable)), + std::make_pair(ID(shift_right_i), ID(shift_right)), + std::make_pair(ID(round_i), ID(round)), + std::make_pair(ID(register_inputs_i), ID(register_inputs)) + }; - // For QL_DSP3 use parameters instead - const std::vector m_DspParams2Mode = {"OUTPUT_SELECT", "SATURATE_ENABLE", "SHIFT_RIGHT", "ROUND", "REGISTER_INPUTS"}; + const int m_ModeBitsSize = 80; // DSP data ports and how to map them to ports of the target DSP cell - const std::vector> m_DspDataPorts = { - std::make_pair("a_i", "a"), std::make_pair("b_i", "b"), std::make_pair("acc_fir_i", "acc_fir"), - std::make_pair("z_o", "z"), std::make_pair("dly_b_o", "dly_b"), + const std::vector> m_DspDataPorts = { + std::make_pair(ID(a_i), ID(a)), + std::make_pair(ID(b_i), ID(b)), + std::make_pair(ID(acc_fir_i), ID(acc_fir)), + std::make_pair(ID(z_o), ID(z)), + std::make_pair(ID(dly_b_o), ID(dly_b)) }; // DSP parameters const std::vector m_DspParams = {"COEFF_3", "COEFF_2", "COEFF_1", "COEFF_0"}; // Source DSP cell type (SISD) - const std::string m_SisdDspType = "dsp_t1_10x9x32"; - // Suffix for DSP cell with configuration parameters - const std::string m_SisdDspType_cfg_params_suffix = "_cfg_params"; + const IdString m_SisdDspType = ID(dsp_t1_10x9x32); // Target DSP cell types for the SIMD mode - const std::string m_SimdDspType_cfg_ports = "QL_DSP2"; - const std::string m_SimdDspType_cfg_params = "QL_DSP3"; + const IdString m_SimdDspType = ID(QL_DSP2); /// Temporary SigBit to SigBit helper map. - SigMap m_SigMap; + SigMap sigmap; // .......................................... @@ -120,38 +111,32 @@ struct QlDspSimdPass : public Pass { // Process modules for (auto module : a_Design->selected_modules()) { - // Setup the SigMap - m_SigMap.clear(); - m_SigMap.set(module); + sigmap.set(module); // Assemble DSP cell groups dict> groups; for (auto cell : module->selected_cells()) { - // Check if this is a DSP cell we are looking for (type starts with m_SisdDspType) - if (strncmp(cell->type.c_str(), RTLIL::escape_id(m_SisdDspType).c_str(), RTLIL::escape_id(m_SisdDspType).size()) != 0) { + if (cell->type != m_SisdDspType) continue; - } // Skip if it has the (* keep *) attribute set - if (cell->has_keep_attr()) { + if (cell->has_keep_attr()) continue; - } // Add to a group const auto key = getDspConfig(cell); groups[key].push_back(cell); } - std::vector cellsToRemove; + std::vector cellsToRemove; // Map cell pairs to the target DSP SIMD cell for (const auto &it : groups) { const auto &group = it.second; const auto &config = it.first; - bool use_cfg_params = config.use_cfg_params; // Ensure an even number size_t count = group.size(); if (count & 1) @@ -159,66 +144,45 @@ struct QlDspSimdPass : public Pass { // Map SIMD pairs for (size_t i = 0; i < count; i += 2) { - const RTLIL::Cell *dsp_a = group[i]; - const RTLIL::Cell *dsp_b = group[i + 1]; - - std::string name = stringf("simd%ld", i / 2); - std::string SimdDspType; - - if (use_cfg_params) - SimdDspType = m_SimdDspType_cfg_params; - else - SimdDspType = m_SimdDspType_cfg_ports; - - log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", RTLIL::unescape_id(dsp_a->name).c_str(), RTLIL::unescape_id(dsp_a->type).c_str(), - RTLIL::unescape_id(dsp_b->name).c_str(), RTLIL::unescape_id(dsp_b->type).c_str(), RTLIL::unescape_id(name).c_str(), - SimdDspType.c_str()); + Cell *dsp_a = group[i]; + Cell *dsp_b = group[i + 1]; // Create the new cell - RTLIL::Cell *simd = module->addCell(RTLIL::escape_id(name), RTLIL::escape_id(SimdDspType)); + Cell *simd = module->addCell(NEW_ID, m_SimdDspType); + + log(" SIMD: %s (%s) + %s (%s) => %s (%s)\n", log_id(dsp_a), log_id(dsp_a->type), + log_id(dsp_b), log_id(dsp_b->type), log_id(simd), log_id(simd->type)); // Check if the target cell is known (important to know // its port widths) - if (!simd->known()) { - log_error(" The target cell type '%s' is not known!", SimdDspType.c_str()); - } - - std::vector> DspCfgPorts = m_DspCfgPorts; - if (!use_cfg_params) - DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); + if (!simd->known()) + log_error(" The target cell type '%s' is not known!", log_id(simd)); // Connect common ports - for (const auto &it : DspCfgPorts) { - auto sport = RTLIL::escape_id(it.first); - auto dport = RTLIL::escape_id(it.second); - - simd->setPort(dport, config.connections.at(sport)); - } + for (const auto &it : m_DspCfgPorts) + simd->setPort(it.first, config.connections.at(it.second)); // Connect data ports for (const auto &it : m_DspDataPorts) { - auto sport = RTLIL::escape_id(it.first); - auto dport = RTLIL::escape_id(it.second); - size_t width; bool isOutput; - std::tie(width, isOutput) = getPortInfo(simd, dport); + std::tie(width, isOutput) = getPortInfo(simd, it.second); auto getConnection = [&](const RTLIL::Cell *cell) { RTLIL::SigSpec sigspec; - if (cell->hasPort(sport)) { - const auto &sig = cell->getPort(sport); + if (cell->hasPort(it.first)) { + const auto &sig = cell->getPort(it.first); sigspec.append(sig); } - if (sigspec.bits().size() < width / 2) { - if (isOutput) { - for (size_t i = 0; i < width / 2 - sigspec.bits().size(); ++i) { - sigspec.append(RTLIL::SigSpec()); - } - } else { - sigspec.append(RTLIL::SigSpec(RTLIL::Sx, width / 2 - sigspec.bits().size())); - } + + int padding = width / 2 - sigspec.bits().size(); + + if (padding) { + if (!isOutput) + sigspec.append(RTLIL::SigSpec(RTLIL::Sx, padding)); + else + sigspec.append(module->addWire(NEW_ID, padding)); } return sigspec; }; @@ -226,49 +190,31 @@ struct QlDspSimdPass : public Pass { RTLIL::SigSpec sigspec; sigspec.append(getConnection(dsp_a)); sigspec.append(getConnection(dsp_b)); - simd->setPort(dport, sigspec); + simd->setPort(it.second, sigspec); } // Concatenate FIR coefficient parameters into the single // MODE_BITS parameter - std::vector mode_bits; + Const mode_bits; for (const auto &it : m_DspParams) { - auto val_a = dsp_a->getParam(RTLIL::escape_id(it)); - auto val_b = dsp_b->getParam(RTLIL::escape_id(it)); + auto val_a = dsp_a->getParam(it); + auto val_b = dsp_b->getParam(it); - mode_bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); - mode_bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); - } - long unsigned int mode_bits_size = MODE_BITS_BASE_SIZE; - if (use_cfg_params) { - // Add additional config parameters if necessary - mode_bits.push_back(RTLIL::S1); // MODE_BITS[80] == F_MODE : Enable fractured mode - for (const auto &it : m_DspParams2Mode) { - log_assert(dsp_a->getParam(RTLIL::escape_id(it)) == dsp_b->getParam(RTLIL::escape_id(it))); - auto param = dsp_a->getParam(RTLIL::escape_id(it)); - if (param.size() > 1) { - mode_bits.insert(mode_bits.end(), param.bits.begin(), param.bits.end()); - } else { - mode_bits.push_back(param.bits[0]); - } - } - mode_bits_size += MODE_BITS_EXTENSION_SIZE; - } else { - // Enable the fractured mode by connecting the control - // port. - simd->setPort(RTLIL::escape_id("f_mode"), RTLIL::S1); + mode_bits.bits.insert(mode_bits.end(), val_a.begin(), val_a.end()); + mode_bits.bits.insert(mode_bits.end(), val_b.begin(), val_b.end()); } - simd->setParam(RTLIL::escape_id("MODE_BITS"), RTLIL::Const(mode_bits)); - log_assert(mode_bits.size() == mode_bits_size); + + // Enable the fractured mode by connecting the control + // port. + simd->setPort(ID(f_mode), State::S1); + simd->setParam(ID(MODE_BITS), mode_bits); + log_assert(mode_bits.size() == m_ModeBitsSize); // Handle the "is_inferred" attribute. If one of the fragments // is not inferred mark the whole DSP as not inferred - bool is_inferred_a = - dsp_a->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_a->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; - bool is_inferred_b = - dsp_b->has_attribute(RTLIL::escape_id("is_inferred")) ? dsp_b->get_bool_attribute(RTLIL::escape_id("is_inferred")) : false; - - simd->set_bool_attribute(RTLIL::escape_id("is_inferred"), is_inferred_a && is_inferred_b); + bool is_inferred_a = dsp_a->get_bool_attribute(ID(is_inferred)); + bool is_inferred_b = dsp_b->get_bool_attribute(ID(is_inferred)); + simd->set_bool_attribute(ID(is_inferred), is_inferred_a && is_inferred_b); // Mark DSP parts for removal cellsToRemove.push_back(dsp_a); @@ -277,13 +223,9 @@ struct QlDspSimdPass : public Pass { } // Remove old cells - for (const auto &cell : cellsToRemove) { - module->remove(const_cast(cell)); - } + for (auto cell : cellsToRemove) + module->remove(cell); } - - // Clear - m_SigMap.clear(); } // .......................................... @@ -317,43 +259,18 @@ struct QlDspSimdPass : public Pass { { DspConfig config; - string cell_type = a_Cell->type.str(); - string suffix = m_SisdDspType_cfg_params_suffix; - - bool use_cfg_params = cell_type.size() >= suffix.size() && 0 == cell_type.compare(cell_type.size() - suffix.size(), suffix.size(), suffix); - - std::vector> DspCfgPorts = m_DspCfgPorts; - if (!use_cfg_params) - DspCfgPorts.insert(DspCfgPorts.end(), m_DspCfgPorts_expand.begin(), m_DspCfgPorts_expand.end()); - - config.use_cfg_params = use_cfg_params; - - for (const auto &it : DspCfgPorts) { - auto port = RTLIL::escape_id(it.first); + for (const auto &it : m_DspCfgPorts) { + auto port = it.first; // Port unconnected - if (!a_Cell->hasPort(port)) { - config.connections[port] = RTLIL::SigSpec(RTLIL::Sx); + if (!a_Cell->hasPort(port)) continue; - } - // Get the port connection and map it to unique SigBits - const auto &orgSigSpec = a_Cell->getPort(port); - const auto &orgSigBits = orgSigSpec.bits(); - - RTLIL::SigSpec newSigSpec; - for (size_t i = 0; i < orgSigBits.size(); ++i) { - auto newSigBit = m_SigMap(orgSigBits[i]); - newSigSpec.append(newSigBit); - } - - // Store - config.connections[port] = newSigSpec; + config.connections[port] = sigmap(a_Cell->getPort(port)); } return config; } - } QlDspSimdPass; PRIVATE_NAMESPACE_END From e43810e13f4dc344962df139adff5867914116b1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 2 Oct 2023 15:55:41 +0200 Subject: [PATCH 08/39] ql_dsp_macc: Tune DSP inference code --- techlibs/quicklogic/ql_dsp_macc.cc | 381 ++++++++++++---------------- techlibs/quicklogic/ql_dsp_macc.pmg | 55 +++- 2 files changed, 198 insertions(+), 238 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc index 602fbf3cc1a..b99b32b95cb 100644 --- a/techlibs/quicklogic/ql_dsp_macc.cc +++ b/techlibs/quicklogic/ql_dsp_macc.cc @@ -29,235 +29,169 @@ PRIVATE_NAMESPACE_BEGIN static void create_ql_macc_dsp(ql_dsp_macc_pm &pm) { - auto &st = pm.st_ql_dsp_macc; - - // Reject if multiplier drives anything else than either $add or $add and - // $mux - if (st.mux == nullptr && st.mul_nusers > 2) { - return; - } - - // Determine whether the output is taken from before or after the ff - bool out_ff; - if (st.ff_d_nusers == 2 && st.ff_q_nusers == 3) { - out_ff = true; - } else if (st.ff_d_nusers == 3 && st.ff_q_nusers == 2) { - out_ff = false; - } else { - // Illegal, cannot take the two outputs simulataneously - return; - } - - // No mux, the adder can driver either the ff or the ff + output - if (st.mux == nullptr) { - if (out_ff && st.add_nusers != 2) { - return; - } - if (!out_ff && st.add_nusers != 3) { - return; - } - } - // Mux present, the adder cannot drive anything else - else { - if (st.add_nusers != 2) { - return; - } - } - - // Mux can driver either the ff or the ff + output - if (st.mux != nullptr) { - if (out_ff && st.mux_nusers != 2) { - return; - } - if (!out_ff && st.mux_nusers != 3) { - return; - } - } - - // Accept only posedge clocked FFs - if (st.ff->getParam(ID(CLK_POLARITY)).as_int() != 1) { - return; - } - - // Get port widths - size_t a_width = GetSize(st.mul->getPort(ID(A))); - size_t b_width = GetSize(st.mul->getPort(ID(B))); - size_t z_width = GetSize(st.ff->getPort(ID(Q))); - - size_t min_width = std::min(a_width, b_width); - size_t max_width = std::max(a_width, b_width); - - // Signed / unsigned - bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); - bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool(); - - // Determine DSP type or discard if too narrow / wide - RTLIL::IdString type; - size_t tgt_a_width; - size_t tgt_b_width; - size_t tgt_z_width; - - string cell_base_name = "dsp_t1"; - string cell_size_name = ""; - string cell_cfg_name = ""; - string cell_full_name = ""; - - if (min_width <= 2 && max_width <= 2 && z_width <= 4) { - // Too narrow - return; - } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { - cell_size_name = "_10x9x32"; - tgt_a_width = 10; - tgt_b_width = 9; - tgt_z_width = 19; - } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { - cell_size_name = "_20x18x64"; - tgt_a_width = 20; - tgt_b_width = 18; - tgt_z_width = 38; - } else { - // Too wide - return; - } - - cell_cfg_name = "_cfg_ports"; // TODO: remove - cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; - - type = RTLIL::escape_id(cell_full_name); - log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, RTLIL::unescape_id(type).c_str()); - - for (auto cell : {st.mul, st.add, st.mux, st.ff}) { - if (cell != nullptr) { - log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), RTLIL::unescape_id(cell->type).c_str()); - } - } - - // Build the DSP cell name - std::string name; - name += RTLIL::unescape_id(st.mul->name) + "_"; - name += RTLIL::unescape_id(st.add->name) + "_"; - if (st.mux != nullptr) { - name += RTLIL::unescape_id(st.mux->name) + "_"; - } - name += RTLIL::unescape_id(st.ff->name); - - // Add the DSP cell - RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type); - - // Set attributes - cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); - - // Get input/output data signals - RTLIL::SigSpec sig_a; - RTLIL::SigSpec sig_b; - RTLIL::SigSpec sig_z; - - if (a_width >= b_width) { - sig_a = st.mul->getPort(ID(A)); - sig_b = st.mul->getPort(ID(B)); - } else { - sig_a = st.mul->getPort(ID(B)); - sig_b = st.mul->getPort(ID(A)); - } - - sig_z = out_ff ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); - - // Connect input data ports, sign extend / pad with zeros - sig_a.extend_u0(tgt_a_width, a_signed); - sig_b.extend_u0(tgt_b_width, b_signed); - cell->setPort(RTLIL::escape_id("a_i"), sig_a); - cell->setPort(RTLIL::escape_id("b_i"), sig_b); - - // Connect output data port, pad if needed - if ((size_t)GetSize(sig_z) < tgt_z_width) { - auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); - sig_z.append(wire); - } - cell->setPort(RTLIL::escape_id("z_o"), sig_z); - - // Connect clock, reset and enable - cell->setPort(RTLIL::escape_id("clock_i"), st.ff->getPort(ID(CLK))); - - RTLIL::SigSpec rst; - RTLIL::SigSpec ena; - - if (st.ff->hasPort(ID(ARST))) { - if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { - rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); - } else { - rst = st.ff->getPort(ID(ARST)); - } - } else { - rst = RTLIL::SigSpec(RTLIL::S0); - } - - if (st.ff->hasPort(ID(EN))) { - if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { - ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); - } else { - ena = st.ff->getPort(ID(EN)); - } - } else { - ena = RTLIL::SigSpec(RTLIL::S1); - } - - cell->setPort(RTLIL::escape_id("reset_i"), rst); - cell->setPort(RTLIL::escape_id("load_acc_i"), ena); - - // Insert feedback_i control logic used for clearing / loading the accumulator - if (st.mux != nullptr) { - RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); - - // Depending on the mux port ordering insert inverter if needed - log_assert(st.mux_ab == ID(A) || st.mux_ab == ID(B)); - if (st.mux_ab == ID(A)) { - sig_s = pm.module->Not(NEW_ID, sig_s); - } - - // Assemble the full control signal for the feedback_i port - RTLIL::SigSpec sig_f; - sig_f.append(sig_s); - sig_f.append(RTLIL::S0); - sig_f.append(RTLIL::S0); - cell->setPort(RTLIL::escape_id("feedback_i"), sig_f); - } - // No acc clear/load - else { - cell->setPort(RTLIL::escape_id("feedback_i"), RTLIL::SigSpec(RTLIL::S0, 3)); - } - - // Connect control ports - cell->setPort(RTLIL::escape_id("unsigned_a_i"), RTLIL::SigSpec(a_signed ? RTLIL::S0 : RTLIL::S1)); - cell->setPort(RTLIL::escape_id("unsigned_b_i"), RTLIL::SigSpec(b_signed ? RTLIL::S0 : RTLIL::S1)); - - // Connect config bits - cell->setPort(RTLIL::escape_id("saturate_enable_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("shift_right_i"), RTLIL::SigSpec(RTLIL::S0, 6)); - cell->setPort(RTLIL::escape_id("round_i"), RTLIL::SigSpec(RTLIL::S0)); - cell->setPort(RTLIL::escape_id("register_inputs_i"), RTLIL::SigSpec(RTLIL::S0)); - // 3 - output post acc; 1 - output pre acc - cell->setPort(RTLIL::escape_id("output_select_i"), out_ff ? RTLIL::Const(1, 3) : RTLIL::Const(3, 3)); - - bool subtract = (st.add->type == RTLIL::escape_id("$sub")); - cell->setPort(RTLIL::escape_id("subtract_i"), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); - - // Mark the cells for removal - pm.autoremove(st.mul); - pm.autoremove(st.add); - if (st.mux != nullptr) { - pm.autoremove(st.mux); - } - pm.autoremove(st.ff); + auto &st = pm.st_ql_dsp_macc; + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t z_width = GetSize(st.ff->getPort(ID(Q))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool ab_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + log_assert(ab_signed == st.mul->getParam(ID(B_SIGNED)).as_bool()); + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_z_width; + + string cell_base_name = "dsp_t1"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + log_debug("\trejected: too narrow (%zd %zd %zd)\n", min_width, max_width, z_width); + return; + } else if (min_width <= 9 && max_width <= 10 && z_width <= 19) { + cell_size_name = "_10x9x32"; + tgt_a_width = 10; + tgt_b_width = 9; + tgt_z_width = 19; + } else if (min_width <= 18 && max_width <= 20 && z_width <= 38) { + cell_size_name = "_20x18x64"; + tgt_a_width = 20; + tgt_b_width = 18; + tgt_z_width = 38; + } else { + log_debug("\trejected: too wide (%zd %zd %zd)\n", min_width, max_width, z_width); + return; + } + + type = RTLIL::escape_id(cell_base_name + cell_size_name + "_cfg_ports"); + log("Inferring MACC %zux%zu->%zu as %s from:\n", a_width, b_width, z_width, log_id(type)); + + for (auto cell : {st.mul, st.add, st.mux, st.ff}) + if (cell) + log(" %s (%s)\n", log_id(cell), log_id(cell->type)); + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(NEW_ID, type); + + // Set attributes + cell->set_bool_attribute(ID(is_inferred), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a, sig_b, sig_z; + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + sig_z = st.output_registered ? st.ff->getPort(ID(Q)) : st.ff->getPort(ID(D)); + + if (a_width < b_width) + std::swap(sig_a, sig_b); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, ab_signed); + sig_b.extend_u0(tgt_b_width, ab_signed); + cell->setPort(ID(a_i), sig_a); + cell->setPort(ID(b_i), sig_b); + + // Connect output data port, pad if needed + if ((size_t) GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(ID(z_o), sig_z); + + // Connect clock, reset and enable + cell->setPort(ID(clock_i), st.ff->getPort(ID(CLK))); + + RTLIL::SigSpec rst; + RTLIL::SigSpec ena; + + if (st.ff->hasPort(ID(ARST))) { + if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) { + rst = pm.module->Not(NEW_ID, st.ff->getPort(ID(ARST))); + } else { + rst = st.ff->getPort(ID(ARST)); + } + } else { + rst = RTLIL::SigSpec(RTLIL::S0); + } + + if (st.ff->hasPort(ID(EN))) { + if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) { + ena = pm.module->Not(NEW_ID, st.ff->getPort(ID(EN))); + } else { + ena = st.ff->getPort(ID(EN)); + } + } else { + ena = RTLIL::SigSpec(RTLIL::S1); + } + + cell->setPort(ID(reset_i), rst); + cell->setPort(ID(load_acc_i), ena); + + // Insert feedback_i control logic used for clearing / loading the accumulator + if (st.mux_in_pattern) { + RTLIL::SigSpec sig_s = st.mux->getPort(ID(S)); + + // Depending on the mux port ordering insert inverter if needed + log_assert(st.mux_ab.in(ID(A), ID(B))); + if (st.mux_ab == ID(A)) + sig_s = pm.module->Not(NEW_ID, sig_s); + + // Assemble the full control signal for the feedback_i port + RTLIL::SigSpec sig_f; + sig_f.append(sig_s); + sig_f.append(RTLIL::S0); + sig_f.append(RTLIL::S0); + cell->setPort(ID(feedback_i), sig_f); + } + // No acc clear/load + else { + cell->setPort(ID(feedback_i), RTLIL::SigSpec(RTLIL::S0, 3)); + } + + // Connect control ports + cell->setPort(ID(unsigned_a_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + cell->setPort(ID(unsigned_b_i), RTLIL::SigSpec(ab_signed ? RTLIL::S0 : RTLIL::S1)); + + // Connect config bits + cell->setPort(ID(saturate_enable_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(ID(shift_right_i), RTLIL::SigSpec(RTLIL::S0, 6)); + cell->setPort(ID(round_i), RTLIL::SigSpec(RTLIL::S0)); + cell->setPort(ID(register_inputs_i), RTLIL::SigSpec(RTLIL::S0)); + // 3 - output post acc; 1 - output pre acc + cell->setPort(ID(output_select_i), RTLIL::Const(st.output_registered ? 1 : 3, 3)); + + bool subtract = (st.add->type == ID($sub)); + cell->setPort(ID(subtract_i), RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); + if (st.mux != nullptr) { + pm.autoremove(st.mux); + } + pm.autoremove(st.ff); } struct QlDspMacc : public Pass { - - QlDspMacc() : Pass("ql_dsp_macc", "Does something") {} + QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {} void help() override { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" ql_dsp_macc [options] [selection]\n"); + log(" ql_dsp_macc [selection]\n"); + log("\n"); + log("This pass looks for a multiply-accumulate pattern based on which it infers a\n"); + log("QuickLogic DSP cell.\n"); log("\n"); } @@ -271,9 +205,8 @@ struct QlDspMacc : public Pass { } extra_args(a_Args, argidx, a_Design); - for (auto module : a_Design->selected_modules()) { + for (auto module : a_Design->selected_modules()) ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp); - } } } QlDspMacc; diff --git a/techlibs/quicklogic/ql_dsp_macc.pmg b/techlibs/quicklogic/ql_dsp_macc.pmg index 4cfd15a2436..df18596d109 100644 --- a/techlibs/quicklogic/ql_dsp_macc.pmg +++ b/techlibs/quicklogic/ql_dsp_macc.pmg @@ -1,48 +1,75 @@ pattern ql_dsp_macc +// Rough sketch: (mux is optional) +// +// /-----------------------\ +// | | +// \ / | +// mul ----> add -----> mux -----> ff -+----> +// | /\ +// | | +// -------------- state add_ba state mux_ab -state mul_nusers -state add_nusers -state mux_nusers -state ff_d_nusers -state ff_q_nusers +// Is the output taken from before or after the FF? +state output_registered +// Is there a mux in the pattern? +state mux_in_pattern + +code mux_in_pattern + mux_in_pattern = false; + branch; + mux_in_pattern = true; +endcode + +// The multiplier is at the center of our pattern match mul select mul->type.in($mul) + // It has either two or three consumers depending on whether there's a mux + // in the pattern or not select nusers(port(mul, \Y)) <= 3 - set mul_nusers nusers(port(mul, \Y)) + filter nusers(port(mul, \Y)) == (mux_in_pattern ? 3 : 2) endmatch +code output_registered + output_registered = false; + branch; + output_registered = true; +endcode + match add select add->type.in($add, $sub) choice AB {\A, \B} define BA (AB == \A ? \B : \A) + // One input to the adder is fed by the multiplier index port(add, AB) === port(mul, \Y) - select nusers(port(add, \Y)) <= 3 - set add_nusers nusers(port(add, \Y)) + // Save the other input port, it needs to be fed by the flip-flop set add_ba BA + // Adder has either two or three consumers; it will have three consumers + // IFF there's no mux in the pattern and the multiplier-accumulator result + // is taken unregistered + filter nusers(port(add, \Y)) == (!mux_in_pattern && !output_registered ? 3 : 2) endmatch match mux + if mux_in_pattern select mux->type.in($mux) choice AB {\A, \B} define BA (AB == \A ? \B : \A) index port(mux, AB) === port(mul, \Y) index port(mux, BA) === port(add, \Y) - select nusers(port(mux, \Y)) <= 3 - set mux_nusers nusers(port(mux, \Y)) + filter nusers(port(mux, \Y)) == (output_registered ? 2 : 3) set mux_ab AB - optional endmatch match ff select ff->type.in($dff, $adff, $dffe, $adffe) - index port(ff, \D) === (mux == nullptr ? port(add, \Y) : port(mux, \Y)) + select param(ff, \CLK_POLARITY).as_bool() + index port(ff, \D) === mux_in_pattern ? port(mux, \Y) : port(add, \Y); index port(ff, \Q) === port(add, add_ba) - set ff_d_nusers nusers(port(ff, \D)) - set ff_q_nusers nusers(port(ff, \Q)) + filter nusers(port(ff, \Q)) == (output_registered ? 3 : 2) endmatch code From 6672b6c1b38bb1556a035c7459078806e935c5ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 9 Oct 2023 13:13:42 +0200 Subject: [PATCH 09/39] quicklogic: Move pp3 tests one level down --- Makefile | 2 +- tests/arch/quicklogic/{ => pp3}/add_sub.ys | 2 +- tests/arch/quicklogic/{ => pp3}/adffs.ys | 2 +- tests/arch/quicklogic/{ => pp3}/counter.ys | 2 +- tests/arch/quicklogic/{ => pp3}/dffs.ys | 2 +- tests/arch/quicklogic/{ => pp3}/fsm.ys | 2 +- tests/arch/quicklogic/{ => pp3}/latches.ys | 2 +- tests/arch/quicklogic/{ => pp3}/logic.ys | 2 +- tests/arch/quicklogic/{ => pp3}/mux.ys | 2 +- tests/arch/quicklogic/{ => pp3}/run-test.sh | 2 +- tests/arch/quicklogic/{ => pp3}/tribuf.ys | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) rename tests/arch/quicklogic/{ => pp3}/add_sub.ys (93%) rename tests/arch/quicklogic/{ => pp3}/adffs.ys (98%) rename tests/arch/quicklogic/{ => pp3}/counter.ys (95%) rename tests/arch/quicklogic/{ => pp3}/dffs.ys (97%) rename tests/arch/quicklogic/{ => pp3}/fsm.ys (96%) rename tests/arch/quicklogic/{ => pp3}/latches.ys (96%) rename tests/arch/quicklogic/{ => pp3}/logic.ys (94%) rename tests/arch/quicklogic/{ => pp3}/mux.ys (98%) rename tests/arch/quicklogic/{ => pp3}/run-test.sh (79%) rename tests/arch/quicklogic/{ => pp3}/tribuf.ys (93%) diff --git a/Makefile b/Makefile index b980bfdd211..f467330c894 100644 --- a/Makefile +++ b/Makefile @@ -880,7 +880,7 @@ endif +cd tests/arch/gowin && bash run-test.sh $(SEEDOPT) +cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT) +cd tests/arch/nexus && bash run-test.sh $(SEEDOPT) - +cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT) + +cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT) +cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh +cd tests/memfile && bash run-test.sh diff --git a/tests/arch/quicklogic/add_sub.ys b/tests/arch/quicklogic/pp3/add_sub.ys similarity index 93% rename from tests/arch/quicklogic/add_sub.ys rename to tests/arch/quicklogic/pp3/add_sub.ys index 47db42afc9a..c5e9fb29be8 100644 --- a/tests/arch/quicklogic/add_sub.ys +++ b/tests/arch/quicklogic/pp3/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog ../common/add_sub.v +read_verilog ../../common/add_sub.v hierarchy -top top equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v synth_quicklogic -family pp3 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/quicklogic/adffs.ys b/tests/arch/quicklogic/pp3/adffs.ys similarity index 98% rename from tests/arch/quicklogic/adffs.ys rename to tests/arch/quicklogic/pp3/adffs.ys index 43f36c20cb5..fb9f34df429 100644 --- a/tests/arch/quicklogic/adffs.ys +++ b/tests/arch/quicklogic/pp3/adffs.ys @@ -1,4 +1,4 @@ -read_verilog ../common/adffs.v +read_verilog ../../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/quicklogic/counter.ys b/tests/arch/quicklogic/pp3/counter.ys similarity index 95% rename from tests/arch/quicklogic/counter.ys rename to tests/arch/quicklogic/pp3/counter.ys index 9a7dcdf0809..5095cb8efe8 100644 --- a/tests/arch/quicklogic/counter.ys +++ b/tests/arch/quicklogic/pp3/counter.ys @@ -1,4 +1,4 @@ -read_verilog ../common/counter.v +read_verilog ../../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/quicklogic/dffs.ys b/tests/arch/quicklogic/pp3/dffs.ys similarity index 97% rename from tests/arch/quicklogic/dffs.ys rename to tests/arch/quicklogic/pp3/dffs.ys index 2bcfbf672de..f5023e48e14 100644 --- a/tests/arch/quicklogic/dffs.ys +++ b/tests/arch/quicklogic/pp3/dffs.ys @@ -1,4 +1,4 @@ -read_verilog ../common/dffs.v +read_verilog ../../common/dffs.v rename dff my_dff # Work around conflicting module names between test and vendor cells rename dffe my_dffe design -save read diff --git a/tests/arch/quicklogic/fsm.ys b/tests/arch/quicklogic/pp3/fsm.ys similarity index 96% rename from tests/arch/quicklogic/fsm.ys rename to tests/arch/quicklogic/pp3/fsm.ys index 50dcb71b142..418db8025bd 100644 --- a/tests/arch/quicklogic/fsm.ys +++ b/tests/arch/quicklogic/pp3/fsm.ys @@ -1,4 +1,4 @@ -read_verilog ../common/fsm.v +read_verilog ../../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/quicklogic/latches.ys b/tests/arch/quicklogic/pp3/latches.ys similarity index 96% rename from tests/arch/quicklogic/latches.ys rename to tests/arch/quicklogic/pp3/latches.ys index bcef429904b..90a4f515b75 100644 --- a/tests/arch/quicklogic/latches.ys +++ b/tests/arch/quicklogic/pp3/latches.ys @@ -1,4 +1,4 @@ -read_verilog ../common/latches.v +read_verilog ../../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/quicklogic/logic.ys b/tests/arch/quicklogic/pp3/logic.ys similarity index 94% rename from tests/arch/quicklogic/logic.ys rename to tests/arch/quicklogic/pp3/logic.ys index 9c34ddaeb3d..ecddda577d3 100644 --- a/tests/arch/quicklogic/logic.ys +++ b/tests/arch/quicklogic/pp3/logic.ys @@ -1,4 +1,4 @@ -read_verilog ../common/logic.v +read_verilog ../../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/quicklogic/pp3/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic # equivalency check diff --git a/tests/arch/quicklogic/mux.ys b/tests/arch/quicklogic/pp3/mux.ys similarity index 98% rename from tests/arch/quicklogic/mux.ys rename to tests/arch/quicklogic/pp3/mux.ys index 5214bb7872d..a3b12a73d2a 100644 --- a/tests/arch/quicklogic/mux.ys +++ b/tests/arch/quicklogic/pp3/mux.ys @@ -1,4 +1,4 @@ -read_verilog ../common/mux.v +read_verilog ../../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/quicklogic/run-test.sh b/tests/arch/quicklogic/pp3/run-test.sh similarity index 79% rename from tests/arch/quicklogic/run-test.sh rename to tests/arch/quicklogic/pp3/run-test.sh index 4be4b70ae17..3f8515f9aa6 100755 --- a/tests/arch/quicklogic/run-test.sh +++ b/tests/arch/quicklogic/pp3/run-test.sh @@ -1,4 +1,4 @@ #!/usr/bin/env bash set -eu -source ../../gen-tests-makefile.sh +source ../../../gen-tests-makefile.sh run_tests --yosys-scripts --bash --yosys-args "-w 'Yosys has only limited support for tri-state logic at the moment.'" diff --git a/tests/arch/quicklogic/tribuf.ys b/tests/arch/quicklogic/pp3/tribuf.ys similarity index 93% rename from tests/arch/quicklogic/tribuf.ys rename to tests/arch/quicklogic/pp3/tribuf.ys index d74fbbcdd2a..f68a0d7790e 100644 --- a/tests/arch/quicklogic/tribuf.ys +++ b/tests/arch/quicklogic/pp3/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog ../common/tribuf.v +read_verilog ../../common/tribuf.v hierarchy -top tristate proc tribuf From e19833f8c78846fc30f581259d06d2e34ff9fd86 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 9 Oct 2023 13:18:09 +0200 Subject: [PATCH 10/39] synth_quiclogic: Fix conditioning of bram passes --- techlibs/quicklogic/synth_quicklogic.cc | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 101dff66597..9bfaa191e93 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -245,16 +245,15 @@ struct SynthQuickLogicPass : public ScriptPass { run("opt_clean"); } - if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)")) { - if(family == "qlf_k6n10f" || help_mode) + if (check_label("map_bram", "(for qlf_k6n10f, skip if -no_bram)") + && (family == "qlf_k6n10f" || help_mode)) { run("memory_libmap -lib " + lib_path + family + "/libmap_brams.txt"); run("ql_bram_merge"); run("techmap -map " + lib_path + family + "/libmap_brams_map.v"); run("techmap -autoproc -map " + lib_path + family + "/brams_map.v"); - if (bramTypes || help_mode) { + if (bramTypes || help_mode) run("ql_bram_types", "(if -bramtypes)"); - } } if (check_label("map_ffram")) { From 554d8caef7e42e074f825d648adf3c7fd1a32f5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 12:14:48 +0100 Subject: [PATCH 11/39] quicklogic: Add basic k6n10f tests --- Makefile | 1 + tests/arch/quicklogic/qlf_k6n10f/add_sub.ys | 8 ++++ tests/arch/quicklogic/qlf_k6n10f/adffs.ys | 48 ++++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/counter.ys | 12 +++++ tests/arch/quicklogic/qlf_k6n10f/dffs.ys | 21 +++++++++ tests/arch/quicklogic/qlf_k6n10f/fsm.ys | 17 +++++++ tests/arch/quicklogic/qlf_k6n10f/latches.ys | 29 ++++++++++++ tests/arch/quicklogic/qlf_k6n10f/logic.ys | 10 ++++ tests/arch/quicklogic/qlf_k6n10f/mux.ys | 40 ++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/run-test.sh | 4 ++ 10 files changed, 190 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/add_sub.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/adffs.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/counter.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/dffs.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/fsm.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/latches.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/logic.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/mux.ys create mode 100755 tests/arch/quicklogic/qlf_k6n10f/run-test.sh diff --git a/Makefile b/Makefile index f467330c894..c3d3f57eac8 100644 --- a/Makefile +++ b/Makefile @@ -881,6 +881,7 @@ endif +cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT) +cd tests/arch/nexus && bash run-test.sh $(SEEDOPT) +cd tests/arch/quicklogic/pp3 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh $(SEEDOPT) +cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh +cd tests/memfile && bash run-test.sh diff --git a/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys b/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys new file mode 100644 index 00000000000..30d9bbc9dc3 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog ../../common/add_sub.v +hierarchy -top top +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:$lut # OOT flow has 8 +select -assert-count 8 t:adder_carry +select -assert-none t:$lut t:adder_carry %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/adffs.ys b/tests/arch/quicklogic/qlf_k6n10f/adffs.ys new file mode 100644 index 00000000000..475355d2bd0 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/adffs.ys @@ -0,0 +1,48 @@ +read_verilog ../../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=1 %i +select -assert-none r:WIDTH>1 +select -assert-count 1 t:dffsre + +select -assert-none t:$lut t:dffsre %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:dffsre + +select -assert-none t:dffsre %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=1 %i +select -assert-none r:WIDTH>1 +select -assert-count 1 t:sdffsre + +select -assert-none t:$lut t:sdffsre %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffnsre + +select -assert-none t:sdffnsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/counter.ys b/tests/arch/quicklogic/qlf_k6n10f/counter.ys new file mode 100644 index 00000000000..ebb6ce243eb --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/counter.ys @@ -0,0 +1,12 @@ +read_verilog ../../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -multiclock -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:$lut +select -assert-count 8 t:adder_carry +select -assert-count 8 t:dffsre + +select -assert-none t:$lut t:adder_carry t:dffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys new file mode 100644 index 00000000000..a4a159f1b09 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -0,0 +1,21 @@ +read_verilog ../../common/dffs.v +rename dff my_dff # Work around conflicting module names between test and vendor cells +rename dffe my_dffe +design -save read + +hierarchy -top my_dff +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffsre +select -assert-none t:sdffsre %% t:* %D + +design -load read +hierarchy -top my_dffe +proc +equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:sdffsre +select -assert-none t:sdffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/fsm.ys b/tests/arch/quicklogic/qlf_k6n10f/fsm.ys new file mode 100644 index 00000000000..e7a9d962d6e --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/fsm.ys @@ -0,0 +1,17 @@ +read_verilog ../../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f +async2sync +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 9 t:$lut +select -assert-count 6 t:sdffsre + +select -assert-none t:$lut t:sdffsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/latches.ys b/tests/arch/quicklogic/qlf_k6n10f/latches.ys new file mode 100644 index 00000000000..59574a1fb77 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/latches.ys @@ -0,0 +1,29 @@ +read_verilog ../../common/latches.v +design -save read + +hierarchy -top latchp +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchp +select -assert-count 1 t:latchsre +select -assert-none t:latchsre %% t:* %D + +design -load read +hierarchy -top latchn +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchn +select -assert-count 1 t:latchnsre +select -assert-none t:latchnsre %% t:* %D + +design -load read +hierarchy -top latchsr +proc +equiv_opt -assert -async2sync -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f +design -load postopt +cd latchsr +select -assert-count 2 t:$lut +select -assert-count 1 t:latchnsre +select -assert-none t:$lut t:latchnsre %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/logic.ys b/tests/arch/quicklogic/qlf_k6n10f/logic.ys new file mode 100644 index 00000000000..a24d5a479f6 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/logic.ys @@ -0,0 +1,10 @@ +read_verilog ../../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:$lut + +select -assert-none t:$lut %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/mux.ys b/tests/arch/quicklogic/qlf_k6n10f/mux.ys new file mode 100644 index 00000000000..633b5fc8656 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/mux.ys @@ -0,0 +1,40 @@ +read_verilog ../../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=3 %i +select -assert-none t:$lut r:WIDTH=3 %i %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:$lut r:WIDTH=6 %i +select -assert-none t:$lut r:WIDTH=6 %i %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 2 t:$lut r:WIDTH=6 %i +select -assert-count 1 t:$lut r:WIDTH=3 %i +select -assert-none t:$lut r:WIDTH=6 r:WIDTH=3 %u %i %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-max 5 t:$lut r:WIDTH=6 %i # OOT flow does 2 +select -assert-max 1 t:$lut r:WIDTH=3 %i # and here 1 +select -assert-max 1 t:$lut r:WIDTH=4 r:WIDTH=5 %u %i +select -assert-none t:$lut r:WIDTH>2 %i %% t:* %D diff --git a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh new file mode 100755 index 00000000000..36689eddedc --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh @@ -0,0 +1,4 @@ +#!/usr/bin/env bash +set -eu +source ../../../gen-tests-makefile.sh +run_tests --yosys-scripts --bash From 532aca28ab9e5fbe245a4bb943e0b2e88c0015aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 14:21:59 +0100 Subject: [PATCH 12/39] quicklogic: Drop `blackbox` off `adder_carry` --- techlibs/quicklogic/qlf_k6n10f/cells_sim.v | 1 - 1 file changed, 1 deletion(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v index b9f40625646..ddfd51ee7ce 100644 --- a/techlibs/quicklogic/qlf_k6n10f/cells_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/cells_sim.v @@ -121,7 +121,6 @@ module sh_dff( endmodule (* abc9_box, lib_whitebox *) -(* blackbox *) (* keep *) module adder_carry( output wire sumout, From dad85b5178133cbadd25dbf52ddb95ae033acca4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 14:22:28 +0100 Subject: [PATCH 13/39] synth_quicklogic: Fix missing FF mapping --- techlibs/quicklogic/synth_quicklogic.cc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 9bfaa191e93..0e7aaa75276 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -282,6 +282,7 @@ struct SynthQuickLogicPass : public ScriptPass { run("shregmap -minlen -maxlen ", "(for qlf_k6n10f)"); run("dfflegalize -cell "); run("techmap -map " + lib_path + family + "/cells_map.v", "(for pp3)"); + run("techmap -map " + lib_path + family + "/ffs_map.v", "(for ql_k6n10f)"); } if (family == "pp3") { run("dfflegalize -cell $_DFFSRE_PPPP_ 0 -cell $_DLATCH_?_ x"); @@ -293,6 +294,7 @@ struct SynthQuickLogicPass : public ScriptPass { // not in the allowed set. As a workaround we put them in the allowed // set explicitly and map them later to $_DLATCHSR_[NP]NN_. run("dfflegalize -cell $_DFFSRE_?NNP_ 0 -cell $_DLATCHSR_?NN_ 0 -cell $_DLATCH_?_ 0" " -cell $_SDFFE_?N?P_ 0"); + run("techmap -map " + lib_path + family + "/ffs_map.v"); } run("opt"); } From db9e5b4f14959ef4b1883a1909b0fcfa7c2cd098 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:27:35 +0100 Subject: [PATCH 14/39] quicklogic: Fix `dffs.ys` test --- tests/arch/quicklogic/qlf_k6n10f/dffs.ys | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys index a4a159f1b09..79a16c9412b 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/dffs.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/dffs.ys @@ -7,7 +7,7 @@ hierarchy -top my_dff proc equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module +cd my_dff # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre select -assert-none t:sdffsre %% t:* %D @@ -16,6 +16,6 @@ hierarchy -top my_dffe proc equiv_opt -async2sync -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v -map +/quicklogic/common/cells_sim.v synth_quicklogic -family qlf_k6n10f # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module +cd my_dffe # Constrain all select calls below inside the top module select -assert-count 1 t:sdffsre select -assert-none t:sdffsre %% t:* %D From b30544d61d575658cff664d7ffbd52f8d7be7c2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:17:03 +0100 Subject: [PATCH 15/39] ql_dsp_io_regs: Fix ID strings, constant detection --- techlibs/quicklogic/ql_dsp_io_regs.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc index efb1ad4d5f3..523c86e7341 100644 --- a/techlibs/quicklogic/ql_dsp_io_regs.cc +++ b/techlibs/quicklogic/ql_dsp_io_regs.cc @@ -30,9 +30,9 @@ PRIVATE_NAMESPACE_BEGIN // ============================================================================ struct QlDspIORegs : public Pass { - const std::vector ports2del_mult = {"load_acc", "subtract", "acc_fir", "dly_b", - "saturate_enable", "shift_right", "round"}; - const std::vector ports2del_mult_acc = {"acc_fir", "dly_b"}; + const std::vector ports2del_mult = {ID(load_acc), ID(subtract), ID(acc_fir), ID(dly_b), + ID(saturate_enable), ID(shift_right), ID(round)}; + const std::vector ports2del_mult_acc = {ID(acc_fir), ID(dly_b)}; SigMap sigmap; @@ -80,7 +80,7 @@ struct QlDspIORegs : public Pass { // Get DSP configuration for (auto cfg_port : {ID(register_inputs), ID(output_select)}) - if (!cell->hasPort(cfg_port) || sigmap(cell->getPort(cfg_port)).is_fully_const()) + if (!cell->hasPort(cfg_port) || !sigmap(cell->getPort(cfg_port)).is_fully_const()) log_error("Missing or non-constant '%s' port on DSP cell %s\n", log_id(cfg_port), log_id(cell)); int reg_in_i = sigmap(cell->getPort(ID(register_inputs))).as_int(); @@ -97,7 +97,7 @@ struct QlDspIORegs : public Pass { log_error("Unexpected feedback configuration on %s\n", log_id(cell)); // Build new type name - std::string new_type = "QL_DSP2_MULT"; + std::string new_type = "\\QL_DSP2_MULT"; // Decide if we should be deleting the clock port bool del_clk = true; From a5c8d246f7d618893bacadc516d07ac9df50f448 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:18:33 +0100 Subject: [PATCH 16/39] quicklogic: Add k6n10f DSP test --- tests/arch/quicklogic/qlf_k6n10f/dsp.ys | 120 ++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/dsp.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/dsp.ys b/tests/arch/quicklogic/qlf_k6n10f/dsp.ys new file mode 100644 index 00000000000..023ff0d89f6 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/dsp.ys @@ -0,0 +1,120 @@ +read_verilog < 0) + assert(y == y_expected); + i <= i + 1; + end +end +endmodule +EOF +read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v +hierarchy -top testbench +proc +sim -assert -q -clock clk -n 20 From b602c0858f4da092a072b53e84a910c3ee419d1e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 27 Nov 2023 17:31:46 +0100 Subject: [PATCH 17/39] quicklogic: Set initial values on inferred TDP36K --- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index 20638c4f9af..f4f4420c1a2 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -75,6 +75,18 @@ default: mode = 3'b000; endcase endfunction +function [36863:0] pack_init; + integer i; + reg [35:0] ri; + for (i = 0; i < (OPTION_SPLIT ? 512 : 1024); i = i + 1) begin + ri = INIT[i*36 +: 36]; + pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], + ri[17], ri[8], ri[16:9], ri[7:0]}; + end + if (OPTION_SPLIT) + pack_init[36863:18432] = 18432'bx; +endfunction + wire REN_A1_i; wire REN_A2_i; @@ -168,7 +180,9 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, (* is_split = 0 *) (* port_a_width = PORT_A_WIDTH *) (* port_b_width = PORT_B_WIDTH *) -TDP36K _TECHMAP_REPLACE_ ( +TDP36K #( + .RAM_INIT(pack_init()), +) _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .CLK_A1_i(PORT_A_CLK), @@ -290,6 +304,15 @@ default: mode = 3'b000; endcase endfunction +function [36863:0] pack_init; + integer i; + reg [35:0] ri; + for (i = 0; i < 1024; i = i + 1) begin + ri = {INIT2[i*18 +: 18], INIT1[i*18 +: 18]}; + pack_init[i*36 +: 36] = {ri[35], ri[26], ri[34:27], ri[25:18], ri[17], ri[8], ri[16:9], ri[7:0]}; + end +endfunction + wire REN_A1_i; wire REN_A2_i; @@ -418,7 +441,9 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = {1'b1, (* port_a2_width = PORT_A2_WIDTH *) (* port_b1_width = PORT_B1_WIDTH *) (* port_b2_width = PORT_B2_WIDTH *) -TDP36K _TECHMAP_REPLACE_ ( +TDP36K #( + .RAM_INIT(pack_init()), +) _TECHMAP_REPLACE_ ( .RESET_ni(1'b1), .WDATA_A1_i(WDATA_A1_i), .WDATA_A2_i(WDATA_A2_i), From 4903f99f85a9392418c03796d251391f83182276 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Wed, 29 Nov 2023 11:04:34 +0100 Subject: [PATCH 18/39] quicklogic: Add missing `RAM_INIT` param on TDP36K sim model --- techlibs/quicklogic/qlf_k6n10f/brams_sim.v | 160 ++------------------- 1 file changed, 14 insertions(+), 146 deletions(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v index 5f04c0e7fac..de6d992335a 100644 --- a/techlibs/quicklogic/qlf_k6n10f/brams_sim.v +++ b/techlibs/quicklogic/qlf_k6n10f/brams_sim.v @@ -81,150 +81,7 @@ module TDP36K ( // Split (1 bit) localparam [ 0:0] SPLIT_i = MODE_BITS[80]; - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; input wire RESET_ni; input wire WEN_A1_i; @@ -261,6 +118,15 @@ module TDP36K ( output reg [17:0] RDATA_A2_o; output reg [17:0] RDATA_B2_o; input wire FLUSH2_i; + + function [18431:0] split_init; + input index; + integer i; + for (i = 0; i < 1024; i = i + 1) begin + split_init[i * 18 +: 18] = RAM_INIT[i * 36 + index * 18 +: 18]; + end + endfunction + wire EMPTY2; wire EPO2; wire EWM2; @@ -605,7 +471,8 @@ module TDP36K ( .SYNC_FIFO_i(SYNC_FIFO1_i), .POWERDN_i(POWERDN1_i), .SLEEP_i(SLEEP1_i), - .PROTECT_i(PROTECT1_i) + .PROTECT_i(PROTECT1_i), + .INIT_i(split_init(0)) )u1( .RMODE_A_i(ram_rmode_a1), .RMODE_B_i(ram_rmode_b1), @@ -642,7 +509,8 @@ module TDP36K ( .SYNC_FIFO_i(SYNC_FIFO2_i), .POWERDN_i(POWERDN2_i), .SLEEP_i(SLEEP2_i), - .PROTECT_i(PROTECT2_i) + .PROTECT_i(PROTECT2_i), + .INIT_i(split_init(1)) )u2( .RMODE_A_i(ram_rmode_a2), .RMODE_B_i(ram_rmode_b2), From e0a6a01ecb897f39045b12b2135a998ac440b061 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Thu, 30 Nov 2023 10:41:55 +0100 Subject: [PATCH 19/39] quicklogic: Add `RAM_INIT` to specialized BRAM models --- techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py index 5f7da90977e..e57c04a0887 100644 --- a/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py +++ b/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py @@ -31,6 +31,7 @@ def generate(filename): ); parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; input wire RESET_ni; input wire WEN_A1_i, WEN_B1_i; @@ -61,7 +62,7 @@ def generate(filename): input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( .RESET_ni (RESET_ni), .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), @@ -148,6 +149,7 @@ def generate(filename): ); parameter [80:0] MODE_BITS = 81'd0; + parameter [1024*36-1:0] RAM_INIT = 36864'bx; input wire RESET_ni; input wire WEN_A1_i, WEN_B1_i; @@ -178,7 +180,7 @@ def generate(filename): input wire FLUSH2_i; - TDP36K #(.MODE_BITS(MODE_BITS)) bram ( + TDP36K #(.MODE_BITS(MODE_BITS), .RAM_INIT(RAM_INIT)) bram ( .RESET_ni (RESET_ni), .WEN_A1_i (WEN_A1_i), .WEN_B1_i (WEN_B1_i), .REN_A1_i (REN_A1_i), .REN_B1_i (REN_B1_i), From 991850e1c9de77a1788c886d89106bd0769ae5c7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 29 Nov 2023 16:48:20 +1300 Subject: [PATCH 20/39] quicklogic: Initial blockram tests Use python script to generate tests for both SDP and TDP across multiple sizes of RAM. Adds sync_ram_sdp_(wwr|wrr) to common blockram.v for double width write and double width read respectively. --- tests/arch/common/blockram.v | 51 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/.gitignore | 1 + .../quicklogic/qlf_k6n10f/gen_memories.py | 51 +++++++++++++++++++ 3 files changed, 103 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/.gitignore create mode 100644 tests/arch/quicklogic/qlf_k6n10f/gen_memories.py diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index c06ac96d5bc..d2b2dae56ea 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,6 +45,57 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // wd=16, wa=9 + (input wire clk, write_enable, + input wire [(DATA_WIDTH*2)-1:0] data_in, + input wire [ADDRESS_WIDTH-2:0] address_in_w, + input wire [ADDRESS_WIDTH-1:0] address_in_r, + output wire [DATA_WIDTH-1:0] data_out); + + localparam WORD = ((DATA_WIDTH*2)-1); + localparam DEPTH = (2**(ADDRESS_WIDTH-1)-1); + + reg [WORD:0] data_out_r; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) begin + memory[address_in_w] <= data_in; + end + data_out_r <= memory[address_in_r>>1]; + end + + assign data_out = address_in_r[0] ? data_out_r[WORD:DATA_WIDTH] : data_out_r[DATA_WIDTH-1:0]; + +endmodule // sync_ram_sdp_wwr + + +module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9 + (input wire clk, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_w, + input wire [ADDRESS_WIDTH-2:0] address_in_r, + output wire [(DATA_WIDTH*1)-1:0] data_out); + + localparam WORD = (DATA_WIDTH-1); + localparam DEPTH = (2**ADDRESS_WIDTH-1); + + reg [WORD:0] data_out_r0; + reg [WORD:0] data_out_r1; + reg [WORD:0] memory [0:DEPTH]; + + always @(posedge clk) begin + if (write_enable) + memory[address_in_w] <= data_in; + data_out_r0 <= memory[address_in_r<<1+0]; + data_out_r1 <= memory[address_in_r<<1+1]; + end + + assign data_out = {data_out_r0, data_out_r1}; + +endmodule // sync_ram_sdp_wrr + + module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, diff --git a/tests/arch/quicklogic/qlf_k6n10f/.gitignore b/tests/arch/quicklogic/qlf_k6n10f/.gitignore new file mode 100644 index 00000000000..fb232f235f3 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/.gitignore @@ -0,0 +1 @@ +t_*.ys diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py new file mode 100644 index 00000000000..d0eb22a475f --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -0,0 +1,51 @@ +blockram_template = """\ +design -reset; read_verilog -defer ../../common/blockram.v +chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top} +hierarchy -top {top} +synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} +log TESTING aw:{aw} dw:{dw} top:{top}\ +""" +blockram_tests: "list[tuple[int, int, str, list[str]]]" = [ + # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work + (10, 36, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (11, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (12, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + # larger sizes need an extra ram + (10, 48, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + (11, 36, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + (12, 18, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + (12, 10, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + # 4096x20bit *can* fit in 3, albeit somewhat awkwardly + (12, 20, "sync_ram_*dp", ["-assert-min 3 t:TDP36K", + "-assert-max 4 t:TDP36K"]), + # smaller sizes can still fit in one + (10, 32, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (10, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (10, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (11, 16, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (11, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (12, 8, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (13, 4, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (14, 2, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + (15, 1, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) + (11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + (11, 9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) + (11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + (10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), +] + +with open("t_mem.ys", mode="w") as f: + for (aw, dw, top, assertions) in blockram_tests: + if "*" in top: + star_sub = ["s", "t"] + else: + star_sub = [""] + for sub in star_sub: + print( + blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)), + file=f + ) + for assertion in assertions: + print("select {}\n".format(assertion), file=f, end=None) From 8d3b238b9b90f61e505025cecba29ac0e18e3ec7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Wed, 29 Nov 2023 17:34:22 +1300 Subject: [PATCH 21/39] quicklogic: Testing split TDP36K Adds `double_sync_ram_sdp` to `common/blockram.v`, providing a test for two disjoint memories. Refactor python blockram template to take a list of params to support the above. Also change the smaller single TDP36K tests to also test `port_a_width` value. --- tests/arch/common/blockram.v | 40 +++++++++ .../quicklogic/qlf_k6n10f/gen_memories.py | 83 ++++++++++++------- 2 files changed, 93 insertions(+), 30 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index d2b2dae56ea..c37074382b2 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -96,6 +96,46 @@ module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra endmodule // sync_ram_sdp_wrr +module double_sync_ram_sdp #(parameter DATA_WIDTH_A=8, ADDRESS_WIDTH_A=10, DATA_WIDTH_B=8, ADDRESS_WIDTH_B=10) +( + input wire write_enable_a, clk_a, + input wire [DATA_WIDTH_A-1:0] data_in_a, + input wire [ADDRESS_WIDTH_A-1:0] address_in_r_a, address_in_w_a, + output wire [DATA_WIDTH_A-1:0] data_out_a, + + input wire write_enable_b, clk_b, + input wire [DATA_WIDTH_B-1:0] data_in_b, + input wire [ADDRESS_WIDTH_B-1:0] address_in_r_b, address_in_w_b, + output wire [DATA_WIDTH_B-1:0] data_out_b +); + + sync_ram_sdp #( + .DATA_WIDTH(DATA_WIDTH_A), + .ADDRESS_WIDTH(ADDRESS_WIDTH_A) + ) a_ram ( + .write_enable(write_enable_a), + .clk(clk_a), + .data_in(data_in_a), + .address_in_r(address_in_r_a), + .address_in_w(address_in_w_a), + .data_out(data_out_a) + ); + + sync_ram_sdp #( + .DATA_WIDTH(DATA_WIDTH_B), + .ADDRESS_WIDTH(ADDRESS_WIDTH_B) + ) b_ram ( + .write_enable(write_enable_b), + .clk(clk_b), + .data_in(data_in_b), + .address_in_r(address_in_r_b), + .address_in_w(address_in_w_b), + .data_out(data_out_b) + ); + +endmodule // double_sync_ram_sdp + + module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) (input wire clk_a, clk_b, input wire write_enable_a, write_enable_b, diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index d0eb22a475f..54f29125b45 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -1,51 +1,74 @@ -blockram_template = """\ +blockram_template = """# ====================================== design -reset; read_verilog -defer ../../common/blockram.v -chparam -set ADDRESS_WIDTH {aw} -set DATA_WIDTH {dw} {top} +chparam{param_str} {top} hierarchy -top {top} synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} -log TESTING aw:{aw} dw:{dw} top:{top}\ +log ** TESTING {top} WITH PARAMS{param_str}\ """ -blockram_tests: "list[tuple[int, int, str, list[str]]]" = [ +blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [ # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work - (10, 36, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (11, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (12, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), # larger sizes need an extra ram - (10, 48, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), - (11, 36, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), - (12, 18, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), - (12, 10, "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 48)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 10)], "sync_ram_*dp", ["-assert-count 2 t:TDP36K"]), # 4096x20bit *can* fit in 3, albeit somewhat awkwardly - (12, 20, "sync_ram_*dp", ["-assert-min 3 t:TDP36K", - "-assert-max 4 t:TDP36K"]), - # smaller sizes can still fit in one - (10, 32, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (10, 18, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (10, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (11, 16, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (11, 9, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (12, 8, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (13, 4, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (14, 2, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), - (15, 1, "sync_ram_*dp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 20)], "sync_ram_*dp", ["-assert-min 3 t:TDP36K", + "-assert-max 4 t:TDP36K"]), + + # smaller sizes can still fit in one, and assign the correct width (1, 2, 4, 8, 18 or 36) + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 32)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 24)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i"]), + ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 4)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=4 %i"]), + ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]), + ([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]), + # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) - (11, 18, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - (11, 9, "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) - (11, 18, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - (10, 36, "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + + # two disjoint 18K memories can share a single TDP36K + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), + ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 14), ("DATA_WIDTH_A", 1), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 8)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K"]), + # but only if data width is <= 18 + ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), + ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + # sharing a TDP36K sets is_split=1 + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), + ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), + # an unshared TDP36K sets is_split=0 + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), ] with open("t_mem.ys", mode="w") as f: - for (aw, dw, top, assertions) in blockram_tests: + for (params, top, assertions) in blockram_tests: + param_str = "" + for (key, val) in params: + param_str += f" -set {key} {val}" if "*" in top: star_sub = ["s", "t"] else: star_sub = [""] for sub in star_sub: print( - blockram_template.format(aw=aw, dw=dw, top=top.replace("*", sub)), + blockram_template.format(param_str=param_str, top=top.replace("*", sub)), file=f ) for assertion in assertions: - print("select {}\n".format(assertion), file=f, end=None) + print("select {}".format(assertion), file=f) + print("", file=f) From 7513bfcbfe73f5ef99ab416d10d58f5395edab88 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 30 Nov 2023 09:16:12 +1300 Subject: [PATCH 22/39] quicklogic: fix double width read --- tests/arch/common/blockram.v | 49 +++++++++++-------- .../quicklogic/qlf_k6n10f/gen_memories.py | 2 +- 2 files changed, 29 insertions(+), 22 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index c37074382b2..43a6864d2a3 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -71,27 +71,34 @@ endmodule // sync_ram_sdp_wwr module sync_ram_sdp_wrr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // rd=16, ra=9 - (input wire clk, write_enable, - input wire [DATA_WIDTH-1:0] data_in, - input wire [ADDRESS_WIDTH-1:0] address_in_w, - input wire [ADDRESS_WIDTH-2:0] address_in_r, - output wire [(DATA_WIDTH*1)-1:0] data_out); - - localparam WORD = (DATA_WIDTH-1); - localparam DEPTH = (2**ADDRESS_WIDTH-1); - - reg [WORD:0] data_out_r0; - reg [WORD:0] data_out_r1; - reg [WORD:0] memory [0:DEPTH]; - - always @(posedge clk) begin - if (write_enable) - memory[address_in_w] <= data_in; - data_out_r0 <= memory[address_in_r<<1+0]; - data_out_r1 <= memory[address_in_r<<1+1]; - end - - assign data_out = {data_out_r0, data_out_r1}; +( + input wire clk_w, clk_r, write_enable, + input wire [DATA_WIDTH-1:0] data_in, + input wire [ADDRESS_WIDTH-1:0] address_in_w, + input wire [ADDRESS_WIDTH_R-1:0] address_in_r, + output wire [WORD-1:0] data_out +); + localparam ADDRESS_WIDTH_R = ADDRESS_WIDTH-1; + localparam HWORD = DATA_WIDTH; + localparam WORD = 2*DATA_WIDTH; + localparam DEPTH = 2**ADDRESS_WIDTH_R; + + reg [WORD-1:0] data_out_r; + reg [WORD-1:0] memory [0:DEPTH-1]; + + always @(posedge clk_w) begin + if (write_enable) + if (address_in_w[0]) // upper HWORD + memory[address_in_w>>1][WORD-1:HWORD] <= data_in; + else // lower HWORD + memory[address_in_w>>1][HWORD-1:0] <= data_in; + end + + always @(posedge clk_r) begin + data_out_r <= memory[address_in_r]; + end + + assign data_out = data_out_r; endmodule // sync_ram_sdp_wrr diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 54f29125b45..e4becb77dfc 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -36,7 +36,7 @@ ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 9)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), # 2x read width (1024x36bit read / 2048x18bit write = 1TDP36K) ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), # two disjoint 18K memories can share a single TDP36K ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), From 1a843b2a86a8829a9d1dea94e76f8dd2731be2f7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 30 Nov 2023 11:17:24 +1300 Subject: [PATCH 23/39] quicklogic: testing 1:4 assymetric memory --- tests/arch/common/blockram.v | 74 ++++++++++++------- .../quicklogic/qlf_k6n10f/gen_memories.py | 46 ++++++++++-- 2 files changed, 88 insertions(+), 32 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 43a6864d2a3..c7e5aca052d 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,57 +45,77 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp -module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) // wd=16, wa=9 - (input wire clk, write_enable, - input wire [(DATA_WIDTH*2)-1:0] data_in, - input wire [ADDRESS_WIDTH-2:0] address_in_w, - input wire [ADDRESS_WIDTH-1:0] address_in_r, - output wire [DATA_WIDTH-1:0] data_out); +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, WRITE_SHIFT=1) // wd=16, wa=9 +( + input wire clk_w, clk_r, write_enable, + input wire [WORD-1:0] data_in, + input wire [ADDRESS_WIDTH_W-1:0] address_in_w, + input wire [ADDRESS_WIDTH-1:0] address_in_r, + output wire [DATA_WIDTH-1:0] data_out +); - localparam WORD = ((DATA_WIDTH*2)-1); - localparam DEPTH = (2**(ADDRESS_WIDTH-1)-1); + localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-WRITE_SHIFT; + localparam BYTE = DATA_WIDTH; + localparam WORD = DATA_WIDTH<>1]; - end + always @(posedge clk_w) begin + if (write_enable) + memory[address_in_w] <= data_in; + end + + always @(posedge clk_r) begin + data_out_r <= memory[address_in_r>>WRITE_SHIFT]; + end - assign data_out = address_in_r[0] ? data_out_r[WORD:DATA_WIDTH] : data_out_r[DATA_WIDTH-1:0]; + wire [WRITE_SHIFT-1:0] inner_address; + assign inner_address = address_in_r[WRITE_SHIFT-1:0]; + genvar i; + generate + for (i=0; i>READ_SHIFT; + assign inner_address = address_in_w[READ_SHIFT-1:0]; + always @(posedge clk_w) begin if (write_enable) - if (address_in_w[0]) // upper HWORD - memory[address_in_w>>1][WORD-1:HWORD] <= data_in; - else // lower HWORD - memory[address_in_w>>1][HWORD-1:0] <= data_in; + for (i=0; i Date: Thu, 30 Nov 2023 11:41:41 +1300 Subject: [PATCH 24/39] quicklogic: testing port widths on split rams --- .../arch/quicklogic/qlf_k6n10f/gen_memories.py | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 7dcf2bc8947..3b23254a7c7 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -84,11 +84,29 @@ # but only if data width is <= 18 ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + # sharing a TDP36K sets is_split=1 ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), # an unshared TDP36K sets is_split=0 ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), + + # sharing a TDP36K sets correct port widths + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8), ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9 %i " + + "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9 %i %u", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 12), ("DATA_WIDTH_A", 4), ("DATA_WIDTH_B", 12), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=4 %i a:port_a2_width=18 %i " + + "t:TDP36K a:port_a2_width=4 %i a:port_a1_width=18 %i %u", + "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH_A", 13), ("DATA_WIDTH_A", 2), ("DATA_WIDTH_B", 1), ("ADDRESS_WIDTH_B", 14)], "double_sync_ram_sdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=2 %i a:port_a2_width=1 %i " + + "t:TDP36K a:port_a2_width=2 %i a:port_a1_width=1 %i %u", + "-assert-count 1 t:TDP36K"]), ] with open("t_mem.ys", mode="w") as f: From 8ded7020f46113a0a7a27441029e19df411ec940 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 30 Nov 2023 12:36:21 +1300 Subject: [PATCH 25/39] tests: asymmetric sync rams now correctly asymmetric Also both use the same named parameters for better mirroring. --- tests/arch/common/blockram.v | 57 +++++++++++++++--------------------- 1 file changed, 23 insertions(+), 34 deletions(-) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index c7e5aca052d..09bc7786346 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -45,7 +45,7 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_sdp -module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, WRITE_SHIFT=1) // wd=16, wa=9 +module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, SHIFT_VAL=1) // wd=16, wa=9 ( input wire clk_w, clk_r, write_enable, input wire [WORD-1:0] data_in, @@ -54,36 +54,32 @@ module sync_ram_sdp_wwr #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10, WRITE_SHIFT= output wire [DATA_WIDTH-1:0] data_out ); - localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-WRITE_SHIFT; + localparam ADDRESS_WIDTH_W = ADDRESS_WIDTH-SHIFT_VAL; localparam BYTE = DATA_WIDTH; - localparam WORD = DATA_WIDTH<>WRITE_SHIFT]; + data_out_r <= memory[address_in_r]; end - wire [WRITE_SHIFT-1:0] inner_address; - assign inner_address = address_in_r[WRITE_SHIFT-1:0]; - genvar i; - generate - for (i=0; i>READ_SHIFT; - assign inner_address = address_in_w[READ_SHIFT-1:0]; + reg [BYTE-1:0] memory [0:DEPTH-1]; always @(posedge clk_w) begin - if (write_enable) - for (i=0; i Date: Thu, 30 Nov 2023 12:41:03 +1300 Subject: [PATCH 26/39] quicklogic: wildcard asymmetric memory tests --- .../quicklogic/qlf_k6n10f/gen_memories.py | 89 +++++++++---------- 1 file changed, 40 insertions(+), 49 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 3b23254a7c7..353843b7898 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -31,48 +31,35 @@ ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 2)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=2 %i"]), ([("ADDRESS_WIDTH", 15), ("DATA_WIDTH", 1)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=1 %i"]), - # 2x write width (1024x36bit write / 2048x18bit read = 1TDP36K) - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - # same for read - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + # 2x asymmetric (1024x36bit write / 2048x18bit read or vice versa = 1TDP36K) + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), - # 4x write width (1024x36bit write / 4096x9bit read = 1TDP36K) - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - # and again for read - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - - # etc - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), + # 4x asymmetric (1024x36bit write / 4096x9bit read or vice versa = 1TDP36K) + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 4), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), # can also use an extra TDP36K for higher width - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 1)], "sync_ram_sdp_wwr", ["-assert-count 2 t:TDP36K"]), - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ( "READ_SHIFT", 1)], "sync_ram_sdp_wrr", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 16), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 8), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 1)], "sync_ram_sdp_w*r", ["-assert-count 2 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]), + ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ("SHIFT_VAL", 2)], "sync_ram_sdp_w*r", ["-assert-count 4 t:TDP36K"]), - # not sure why these are different but apparently wide writes pack better? - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 2 t:TDP36K"]), - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 4 t:TDP36K"]), - ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 2)], "sync_ram_sdp_wwr", ["-assert-count 2 t:TDP36K"]), - ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36), ( "READ_SHIFT", 2)], "sync_ram_sdp_wrr", ["-assert-count 4 t:TDP36K"]), + # # SHIFT=0 should be identical to sync_ram_sdp + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("SHIFT_VAL", 0)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K"]), - # SHIFT=0 should be identical to sync_ram_sdp - ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ( "READ_SHIFT", 0)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ( "READ_SHIFT", 0)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K"]), - # but WRITE_SHIFT=0 doesn't generate any read circuitry and optimises the memory away -# ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36), ("WRITE_SHIFT", 0)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), -# ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18), ("WRITE_SHIFT", 0)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K"]), + # asymmetric memories assign different port widths on a and b ports + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=9 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wwr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=36 %i a:port_b_width=9 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=18 %i a:port_b_width=36 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 1)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=18 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 9), ("SHIFT_VAL", 2)], "sync_ram_sdp_wrr", ["-assert-count 1 t:TDP36K", "-assert-count 1 t:TDP36K a:port_a_width=9 %i a:port_b_width=36 %i"]), # two disjoint 18K memories can share a single TDP36K ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), @@ -90,6 +77,7 @@ ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), # an unshared TDP36K sets is_split=0 ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), # sharing a TDP36K sets correct port widths ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", @@ -114,15 +102,18 @@ param_str = "" for (key, val) in params: param_str += f" -set {key} {val}" - if "*" in top: - star_sub = ["s", "t"] - else: - star_sub = [""] - for sub in star_sub: - print( - blockram_template.format(param_str=param_str, top=top.replace("*", sub)), - file=f - ) - for assertion in assertions: - print("select {}".format(assertion), file=f) - print("", file=f) + dp_subs = [""] + if "*dp" in top: + dp_subs = ["sdp", "tdp"] + wr_subs = [""] + if "w*r" in top: + wr_subs = ["wwr", "wrr"] + for db_sub in dp_subs: + for wr_sub in wr_subs: + print( + blockram_template.format(param_str=param_str, top=top.replace("*dp", db_sub).replace("w*r", wr_sub)), + file=f + ) + for assertion in assertions: + print("select {}".format(assertion), file=f) + print("", file=f) From f9c897812826655c61af63fa24361acdc0432d37 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 30 Nov 2023 19:35:43 +0100 Subject: [PATCH 27/39] add example memory test --- techlibs/quicklogic/Makefile.inc | 5 +- techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v | 344 ++++++++++ .../quicklogic/qlf_k6n10f/sram1024x18_mem.v | 64 ++ techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v | 620 ++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v | 77 +++ tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 5 + .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 99 +++ 7 files changed, 1213 insertions(+), 1 deletion(-) create mode 100644 techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v create mode 100644 techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v create mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v create mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys create mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v diff --git a/techlibs/quicklogic/Makefile.inc b/techlibs/quicklogic/Makefile.inc index 852a8a77a88..58dfc5b45f2 100644 --- a/techlibs/quicklogic/Makefile.inc +++ b/techlibs/quicklogic/Makefile.inc @@ -37,4 +37,7 @@ $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ffs_map.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_sim.v)) $(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_map.v)) -$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) \ No newline at end of file +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v)) +$(eval $(call add_share_file,share/quicklogic/qlf_k6n10f,techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v)) \ No newline at end of file diff --git a/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v b/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v new file mode 100644 index 00000000000..68c2eb0aa13 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v @@ -0,0 +1,344 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module TDP18K_FIFO ( + RMODE_A_i, + RMODE_B_i, + WMODE_A_i, + WMODE_B_i, + WEN_A_i, + WEN_B_i, + REN_A_i, + REN_B_i, + CLK_A_i, + CLK_B_i, + BE_A_i, + BE_B_i, + ADDR_A_i, + ADDR_B_i, + WDATA_A_i, + WDATA_B_i, + RDATA_A_o, + RDATA_B_o, + EMPTY_o, + EPO_o, + EWM_o, + UNDERRUN_o, + FULL_o, + FMO_o, + FWM_o, + OVERRUN_o, + FLUSH_ni, + FMODE_i, +); + parameter SYNC_FIFO_i = 1'b0; + parameter POWERDN_i = 1'b0; + parameter SLEEP_i = 1'b0; + parameter PROTECT_i = 1'b0; + parameter UPAF_i = 11'b0; + parameter UPAE_i = 11'b0; + parameter [18*1024-1:0] INIT_i = 18431'bx; + + input wire [2:0] RMODE_A_i; + input wire [2:0] RMODE_B_i; + input wire [2:0] WMODE_A_i; + input wire [2:0] WMODE_B_i; + input wire WEN_A_i; + input wire WEN_B_i; + input wire REN_A_i; + input wire REN_B_i; + (* clkbuf_sink *) + input wire CLK_A_i; + (* clkbuf_sink *) + input wire CLK_B_i; + input wire [1:0] BE_A_i; + input wire [1:0] BE_B_i; + input wire [13:0] ADDR_A_i; + input wire [13:0] ADDR_B_i; + input wire [17:0] WDATA_A_i; + input wire [17:0] WDATA_B_i; + output reg [17:0] RDATA_A_o; + output reg [17:0] RDATA_B_o; + output wire EMPTY_o; + output wire EPO_o; + output wire EWM_o; + output wire UNDERRUN_o; + output wire FULL_o; + output wire FMO_o; + output wire FWM_o; + output wire OVERRUN_o; + input wire FLUSH_ni; + input wire FMODE_i; + reg [17:0] wmsk_a; + reg [17:0] wmsk_b; + wire [8:0] addr_a; + wire [8:0] addr_b; + reg [4:0] addr_a_d; + reg [4:0] addr_b_d; + wire [17:0] ram_rdata_a; + wire [17:0] ram_rdata_b; + reg [17:0] aligned_wdata_a; + reg [17:0] aligned_wdata_b; + wire ren_o; + wire [10:0] ff_raddr; + wire [10:0] ff_waddr; + wire [13:0] ram_addr_a; + wire [13:0] ram_addr_b; + wire [3:0] ram_waddr_a; + wire [3:0] ram_waddr_b; + wire initn; + wire smux_rclk; + wire smux_wclk; + wire real_fmode; + wire [3:0] raw_fflags; + reg [1:0] fifo_rmode; + reg [1:0] fifo_wmode; + wire smux_clk_a; + wire smux_clk_b; + wire ram_ren_a; + wire ram_ren_b; + wire ram_wen_a; + wire ram_wen_b; + wire cen_a; + wire cen_b; + wire cen_a_n; + wire cen_b_n; + wire ram_wen_a_n; + wire ram_wen_b_n; + localparam MODE_9 = 3'b001; + always @(*) begin + fifo_rmode = (RMODE_B_i == MODE_9 ? 2'b10 : 2'b01); + fifo_wmode = (WMODE_A_i == MODE_9 ? 2'b10 : 2'b01); + end + assign smux_clk_a = CLK_A_i; + assign smux_clk_b = CLK_B_i; + assign real_fmode = FMODE_i; + assign ram_ren_b = real_fmode ? ren_o : REN_B_i; + assign ram_wen_a = FMODE_i ? ~FULL_o & WEN_A_i : WEN_A_i; + assign ram_ren_a = FMODE_i ? 0 : REN_A_i; + assign ram_wen_b = FMODE_i ? 1'b0 : WEN_B_i; + assign cen_b = ram_ren_b | ram_wen_b; + assign cen_a = ram_ren_a | ram_wen_a; + assign ram_waddr_b = real_fmode ? {ff_raddr[0], 3'b000} : ADDR_B_i[3:0]; + assign ram_waddr_a = real_fmode ? {ff_waddr[0], 3'b000} : ADDR_A_i[3:0]; + assign ram_addr_b = real_fmode ? {ff_raddr[10:0], 3'h0} : {ADDR_B_i[13:4], addr_b_d[3:0]}; + assign ram_addr_a = real_fmode ? {ff_waddr[10:0], 3'h0} : {ADDR_A_i[13:4], addr_a_d[3:0]}; + always @(posedge CLK_A_i) addr_a_d[3:0] <= ADDR_A_i[3:0]; + always @(posedge CLK_B_i) addr_b_d[3:0] <= ADDR_B_i[3:0]; + assign cen_a_n = ~cen_a; + assign ram_wen_a_n = ~ram_wen_a; + assign cen_b_n = ~cen_b; + assign ram_wen_b_n = ~ram_wen_b; + + sram1024x18 #( + .init(INIT_i) + ) uram( + .clk_a(smux_clk_a), + .cen_a(cen_a_n), + .wen_a(ram_wen_a_n), + .addr_a(ram_addr_a[13:4]), + .wmsk_a(wmsk_a), + .wdata_a(aligned_wdata_a), + .rdata_a(ram_rdata_a), + .clk_b(smux_clk_b), + .cen_b(cen_b_n), + .wen_b(ram_wen_b_n), + .addr_b(ram_addr_b[13:4]), + .wmsk_b(wmsk_b), + .wdata_b(aligned_wdata_b), + .rdata_b(ram_rdata_b) + ); + fifo_ctl #( + .ADDR_WIDTH(11), + .FIFO_WIDTH(2), + .DEPTH(6) + ) fifo_ctl( + .rclk(smux_clk_b), + .rst_R_n(FLUSH_ni), + .wclk(smux_clk_a), + .rst_W_n(FLUSH_ni), + .ren(REN_B_i), + .wen(ram_wen_a), + .sync(SYNC_FIFO_i), + .rmode(fifo_rmode), + .wmode(fifo_wmode), + .ren_o(ren_o), + .fflags({FULL_o, FMO_o, FWM_o, OVERRUN_o, EMPTY_o, EPO_o, EWM_o, UNDERRUN_o}), + .raddr(ff_raddr), + .waddr(ff_waddr), + .upaf(UPAF_i), + .upae(UPAE_i) + ); + localparam MODE_1 = 3'b101; + localparam MODE_18 = 3'b010; + localparam MODE_2 = 3'b110; + localparam MODE_4 = 3'b100; + always @(*) begin : WDATA_MODE_SEL + if (ram_wen_a == 1) begin + case (WMODE_A_i) + MODE_18: begin + aligned_wdata_a = WDATA_A_i; + {wmsk_a[17], wmsk_a[15:8]} = (FMODE_i ? 9'h000 : (BE_A_i[1] ? 9'h000 : 9'h1ff)); + {wmsk_a[16], wmsk_a[7:0]} = (FMODE_i ? 9'h000 : (BE_A_i[0] ? 9'h000 : 9'h1ff)); + end + MODE_9: begin + aligned_wdata_a = {{2 {WDATA_A_i[16]}}, {2 {WDATA_A_i[7:0]}}}; + {wmsk_a[17], wmsk_a[15:8]} = (ram_waddr_a[3] ? 9'h000 : 9'h1ff); + {wmsk_a[16], wmsk_a[7:0]} = (ram_waddr_a[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_a = {2'b00, {4 {WDATA_A_i[3:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:12] = (ram_waddr_a[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_a[11:8] = (ram_waddr_a[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_a[7:4] = (ram_waddr_a[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_a[3:0] = (ram_waddr_a[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_a = {2'b00, {8 {WDATA_A_i[1:0]}}}; + wmsk_a[17:16] = 2'b00; + wmsk_a[15:14] = (ram_waddr_a[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_a[13:12] = (ram_waddr_a[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_a[11:10] = (ram_waddr_a[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_a[9:8] = (ram_waddr_a[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_a[7:6] = (ram_waddr_a[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_a[5:4] = (ram_waddr_a[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_a[3:2] = (ram_waddr_a[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_a[1:0] = (ram_waddr_a[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_a = {2'b00, {16 {WDATA_A_i[0]}}}; + wmsk_a = 18'h0ffff; + wmsk_a[{1'b0, ram_waddr_a[3:0]}] = 0; + end + default: wmsk_a = 18'h3ffff; + endcase + end + else begin + aligned_wdata_a = 18'h00000; + wmsk_a = 18'h3ffff; + end + if (ram_wen_b == 1) + case (WMODE_B_i) + MODE_18: begin + aligned_wdata_b = WDATA_B_i; + {wmsk_b[17], wmsk_b[15:8]} = (BE_B_i[1] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (BE_B_i[0] ? 9'h000 : 9'h1ff); + end + MODE_9: begin + aligned_wdata_b = {{2 {WDATA_B_i[16]}}, {2 {WDATA_B_i[7:0]}}}; + {wmsk_b[17], wmsk_b[15:8]} = (ram_waddr_b[3] ? 9'h000 : 9'h1ff); + {wmsk_b[16], wmsk_b[7:0]} = (ram_waddr_b[3] ? 9'h1ff : 9'h000); + end + MODE_4: begin + aligned_wdata_b = {2'b00, {4 {WDATA_B_i[3:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:12] = (ram_waddr_b[3:2] == 2'b11 ? 4'h0 : 4'hf); + wmsk_b[11:8] = (ram_waddr_b[3:2] == 2'b10 ? 4'h0 : 4'hf); + wmsk_b[7:4] = (ram_waddr_b[3:2] == 2'b01 ? 4'h0 : 4'hf); + wmsk_b[3:0] = (ram_waddr_b[3:2] == 2'b00 ? 4'h0 : 4'hf); + end + MODE_2: begin + aligned_wdata_b = {2'b00, {8 {WDATA_B_i[1:0]}}}; + wmsk_b[17:16] = 2'b00; + wmsk_b[15:14] = (ram_waddr_b[3:1] == 3'b111 ? 2'h0 : 2'h3); + wmsk_b[13:12] = (ram_waddr_b[3:1] == 3'b110 ? 2'h0 : 2'h3); + wmsk_b[11:10] = (ram_waddr_b[3:1] == 3'b101 ? 2'h0 : 2'h3); + wmsk_b[9:8] = (ram_waddr_b[3:1] == 3'b100 ? 2'h0 : 2'h3); + wmsk_b[7:6] = (ram_waddr_b[3:1] == 3'b011 ? 2'h0 : 2'h3); + wmsk_b[5:4] = (ram_waddr_b[3:1] == 3'b010 ? 2'h0 : 2'h3); + wmsk_b[3:2] = (ram_waddr_b[3:1] == 3'b001 ? 2'h0 : 2'h3); + wmsk_b[1:0] = (ram_waddr_b[3:1] == 3'b000 ? 2'h0 : 2'h3); + end + MODE_1: begin + aligned_wdata_b = {2'b00, {16 {WDATA_B_i[0]}}}; + wmsk_b = 18'h0ffff; + wmsk_b[{1'b0, ram_waddr_b[3:0]}] = 0; + end + default: wmsk_b = 18'h3ffff; + endcase + else begin + aligned_wdata_b = 18'b000000000000000000; + wmsk_b = 18'h3ffff; + end + end + always @(*) begin : RDATA_A_MODE_SEL + case (RMODE_A_i) + default: RDATA_A_o = 18'h00000; + MODE_18: RDATA_A_o = ram_rdata_a; + MODE_9: begin + {RDATA_A_o[17], RDATA_A_o[15:8]} = 9'h000; + {RDATA_A_o[16], RDATA_A_o[7:0]} = (ram_addr_a[3] ? {ram_rdata_a[17], ram_rdata_a[15:8]} : {ram_rdata_a[16], ram_rdata_a[7:0]}); + end + MODE_4: begin + RDATA_A_o[17:4] = 14'h0000; + case (ram_addr_a[3:2]) + 3: RDATA_A_o[3:0] = ram_rdata_a[15:12]; + 2: RDATA_A_o[3:0] = ram_rdata_a[11:8]; + 1: RDATA_A_o[3:0] = ram_rdata_a[7:4]; + 0: RDATA_A_o[3:0] = ram_rdata_a[3:0]; + endcase + end + MODE_2: begin + RDATA_A_o[17:2] = 16'h0000; + case (ram_addr_a[3:1]) + 7: RDATA_A_o[1:0] = ram_rdata_a[15:14]; + 6: RDATA_A_o[1:0] = ram_rdata_a[13:12]; + 5: RDATA_A_o[1:0] = ram_rdata_a[11:10]; + 4: RDATA_A_o[1:0] = ram_rdata_a[9:8]; + 3: RDATA_A_o[1:0] = ram_rdata_a[7:6]; + 2: RDATA_A_o[1:0] = ram_rdata_a[5:4]; + 1: RDATA_A_o[1:0] = ram_rdata_a[3:2]; + 0: RDATA_A_o[1:0] = ram_rdata_a[1:0]; + endcase + end + MODE_1: begin + RDATA_A_o[17:1] = 17'h00000; + RDATA_A_o[0] = ram_rdata_a[ram_addr_a[3:0]]; + end + endcase + end + always @(*) + case (RMODE_B_i) + default: RDATA_B_o = 18'h15566; + MODE_18: RDATA_B_o = ram_rdata_b; + MODE_9: begin + {RDATA_B_o[17], RDATA_B_o[15:8]} = 9'b000000000; + {RDATA_B_o[16], RDATA_B_o[7:0]} = (ram_addr_b[3] ? {ram_rdata_b[17], ram_rdata_b[15:8]} : {ram_rdata_b[16], ram_rdata_b[7:0]}); + end + MODE_4: + case (ram_addr_b[3:2]) + 3: RDATA_B_o[3:0] = ram_rdata_b[15:12]; + 2: RDATA_B_o[3:0] = ram_rdata_b[11:8]; + 1: RDATA_B_o[3:0] = ram_rdata_b[7:4]; + 0: RDATA_B_o[3:0] = ram_rdata_b[3:0]; + endcase + MODE_2: + case (ram_addr_b[3:1]) + 7: RDATA_B_o[1:0] = ram_rdata_b[15:14]; + 6: RDATA_B_o[1:0] = ram_rdata_b[13:12]; + 5: RDATA_B_o[1:0] = ram_rdata_b[11:10]; + 4: RDATA_B_o[1:0] = ram_rdata_b[9:8]; + 3: RDATA_B_o[1:0] = ram_rdata_b[7:6]; + 2: RDATA_B_o[1:0] = ram_rdata_b[5:4]; + 1: RDATA_B_o[1:0] = ram_rdata_b[3:2]; + 0: RDATA_B_o[1:0] = ram_rdata_b[1:0]; + endcase + MODE_1: RDATA_B_o[0] = ram_rdata_b[{1'b0, ram_addr_b[3:0]}]; + endcase +endmodule +`default_nettype none diff --git a/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v b/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v new file mode 100644 index 00000000000..86698ffefd3 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v @@ -0,0 +1,64 @@ +`default_nettype none +module sram1024x18 ( + clk_a, + cen_a, + wen_a, + addr_a, + wmsk_a, + wdata_a, + rdata_a, + clk_b, + cen_b, + wen_b, + addr_b, + wmsk_b, + wdata_b, + rdata_b +); + parameter [1024*18-1:0] init = 18431'bx; + (* clkbuf_sink *) + input wire clk_a; + input wire cen_a; + input wire wen_a; + input wire [9:0] addr_a; + input wire [17:0] wmsk_a; + input wire [17:0] wdata_a; + output reg [17:0] rdata_a; + (* clkbuf_sink *) + input wire clk_b; + input wire cen_b; + input wire wen_b; + input wire [9:0] addr_b; + input wire [17:0] wmsk_b; + input wire [17:0] wdata_b; + output reg [17:0] rdata_b; + reg [17:0] ram [1023:0]; + integer i; + initial begin + for (i = 0; i < 1024; i = i + 1) begin + ram[i] = init[18*i +: 18]; + end + end + + always @(posedge clk_a) begin + if (!cen_a) begin + if (!wen_a) + for (i = 0; i < 18; i++) begin + if (!wmsk_a[i]) ram[addr_a][i] <= wdata_a[i]; + end + rdata_a <= ram[addr_a]; + end + end + + always @(posedge clk_b) begin + if (!cen_b) begin + if (!wen_b) + for (i = 0; i < 18; i++) begin + if (!wmsk_b[i]) ram[addr_b][i] <= wdata_b[i]; + end + rdata_b <= ram[addr_b]; + end + end + +endmodule + diff --git a/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v b/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v new file mode 100644 index 00000000000..441f6bc4a81 --- /dev/null +++ b/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v @@ -0,0 +1,620 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype wire +module fifo_ctl ( + raddr, + waddr, + fflags, + ren_o, + sync, + rmode, + wmode, + rclk, + rst_R_n, + wclk, + rst_W_n, + ren, + wen, + upaf, + upae +); + parameter ADDR_WIDTH = 11; + parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; + output wire [ADDR_WIDTH - 1:0] raddr; + output wire [ADDR_WIDTH - 1:0] waddr; + output wire [7:0] fflags; + output wire ren_o; + input wire sync; + input wire [1:0] rmode; + input wire [1:0] wmode; + (* clkbuf_sink *) + input wire rclk; + input wire rst_R_n; + (* clkbuf_sink *) + input wire wclk; + input wire rst_W_n; + input wire ren; + input wire wen; + input wire [ADDR_WIDTH - 1:0] upaf; + input wire [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg [ADDR_WIDTH:0] pushtopop1; + reg [ADDR_WIDTH:0] pushtopop2; + reg [ADDR_WIDTH:0] poptopush1; + reg [ADDR_WIDTH:0] poptopush2; + wire [ADDR_WIDTH:0] pushtopop0; + wire [ADDR_WIDTH:0] poptopush0; + wire [ADDR_WIDTH:0] smux_poptopush; + wire [ADDR_WIDTH:0] smux_pushtopop; + assign smux_poptopush = (sync ? poptopush0 : poptopush2); + assign smux_pushtopop = (sync ? pushtopop0 : pushtopop2); + always @(posedge rclk or negedge rst_R_n) + if (~rst_R_n) begin + pushtopop1 <= 'h0; + pushtopop2 <= 'h0; + end + else begin + pushtopop1 = pushtopop0; + pushtopop2 = pushtopop1; + end + always @(posedge wclk or negedge rst_W_n) + if (~rst_W_n) begin + poptopush1 <= 'h0; + poptopush2 <= 'h0; + end + else begin + poptopush1 <= poptopush0; + poptopush2 <= poptopush1; + end + fifo_push #( + .ADDR_WIDTH(ADDR_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_push( + .wclk(wclk), + .wen(wen), + .rst_n(rst_W_n), + .rmode(rmode), + .wmode(wmode), + .gcout(pushtopop0), + .gcin(smux_poptopush), + .ff_waddr(waddr), + .pushflags(fflags[7:4]), + .upaf(upaf) + ); + fifo_pop #( + .ADDR_WIDTH(ADDR_WIDTH), + .FIFO_WIDTH(FIFO_WIDTH), + .DEPTH(DEPTH) + ) u_fifo_pop( + .rclk(rclk), + .ren_in(ren), + .rst_n(rst_R_n), + .rmode(rmode), + .wmode(wmode), + .ren_o(ren_o), + .gcout(poptopush0), + .gcin(smux_pushtopop), + .out_raddr(raddr), + .popflags(fflags[3:0]), + .upae(upae) + ); +endmodule +module fifo_push ( + pushflags, + gcout, + ff_waddr, + rst_n, + wclk, + wen, + rmode, + wmode, + gcin, + upaf +); + parameter ADDR_WIDTH = 11; + parameter DEPTH = 6; + output wire [3:0] pushflags; + output wire [ADDR_WIDTH:0] gcout; + output wire [ADDR_WIDTH - 1:0] ff_waddr; + input rst_n; + (* clkbuf_sink *) + input wclk; + input wen; + input [1:0] rmode; + input [1:0] wmode; + input [ADDR_WIDTH:0] gcin; + input [ADDR_WIDTH - 1:0] upaf; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg full_next; + reg full; + reg paf_next; + reg paf; + reg fmo; + reg fmo_next; + reg overflow; + reg p1; + reg p2; + reg f1; + reg f2; + reg q1; + reg q2; + reg [1:0] gmode; + reg [ADDR_WIDTH:0] waddr; + reg [ADDR_WIDTH:0] raddr; + reg [ADDR_WIDTH:0] gcout_reg; + reg [ADDR_WIDTH:0] gcout_next; + reg [ADDR_WIDTH:0] raddr_next; + reg [ADDR_WIDTH - 1:0] paf_thresh; + wire overflow_next; + wire [ADDR_WIDTH:0] waddr_next; + wire [ADDR_WIDTH:0] gc8out_next; + wire [ADDR_WIDTH - 1:0] gc16out_next; + wire [ADDR_WIDTH - 2:0] gc32out_next; + wire [ADDR_WIDTH:0] tmp; + wire [ADDR_WIDTH:0] next_count; + wire [ADDR_WIDTH:0] count; + wire [ADDR_WIDTH:0] fbytes; + genvar i; + assign next_count = fbytes - (waddr_next >= raddr_next ? waddr_next - raddr_next : (~raddr_next + waddr_next) + 1); + assign count = fbytes - (waddr >= raddr ? waddr - raddr : (~raddr + waddr) + 1); + assign fbytes = 1 << (DEPTH + 5); + always @(*) begin + paf_thresh = wmode[1] ? upaf : (wmode[0] ? upaf << 1 : upaf << 2); + end + always @(*) + case (wmode) + 2'h0, 2'h1, 2'h2: begin + full_next = (wen ? f1 : f2); + fmo_next = (wen ? p1 : p2); + paf_next = (wen ? q1 : q2); + end + default: begin + full_next = 1'b0; + fmo_next = 1'b0; + paf_next = 1'b0; + end + endcase + always @(*) begin : PUSH_FULL_FLAGS + f1 = 1'b0; + f2 = 1'b0; + p1 = 1'b0; + p2 = 1'b0; + q1 = next_count < {1'b0, paf_thresh}; + q2 = count < {1'b0, paf_thresh}; + case (wmode) + 2'h0: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:2]} == raddr_next[11:2]; + f2 = {~waddr[11], waddr[10:2]} == raddr_next[11:2]; + p1 = ((waddr_next[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; + p2 = ((waddr[10:2] + 1) & 9'h1ff) == raddr_next[10:2]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:2]} == raddr_next[10:2]; + f2 = {~waddr[10], waddr[9:2]} == raddr_next[10:2]; + p1 = ((waddr_next[9:2] + 1) & 8'hff) == raddr_next[9:2]; + p2 = ((waddr[9:2] + 1) & 8'hff) == raddr_next[9:2]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:2]} == raddr_next[9:2]; + f2 = {~waddr[9], waddr[8:2]} == raddr_next[9:2]; + p1 = ((waddr_next[8:2] + 1) & 7'h7f) == raddr_next[8:2]; + p2 = ((waddr[8:2] + 1) & 7'h7f) == raddr_next[8:2]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:2]} == raddr_next[8:2]; + f2 = {~waddr[8], waddr[7:2]} == raddr_next[8:2]; + p1 = ((waddr_next[7:2] + 1) & 6'h3f) == raddr_next[7:2]; + p2 = ((waddr[7:2] + 1) & 6'h3f) == raddr_next[7:2]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:2]} == raddr_next[7:2]; + f2 = {~waddr[7], waddr[6:2]} == raddr_next[7:2]; + p1 = ((waddr_next[6:2] + 1) & 5'h1f) == raddr_next[6:2]; + p2 = ((waddr[6:2] + 1) & 5'h1f) == raddr_next[6:2]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:2]} == raddr_next[6:2]; + f2 = {~waddr[6], waddr[5:2]} == raddr_next[6:2]; + p1 = ((waddr_next[5:2] + 1) & 4'hf) == raddr_next[5:2]; + p2 = ((waddr[5:2] + 1) & 4'hf) == raddr_next[5:2]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:2]} == raddr_next[5:2]; + f2 = {~waddr[5], waddr[4:2]} == raddr_next[5:2]; + p1 = ((waddr_next[4:2] + 1) & 3'h7) == raddr_next[4:2]; + p2 = ((waddr[4:2] + 1) & 3'h7) == raddr_next[4:2]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:2]} == raddr_next[ADDR_WIDTH:2]; + p1 = ((waddr_next[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; + p2 = ((waddr[ADDR_WIDTH - 1:2] + 1) & {ADDR_WIDTH - 2 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:2]; + end + endcase + 2'h1: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:1]} == raddr_next[11:1]; + f2 = {~waddr[11], waddr[10:1]} == raddr_next[11:1]; + p1 = ((waddr_next[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; + p2 = ((waddr[10:1] + 1) & 10'h3ff) == raddr_next[10:1]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:1]} == raddr_next[10:1]; + f2 = {~waddr[10], waddr[9:1]} == raddr_next[10:1]; + p1 = ((waddr_next[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; + p2 = ((waddr[9:1] + 1) & 9'h1ff) == raddr_next[9:1]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:1]} == raddr_next[9:1]; + f2 = {~waddr[9], waddr[8:1]} == raddr_next[9:1]; + p1 = ((waddr_next[8:1] + 1) & 8'hff) == raddr_next[8:1]; + p2 = ((waddr[8:1] + 1) & 8'hff) == raddr_next[8:1]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:1]} == raddr_next[8:1]; + f2 = {~waddr[8], waddr[7:1]} == raddr_next[8:1]; + p1 = ((waddr_next[7:1] + 1) & 7'h7f) == raddr_next[7:1]; + p2 = ((waddr[7:1] + 1) & 7'h7f) == raddr_next[7:1]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:1]} == raddr_next[7:1]; + f2 = {~waddr[7], waddr[6:1]} == raddr_next[7:1]; + p1 = ((waddr_next[6:1] + 1) & 6'h3f) == raddr_next[6:1]; + p2 = ((waddr[6:1] + 1) & 6'h3f) == raddr_next[6:1]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:1]} == raddr_next[6:1]; + f2 = {~waddr[6], waddr[5:1]} == raddr_next[6:1]; + p1 = ((waddr_next[5:1] + 1) & 5'h1f) == raddr_next[5:1]; + p2 = ((waddr[5:1] + 1) & 5'h1f) == raddr_next[5:1]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:1]} == raddr_next[5:1]; + f2 = {~waddr[5], waddr[4:1]} == raddr_next[5:1]; + p1 = ((waddr_next[4:1] + 1) & 4'hf) == raddr_next[4:1]; + p2 = ((waddr[4:1] + 1) & 4'hf) == raddr_next[4:1]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:1]} == raddr_next[ADDR_WIDTH:1]; + p1 = ((waddr_next[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; + p2 = ((waddr[ADDR_WIDTH - 1:1] + 1) & {ADDR_WIDTH - 1 {1'b1}}) == raddr_next[ADDR_WIDTH - 1:1]; + end + endcase + 2'h2: + case (DEPTH) + 3'h6: begin + f1 = {~waddr_next[11], waddr_next[10:0]} == raddr_next[11:0]; + f2 = {~waddr[11], waddr[10:0]} == raddr_next[11:0]; + p1 = ((waddr_next[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; + p2 = ((waddr[10:0] + 1) & 11'h7ff) == raddr_next[10:0]; + end + 3'h5: begin + f1 = {~waddr_next[10], waddr_next[9:0]} == raddr_next[10:0]; + f2 = {~waddr[10], waddr[9:0]} == raddr_next[10:0]; + p1 = ((waddr_next[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; + p2 = ((waddr[9:0] + 1) & 10'h3ff) == raddr_next[9:0]; + end + 3'h4: begin + f1 = {~waddr_next[9], waddr_next[8:0]} == raddr_next[9:0]; + f2 = {~waddr[9], waddr[8:0]} == raddr_next[9:0]; + p1 = ((waddr_next[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; + p2 = ((waddr[8:0] + 1) & 9'h1ff) == raddr_next[8:0]; + end + 3'h3: begin + f1 = {~waddr_next[8], waddr_next[7:0]} == raddr_next[8:0]; + f2 = {~waddr[8], waddr[7:0]} == raddr_next[8:0]; + p1 = ((waddr_next[7:0] + 1) & 8'hff) == raddr_next[7:0]; + p2 = ((waddr[7:0] + 1) & 8'hff) == raddr_next[7:0]; + end + 3'h2: begin + f1 = {~waddr_next[7], waddr_next[6:0]} == raddr_next[7:0]; + f2 = {~waddr[7], waddr[6:0]} == raddr_next[7:0]; + p1 = ((waddr_next[6:0] + 1) & 7'h7f) == raddr_next[6:0]; + p2 = ((waddr[6:0] + 1) & 7'h7f) == raddr_next[6:0]; + end + 3'h1: begin + f1 = {~waddr_next[6], waddr_next[5:0]} == raddr_next[6:0]; + f2 = {~waddr[6], waddr[5:0]} == raddr_next[6:0]; + p1 = ((waddr_next[5:0] + 1) & 6'h3f) == raddr_next[5:0]; + p2 = ((waddr[5:0] + 1) & 6'h3f) == raddr_next[5:0]; + end + 3'h0: begin + f1 = {~waddr_next[5], waddr_next[4:0]} == raddr_next[5:0]; + f2 = {~waddr[5], waddr[4:0]} == raddr_next[5:0]; + p1 = ((waddr_next[4:0] + 1) & 5'h1f) == raddr_next[4:0]; + p2 = ((waddr[4:0] + 1) & 5'h1f) == raddr_next[4:0]; + end + 3'h7: begin + f1 = {~waddr_next[ADDR_WIDTH], waddr_next[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0]; + f2 = {~waddr[ADDR_WIDTH], waddr[ADDR_WIDTH - 1:0]} == raddr_next[ADDR_WIDTH:0]; + p1 = ((waddr_next[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0]; + p2 = ((waddr[ADDR_WIDTH - 1:0] + 1) & {ADDR_WIDTH {1'b1}}) == raddr_next[ADDR_WIDTH - 1:0]; + end + endcase + 2'h3: begin + f1 = 1'b0; + f2 = 1'b0; + p1 = 1'b0; + p2 = 1'b0; + end + endcase + end + always @(*) + case (wmode) + 2'h0: gmode = 2'h0; + 2'h1: gmode = (rmode == 2'h0 ? 2'h0 : 2'h1); + 2'h2: gmode = (rmode == 2'h2 ? 2'h2 : rmode); + 2'h3: gmode = 2'h3; + endcase + assign gc8out_next = (waddr_next >> 1) ^ waddr_next; + assign gc16out_next = (waddr_next >> 2) ^ (waddr_next >> 1); + assign gc32out_next = (waddr_next >> 3) ^ (waddr_next >> 2); + always @(*) + if (wen) + case (gmode) + 2'h2: gcout_next = gc8out_next; + 2'h1: gcout_next = {1'b0, gc16out_next}; + 2'h0: gcout_next = {2'b00, gc32out_next}; + default: gcout_next = {ADDR_PLUS_ONE {1'b0}}; + endcase + else + gcout_next = {ADDR_PLUS_ONE {1'b0}}; + always @(posedge wclk or negedge rst_n) + if (~rst_n) begin + full <= 1'b0; + fmo <= 1'b0; + paf <= 1'b0; + raddr <= {ADDR_PLUS_ONE {1'b0}}; + end + else begin + full <= full_next; + fmo <= fmo_next; + paf <= paf_next; + case (gmode) + 0: raddr <= raddr_next & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 1: raddr <= raddr_next & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2: raddr <= raddr_next & {ADDR_WIDTH + 1 {1'b1}}; + 3: raddr <= 12'h000; + endcase + end + assign overflow_next = full & wen; + always @(posedge wclk or negedge rst_n) + if (~rst_n) + overflow <= 1'b0; + else if (wen == 1'b1) + overflow <= overflow_next; + always @(posedge wclk or negedge rst_n) + if (~rst_n) begin + waddr <= {ADDR_WIDTH + 1 {1'b0}}; + gcout_reg <= {ADDR_WIDTH + 1 {1'b0}}; + end + else if (wen == 1'b1) begin + waddr <= waddr_next; + gcout_reg <= gcout_next; + end + assign gcout = gcout_reg; + generate + for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1 + assign tmp[i] = ^(gcin >> i); + end + endgenerate + always @(*) + case (gmode) + 2'h0: raddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: raddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: raddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_WIDTH + 1 {1'b1}}; + default: raddr_next = {ADDR_WIDTH + 1 {1'b0}}; + endcase + assign ff_waddr = waddr[ADDR_WIDTH - 1:0]; + assign pushflags = {full, fmo, paf, overflow}; + assign waddr_next = waddr + (wmode == 2'h0 ? 'h4 : (wmode == 2'h1 ? 'h2 : 'h1)); +endmodule +module fifo_pop ( + ren_o, + popflags, + out_raddr, + gcout, + rst_n, + rclk, + ren_in, + rmode, + wmode, + gcin, + upae +); + parameter ADDR_WIDTH = 11; + parameter FIFO_WIDTH = 3'd2; + parameter DEPTH = 6; + output wire ren_o; + output wire [3:0] popflags; + output reg [ADDR_WIDTH - 1:0] out_raddr; + output wire [ADDR_WIDTH:0] gcout; + input rst_n; + (* clkbuf_sink *) + input rclk; + input ren_in; + input [1:0] rmode; + input [1:0] wmode; + input [ADDR_WIDTH:0] gcin; + input [ADDR_WIDTH - 1:0] upae; + localparam ADDR_PLUS_ONE = ADDR_WIDTH + 1; + reg empty; + reg epo; + reg pae; + reg underflow; + reg e1; + reg e2; + reg o1; + reg o2; + reg q1; + reg q2; + reg [1:0] bwl_sel; + reg [1:0] gmode; + reg [ADDR_WIDTH - 1:0] ff_raddr; + reg [ADDR_WIDTH:0] waddr; + reg [ADDR_WIDTH:0] raddr; + reg [ADDR_WIDTH:0] gcout_reg; + reg [ADDR_WIDTH:0] gcout_next; + reg [ADDR_WIDTH:0] waddr_next; + reg [ADDR_WIDTH - 1:0] pae_thresh; + wire ren_out; + wire empty_next; + wire pae_next; + wire epo_next; + wire [ADDR_WIDTH - 2:0] gc32out_next; + wire [ADDR_WIDTH - 1:0] gc16out_next; + wire [ADDR_WIDTH:0] gc8out_next; + wire [ADDR_WIDTH:0] raddr_next; + wire [ADDR_WIDTH - 1:0] ff_raddr_next; + wire [ADDR_WIDTH:0] tmp; + wire [ADDR_PLUS_ONE:0] next_count; + wire [ADDR_PLUS_ONE:0] count; + wire [ADDR_PLUS_ONE:0] fbytes; + genvar i; + assign next_count = waddr - raddr_next; + assign count = waddr - raddr; + assign fbytes = 1 << (DEPTH + 5); + always @(*) pae_thresh = rmode[1] ? upae : (rmode[0] ? upae << 1 : upae << 2); + assign ren_out = (empty ? 1'b1 : ren_in); + always @(*) + case (rmode) + 2'h0: gmode = 2'h0; + 2'h1: gmode = (wmode == 2'h0 ? 2'h0 : 2'h1); + 2'h2: gmode = (wmode == 2'h2 ? 2'h2 : wmode); + 2'h3: gmode = 2'h3; + endcase + always @(*) begin + e1 = 1'b0; + e2 = 1'b0; + o1 = 1'b0; + o2 = 1'b0; + q1 = next_count < {1'b0, pae_thresh}; + q2 = count < {1'b0, pae_thresh}; + case (rmode) + 2'h0: begin + e1 = raddr_next[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; + e2 = raddr[ADDR_WIDTH:2] == waddr_next[ADDR_WIDTH:2]; + o1 = (raddr_next[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2]; + o2 = (raddr[ADDR_WIDTH:2] + 1) == waddr_next[ADDR_WIDTH:2]; + end + 2'h1: begin + e1 = raddr_next[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1]; + e2 = raddr[ADDR_WIDTH:1] == waddr_next[ADDR_WIDTH:1]; + o1 = (raddr_next[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1]; + o2 = (raddr[ADDR_WIDTH:1] + 1) == waddr_next[ADDR_WIDTH:1]; + end + 2'h2: begin + e1 = raddr_next[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0]; + e2 = raddr[ADDR_WIDTH:0] == waddr_next[ADDR_WIDTH:0]; + o1 = (raddr_next[ADDR_WIDTH:0] + 1) == waddr_next[ADDR_WIDTH:0]; + o2 = (raddr[ADDR_WIDTH:0] + 1) == waddr_next[11:0]; + end + 2'h3: begin + e1 = 1'b0; + e2 = 1'b0; + o1 = 1'b0; + o2 = 1'b0; + end + endcase + end + assign empty_next = (ren_in & !empty ? e1 : e2); + assign epo_next = (ren_in & !empty ? o1 : o2); + assign pae_next = (ren_in & !empty ? q1 : q2); + always @(posedge rclk or negedge rst_n) + if (~rst_n) begin + empty <= 1'b1; + pae <= 1'b1; + epo <= 1'b0; + end + else begin + empty <= empty_next; + pae <= pae_next; + epo <= epo_next; + end + assign gc8out_next = (raddr_next >> 1) ^ raddr_next; + assign gc16out_next = (raddr_next >> 2) ^ (raddr_next >> 1); + assign gc32out_next = (raddr_next >> 3) ^ (raddr_next >> 2); + always @(*) + if (ren_in) + case (gmode) + 2'h2: gcout_next = gc8out_next; + 2'h1: gcout_next = {1'b0, gc16out_next}; + 2'h0: gcout_next = {2'b00, gc32out_next}; + default: gcout_next = 'h0; + endcase + else + gcout_next = 'h0; + always @(posedge rclk or negedge rst_n) + if (~rst_n) + waddr <= 12'h000; + else + waddr <= waddr_next; + always @(posedge rclk or negedge rst_n) + if (~rst_n) begin + underflow <= 1'b0; + bwl_sel <= 2'h0; + gcout_reg <= 12'h000; + end + else if (ren_in) begin + underflow <= empty; + if (!empty) begin + bwl_sel <= raddr_next[1:0]; + gcout_reg <= gcout_next; + end + end + generate + for (i = 0; i < (ADDR_WIDTH + 1); i = i + 1) begin : genblk1 + assign tmp[i] = ^(gcin >> i); + end + endgenerate + always @(*) + case (gmode) + 2'h0: waddr_next = {tmp[ADDR_WIDTH - 2:0], 2'b00} & {{ADDR_WIDTH - 1 {1'b1}}, 2'b00}; + 2'h1: waddr_next = {tmp[ADDR_WIDTH - 1:0], 1'b0} & {{ADDR_WIDTH {1'b1}}, 1'b0}; + 2'h2: waddr_next = {tmp[ADDR_WIDTH:0]} & {ADDR_PLUS_ONE {1'b1}}; + default: waddr_next = {ADDR_PLUS_ONE {1'b0}}; + endcase + assign ff_raddr_next = ff_raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); + assign raddr_next = raddr + (rmode == 2'h0 ? 'h4 : (rmode == 2'h1 ? 'h2 : 'h1)); + always @(posedge rclk or negedge rst_n) + if (~rst_n) + ff_raddr <= 1'sb0; + else if (empty & ~empty_next) + ff_raddr <= raddr_next[ADDR_WIDTH - 1:0]; + else if ((ren_in & !empty) & ~empty_next) + ff_raddr <= ff_raddr_next; + always @(posedge rclk or negedge rst_n) + if (~rst_n) + raddr <= 12'h000; + else if (ren_in & !empty) + raddr <= raddr_next; + always @(*) + case (FIFO_WIDTH) + 3'h2: out_raddr = {ff_raddr[ADDR_WIDTH - 1:1], bwl_sel[0]}; + 3'h4: out_raddr = {ff_raddr[ADDR_WIDTH - 1:2], bwl_sel}; + default: out_raddr = ff_raddr[ADDR_WIDTH - 1:0]; + endcase + assign ren_o = ren_out; + assign gcout = gcout_reg; + assign popflags = {empty, epo, pae, underflow}; +endmodule +`default_nettype none diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v new file mode 100644 index 00000000000..536cce992f0 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v @@ -0,0 +1,77 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + +module BRAM_TDP #(parameter AWIDTH = 10, +parameter DWIDTH = 36)( + clk_a, + rce_a, + ra_a, + rq_a, + wce_a, + wa_a, + wd_a, + + clk_b, + rce_b, + ra_b, + rq_b, + wce_b, + wa_b, + wd_b +); + + input clk_a; + input rce_a; + input [AWIDTH-1:0] ra_a; + output reg [DWIDTH-1:0] rq_a; + input wce_a; + input [AWIDTH-1:0] wa_a; + input [DWIDTH-1:0] wd_a; + + input clk_b; + input rce_b; + input [AWIDTH-1:0] ra_b; + output reg [DWIDTH-1:0] rq_b; + input wce_b; + input [AWIDTH-1:0] wa_b; + input [DWIDTH-1:0] wd_b; + + (* no_rw_check = 1 *) + reg [DWIDTH-1:0] memory[0:(1< 0) begin + if($past(rce_a)) + assert(rq_a == rq_a_expected[i]); + if($past(rce_b)) + assert(rq_b == rq_b_expected[i]); + end + i <= i + 1; + end +end +endmodule \ No newline at end of file From ba3be3fd1c0051e8b02b51246fbcff437418b39b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 09:47:46 +1300 Subject: [PATCH 28/39] QLF_TDP36K: test bram_tdp post synth --- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 7 +++++-- tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 4 ++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys index 89fcf447280..635769cc0d2 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys @@ -1,5 +1,8 @@ +read_verilog bram_tdp.v +hierarchy -top BRAM_TDP +synth_quicklogic -family qlf_k6n10f read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v -read_verilog -formal bram_tdp.v bram_tdp_tb.v +read_verilog -formal bram_tdp_tb.v hierarchy -top TB proc -sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd \ No newline at end of file +sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v index 0d5d9159d14..5d4fbe06779 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v @@ -63,10 +63,10 @@ wire wce_b = wce_b_testvector[i]; wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i]; wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i]; -uut #( +BRAM_TDP #( .AWIDTH(ADDR_WIDTH), .DWIDTH(DATA_WIDTH) -) BRAM_TDP ( +) uut ( .clk_a(clk), .rce_a(rce_a), .ra_a(ra_a), From 3d08ed216d8734bfd6789a0a651bda147ba8096b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 12:55:59 +1300 Subject: [PATCH 29/39] QLF_TDP36K: parameterised sim test gen Also limited to 16 tests per file to allow parallelism. Previous tests are converted to new test format with no sim test steps. --- .../quicklogic/qlf_k6n10f/gen_memories.py | 174 ++++++++++++++++-- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 73 ++++++++ 2 files changed, 227 insertions(+), 20 deletions(-) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/mem_tb.v diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 353843b7898..ea750b8ed9a 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -1,3 +1,8 @@ +from __future__ import annotations + +from dataclasses import dataclass + + blockram_template = """# ====================================== design -reset; read_verilog -defer ../../common/blockram.v chparam{param_str} {top} @@ -97,23 +102,152 @@ "-assert-count 1 t:TDP36K"]), ] -with open("t_mem.ys", mode="w") as f: - for (params, top, assertions) in blockram_tests: - param_str = "" - for (key, val) in params: - param_str += f" -set {key} {val}" - dp_subs = [""] - if "*dp" in top: - dp_subs = ["sdp", "tdp"] - wr_subs = [""] - if "w*r" in top: - wr_subs = ["wwr", "wrr"] - for db_sub in dp_subs: - for wr_sub in wr_subs: - print( - blockram_template.format(param_str=param_str, top=top.replace("*dp", db_sub).replace("w*r", wr_sub)), - file=f - ) - for assertion in assertions: - print("select {}".format(assertion), file=f) - print("", file=f) +sim_template = """\ +cd +read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +read_verilog < 1: + top_list.pop(0) + + # iterate over string substitutions + for top in top_list: + # limit number of tests per file to allow parallel make + if not f: + fn = f"t_mem{i}.ys" + f = open(fn, mode="w") + j = 0 + + # output yosys script test file + print( + blockram_template.format(param_str=param_str, top=top), + file=f + ) + for assertion in sim_test.assertions: + print("select {}".format(assertion), file=f) + print("", file=f) + + # prepare simulation tests + test_steps = sim_test.test_steps + if test_steps: + if top == "sync_ram_sdp": + uut_submodule = sync_ram_sdp_submodule + else: + raise NotImplementedError(f"missing submodule header for {top}") + mem_test_vector = "" + for step, test in enumerate(test_steps): + for key, val in test.items(): + key = test_val_map[key] + mem_test_vector += f"\\\n{key}[{step}] = 'h{val:x};" + print( + sim_template.format( + mem_test_vector=mem_test_vector, + uut_submodule=uut_submodule, + param_str=param_str, + vectorlen=len(test_steps) + 2 + ), file=f + ) + # simulation counts for 2 tests + j += 1 + + # increment test counter + j += 1 + if j >= max_j: + f = f.close() + i += 1 + +if f: + f.close() diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v new file mode 100644 index 00000000000..93ba2a31a64 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -0,0 +1,73 @@ +module TB(input clk); + +parameter ADDRESS_WIDTH = 10; +parameter DATA_WIDTH = 36; +parameter VECTORLEN = 16; + +reg rce_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; + +reg wce_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0]; + +reg rce_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; + +reg wce_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH-1:0] wd_b_testvector [VECTORLEN-1:0]; + +reg [$clog2(VECTORLEN)-1:0] i = 0; + +integer j; +initial begin + for (j = 0; j < VECTORLEN; j = j + 1) begin + rce_a_testvector[j] = 1'b0; + ra_a_testvector[j] = 10'h0; + wce_a_testvector[j] = 1'b0; + wa_a_testvector[j] = 10'h0; + rce_b_testvector[j] = 1'b0; + ra_b_testvector[j] = 10'h0; + wce_b_testvector[j] = 1'b0; + wa_b_testvector[j] = 10'h0; + + end + + `MEM_TEST_VECTOR + +end + + +wire rce_a = rce_a_testvector[i]; +wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; +wire [DATA_WIDTH-1:0] rq_a; + +wire wce_a = wce_a_testvector[i]; +wire [ADDRESS_WIDTH-1:0] wa_a = wa_a_testvector[i]; +wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; + +wire rce_b = rce_b_testvector[i]; +wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; +wire [DATA_WIDTH-1:0] rq_b; + +wire wce_b = wce_b_testvector[i]; +wire [ADDRESS_WIDTH-1:0] wa_b = wa_b_testvector[i]; +wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i]; + +`UUT_SUBMODULE + +always @(posedge clk) begin + if (i < VECTORLEN-1) begin + if (i > 0) begin + if($past(rce_a)) + assert(rq_a == rq_a_expected[i]); + if($past(rce_b)) + assert(rq_b == rq_b_expected[i]); + end + i <= i + 1; + end +end +endmodule From 7f12d0ba95d312e1cfc16b6aa4243430c5b60868 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 17:00:15 +1300 Subject: [PATCH 30/39] QLF_TDP36K: more basic tdp/sdp sim tests Adds TDP submodule to generator. Adds shorthand expected signal to testbench (mostly to make it easier when I look at the vcd dump to figure out what I did wrong in tests). --- .../quicklogic/qlf_k6n10f/gen_memories.py | 89 ++++++++++++++++++- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 6 +- 2 files changed, 90 insertions(+), 5 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index ea750b8ed9a..e1d77d9dfd0 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -132,6 +132,26 @@ );\ """ +sync_ram_tdp_submodule = """\ +sync_ram_tdp #(\\ + .ADDRESS_WIDTH(ADDRESS_WIDTH),\\ + .DATA_WIDTH(DATA_WIDTH)\\ +) uut (\\ + .clk_a(clk),\\ + .clk_b(clk),\\ + .write_enable_a(wce_a),\\ + .write_enable_b(wce_b),\\ + .read_enable_a(rce_a),\\ + .read_enable_b(rce_b),\\ + .addr_a(ra_a),\\ + .addr_b(ra_b),\\ + .read_data_a(rq_a),\\ + .read_data_b(rq_b),\\ + .write_data_a(wd_a),\\ + .write_data_b(wd_b)\\ +);\ +""" + @dataclass class TestClass: params: dict[str, int] @@ -155,20 +175,81 @@ class TestClass: } sim_tests: list[TestClass] = [ - TestClass( + TestClass( # basic SDP test + # note that the common SDP model reads every cycle, but the testbench + # still uses the rce signal to check read assertions params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36}, top="sync_ram_sdp", - assertions=["-assert-count 1 t:TDP36K"], + assertions=[], test_steps=[ {"wce_a": 1, "wa_a": 0x0A, "wd_a": 0xdeadbeef}, {"wce_a": 1, "wa_a": 0xBA, "wd_a": 0x5a5a5a5a}, {"wce_a": 1, "wa_a": 0xFF, "wd_a": 0}, - {"rce_a": 1, "ra_a": 0xA}, + {"rce_a": 1, "ra_a": 0x0A}, {"rq_a": 0xdeadbeef}, {"rce_a": 1, "ra_a": 0xFF}, {"rq_a": 0}, ] ), + TestClass( # SDP read before write + params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16}, + top="sync_ram_sdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0xA, "wd_a": 0x1234}, + {"wce_a": 1, "wa_a": 0xA, "wd_a": 0x5678, "rce_a": 1, "ra_a": 0xA}, + {"rq_a": 0x1234, "rce_a": 1, "ra_a": 0xA}, + {"rq_a": 0x5678}, + ] + ), + TestClass( # basic TDP test + # note that the testbench uses ra and wa, while the common TDP model + # uses a shared address + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36}, + top="sync_ram_tdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "ra_a": 0x0A, "wce_b": 1, "ra_b": 0xBA, + "wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a}, + {"wce_a": 1, "ra_a": 0xFF, + "wd_a": 0}, + {"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0xdeadbeef, "rq_b": 0xdeadbeef}, + {"rce_a": 1, "ra_a": 0xFF, "rce_b": 1, "ra_b": 0xBA}, + {"rq_a": 0, "rq_b": 0x5a5a5a5a}, + ] + ), + TestClass( # TDP with truncation + params={"ADDRESS_WIDTH": 4, "DATA_WIDTH": 16}, + top="sync_ram_tdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "ra_a": 0x0F, "wce_b": 1, "ra_b": 0xBA, + "wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a}, + {"wce_a": 1, "ra_a": 0xFF, + "wd_a": 0}, + {"rce_a": 1, "ra_a": 0x0F, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0, "rq_b": 0x00005a5a}, + ] + ), + TestClass( # TDP read before write + # note that the testbench uses rce and wce, while the common TDP model + # uses a single enable for write, with reads on no write + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 36}, + top="sync_ram_tdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "ra_a": 0x0A, "wce_b": 1, "ra_b": 0xBA, + "wd_a": 0xdeadbeef, "wd_b": 0x5a5a5a5a}, + {"wce_a": 1, "ra_a": 0xBA, "rce_b": 1, "ra_b": 0xBA, + "wd_a": 0xa5a5a5a5}, + { "rq_b": 0x5a5a5a5a}, + {"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0xdeadbeef, "rq_b": 0xdeadbeef}, + { "rce_b": 1, "ra_b": 0xBA}, + { "rq_b": 0xa5a5a5a5}, + ] + ), ] for (params, top, assertions) in blockram_tests: @@ -225,6 +306,8 @@ class TestClass: if test_steps: if top == "sync_ram_sdp": uut_submodule = sync_ram_sdp_submodule + elif top == "sync_ram_tdp": + uut_submodule = sync_ram_tdp_submodule else: raise NotImplementedError(f"missing submodule header for {top}") mem_test_vector = "" diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 93ba2a31a64..22ff63642ea 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -43,6 +43,7 @@ end wire rce_a = rce_a_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; +wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i]; wire [DATA_WIDTH-1:0] rq_a; wire wce_a = wce_a_testvector[i]; @@ -51,6 +52,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; +wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i]; wire [DATA_WIDTH-1:0] rq_b; wire wce_b = wce_b_testvector[i]; @@ -63,9 +65,9 @@ always @(posedge clk) begin if (i < VECTORLEN-1) begin if (i > 0) begin if($past(rce_a)) - assert(rq_a == rq_a_expected[i]); + assert(rq_a == rq_a_e); if($past(rce_b)) - assert(rq_b == rq_b_expected[i]); + assert(rq_b == rq_b_e); end i <= i + 1; end From 497cd021af5743c23a90fbe01eb2d1c9c25dedb6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 17:14:01 +1300 Subject: [PATCH 31/39] QLF_TDP36K: truncation tests matter Expected values are now stored in full precision rather than truncating to the same value as the input. i.e. 0x5a5a5a5a will truncate to 0x5a5a for write data but will remain 0x5a5a5a5a for expected read. --- tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 22ff63642ea..4572bb976bb 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -3,10 +3,11 @@ module TB(input clk); parameter ADDRESS_WIDTH = 10; parameter DATA_WIDTH = 36; parameter VECTORLEN = 16; +localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; +reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; reg wce_a_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0]; @@ -14,7 +15,7 @@ reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0]; reg rce_b_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; +reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; reg wce_b_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0]; @@ -43,7 +44,7 @@ end wire rce_a = rce_a_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; -wire [DATA_WIDTH-1:0] rq_a_e = rq_a_expected[i]; +wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i]; wire [DATA_WIDTH-1:0] rq_a; wire wce_a = wce_a_testvector[i]; @@ -52,7 +53,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; -wire [DATA_WIDTH-1:0] rq_b_e = rq_b_expected[i]; +wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i]; wire [DATA_WIDTH-1:0] rq_b; wire wce_b = wce_b_testvector[i]; From 0d1668c1ee86c9a14eddfd4bd946ea603bd48fb8 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 20:47:39 +1300 Subject: [PATCH 32/39] QLF_TDP36K: asymmetric simulation tests --- .../quicklogic/qlf_k6n10f/gen_memories.py | 88 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 1 + 2 files changed, 89 insertions(+) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index e1d77d9dfd0..eddc341c275 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -152,6 +152,38 @@ );\ """ +sync_ram_sdp_wwr_submodule = """\ +sync_ram_sdp_wwr #(\\ + .ADDRESS_WIDTH(ADDRESS_WIDTH),\\ + .DATA_WIDTH(DATA_WIDTH),\\ + .SHIFT_VAL(SHIFT_VAL)\\ +) uut (\\ + .clk_w(clk),\\ + .clk_r(clk),\\ + .write_enable(wce_a),\\ + .data_in(wd_a),\\ + .address_in_w(wa_a),\\ + .address_in_r(ra_a),\\ + .data_out(rq_a)\\ +);\ +""" + +sync_ram_sdp_wrr_submodule = """\ +sync_ram_sdp_wrr #(\\ + .ADDRESS_WIDTH(ADDRESS_WIDTH),\\ + .DATA_WIDTH(DATA_WIDTH),\\ + .SHIFT_VAL(SHIFT_VAL)\\ +) uut (\\ + .clk_w(clk),\\ + .clk_r(clk),\\ + .write_enable(wce_a),\\ + .data_in(wd_a),\\ + .address_in_w(wa_a),\\ + .address_in_r(ra_a),\\ + .data_out(rq_a)\\ +);\ +""" + @dataclass class TestClass: params: dict[str, int] @@ -250,6 +282,58 @@ class TestClass: { "rq_b": 0xa5a5a5a5}, ] ), + TestClass( # 2x wide write + params={"ADDRESS_WIDTH": 11, "DATA_WIDTH": 18, "SHIFT_VAL": 1}, + top="sync_ram_sdp_wwr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b0000000001, "wd_a": 0xdeadbeef}, + {"rce_a": 0, "ra_a": 0b00000000010}, + {"rq_a": 0xdead}, + {"rce_a": 0, "ra_a": 0b00000000011}, + {"rq_a": 0xbeef}, + ] + ), + TestClass( # 4x wide write + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 8, "SHIFT_VAL": 2}, + top="sync_ram_sdp_wwr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b000100001, "wd_a": 0xdeadbeef}, + {"rce_a": 0, "ra_a": 0b00010000100}, + {"rq_a": 0xde}, + {"rce_a": 0, "ra_a": 0b00010000101}, + {"rq_a": 0xad}, + {"rce_a": 0, "ra_a": 0b00010000110}, + {"rq_a": 0xbe}, + {"rce_a": 0, "ra_a": 0b00010000111}, + {"rq_a": 0xef}, + ] + ), + TestClass( # 2x wide read + params={"ADDRESS_WIDTH": 11, "DATA_WIDTH": 18, "SHIFT_VAL": 1}, + top="sync_ram_sdp_wrr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b00000000010, "wd_a": 0xdead}, + {"wce_a": 1, "wa_a": 0b00000000011, "wd_a": 0xbeef}, + {"rce_a": 0, "ra_a": 0b0000000001}, + {"rq_a": 0xdeadbeef}, + ] + ), + TestClass( # 4x wide read + params={"ADDRESS_WIDTH": 10, "DATA_WIDTH": 8, "SHIFT_VAL": 2}, + top="sync_ram_sdp_wrr", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0b00010000100, "wd_a": 0xde}, + {"wce_a": 1, "wa_a": 0b00010000101, "wd_a": 0xad}, + {"wce_a": 1, "wa_a": 0b00010000110, "wd_a": 0xbe}, + {"wce_a": 1, "wa_a": 0b00010000111, "wd_a": 0xef}, + {"rce_a": 0, "ra_a": 0b000100001}, + {"rq_a": 0xdeadbeef}, + ] + ), ] for (params, top, assertions) in blockram_tests: @@ -308,6 +392,10 @@ class TestClass: uut_submodule = sync_ram_sdp_submodule elif top == "sync_ram_tdp": uut_submodule = sync_ram_tdp_submodule + elif top == "sync_ram_sdp_wwr": + uut_submodule = sync_ram_sdp_wwr_submodule + elif top == "sync_ram_sdp_wrr": + uut_submodule = sync_ram_sdp_wrr_submodule else: raise NotImplementedError(f"missing submodule header for {top}") mem_test_vector = "" diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 4572bb976bb..9a44243f8ba 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -3,6 +3,7 @@ module TB(input clk); parameter ADDRESS_WIDTH = 10; parameter DATA_WIDTH = 36; parameter VECTORLEN = 16; +parameter SHIFT_VAL = 0; localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; From 509d1765234d207183de81fd66b8eda478d124e6 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 1 Dec 2023 21:16:58 +1300 Subject: [PATCH 33/39] attempting to sim split memory tests and failing --- .../quicklogic/qlf_k6n10f/gen_memories.py | 39 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 32 ++++++++------- 2 files changed, 57 insertions(+), 14 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index eddc341c275..631289800f0 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -113,6 +113,7 @@ EOF read_verilog -defer -formal mem_tb.v chparam{param_str} -set VECTORLEN {vectorlen} TB +read_verilog +/quicklogic/qlf_k6n10f/cells_sim.v hierarchy -top TB -check proc sim -clock clk -n {vectorlen} -assert @@ -184,6 +185,28 @@ );\ """ +double_sync_ram_sdp_submodule = """\ +double_sync_ram_sdp #(\\ + .ADDRESS_WIDTH_A(ADDRESS_WIDTH_A),\\ + .DATA_WIDTH_A(DATA_WIDTH_A),\\ + .ADDRESS_WIDTH_B(ADDRESS_WIDTH_B),\\ + .DATA_WIDTH_B(DATA_WIDTH_B)\\ +) uut (\\ + .clk_a(clk),\\ + .write_enable_a(wce_a),\\ + .address_in_w_a(wa_a),\\ + .address_in_r_a(ra_a),\\ + .data_in_a(wd_a),\\ + .data_out_b(rq_b),\\ + .clk_b(clk),\\ + .write_enable_b(wce_b),\\ + .address_in_w_b(wa_b),\\ + .address_in_r_b(ra_b),\\ + .data_in_b(wd_b),\\ + .data_out_b(rq_b)\\ +);\ +""" + @dataclass class TestClass: params: dict[str, int] @@ -334,6 +357,20 @@ class TestClass: {"rq_a": 0xdeadbeef}, ] ), + TestClass( # basic split SDP test + params={"ADDRESS_WIDTH_A": 10, "DATA_WIDTH_A": 16, + "ADDRESS_WIDTH_B": 10, "DATA_WIDTH_B": 16}, + top="double_sync_ram_sdp", + assertions=[], + test_steps=[ + {"wce_a": 1, "wa_a": 0x0A, "wce_b": 1, "wa_b": 0xBA, + "wd_a": 0x1234, "wd_b": 0x4567}, + {"wce_a": 1, "wa_a": 0xFF, "wce_b": 1, "wa_b": 0x0A, + "wd_a": 0, "wd_b": 0xbeef}, + {"rce_a": 1, "ra_a": 0x0A, "rce_b": 1, "ra_b": 0x0A}, + {"rq_a": 0x1234, "rq_b": 0xbeef}, + ] + ), ] for (params, top, assertions) in blockram_tests: @@ -396,6 +433,8 @@ class TestClass: uut_submodule = sync_ram_sdp_wwr_submodule elif top == "sync_ram_sdp_wrr": uut_submodule = sync_ram_sdp_wrr_submodule + elif top == "double_sync_ram_sdp": + uut_submodule = double_sync_ram_sdp_submodule else: raise NotImplementedError(f"missing submodule header for {top}") mem_test_vector = "" diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 9a44243f8ba..cb64269a17c 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -1,26 +1,30 @@ module TB(input clk); parameter ADDRESS_WIDTH = 10; +parameter ADDRESS_WIDTH_A = ADDRESS_WIDTH; +parameter ADDRESS_WIDTH_B = ADDRESS_WIDTH; parameter DATA_WIDTH = 36; +parameter DATA_WIDTH_A = DATA_WIDTH; +parameter DATA_WIDTH_B = DATA_WIDTH; parameter VECTORLEN = 16; parameter SHIFT_VAL = 0; localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] ra_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0]; reg [MAX_WIDTH-1:0] rq_a_expected [VECTORLEN-1:0]; reg wce_a_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] wa_a_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] wd_a_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_A-1:0] wa_a_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH_A-1:0] wd_a_testvector [VECTORLEN-1:0]; reg rce_b_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] ra_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_B-1:0] ra_b_testvector [VECTORLEN-1:0]; reg [MAX_WIDTH-1:0] rq_b_expected [VECTORLEN-1:0]; reg wce_b_testvector [VECTORLEN-1:0]; -reg [ADDRESS_WIDTH-1:0] wa_b_testvector [VECTORLEN-1:0]; -reg [DATA_WIDTH-1:0] wd_b_testvector [VECTORLEN-1:0]; +reg [ADDRESS_WIDTH_B-1:0] wa_b_testvector [VECTORLEN-1:0]; +reg [DATA_WIDTH_B-1:0] wd_b_testvector [VECTORLEN-1:0]; reg [$clog2(VECTORLEN)-1:0] i = 0; @@ -44,22 +48,22 @@ end wire rce_a = rce_a_testvector[i]; -wire [ADDRESS_WIDTH-1:0] ra_a = ra_a_testvector[i]; +wire [ADDRESS_WIDTH_A-1:0] ra_a = ra_a_testvector[i]; wire [MAX_WIDTH-1:0] rq_a_e = rq_a_expected[i]; -wire [DATA_WIDTH-1:0] rq_a; +wire [DATA_WIDTH_A-1:0] rq_a; wire wce_a = wce_a_testvector[i]; -wire [ADDRESS_WIDTH-1:0] wa_a = wa_a_testvector[i]; -wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; +wire [ADDRESS_WIDTH_A-1:0] wa_a = wa_a_testvector[i]; +wire [DATA_WIDTH_A-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; -wire [ADDRESS_WIDTH-1:0] ra_b = ra_b_testvector[i]; +wire [ADDRESS_WIDTH_B-1:0] ra_b = ra_b_testvector[i]; wire [MAX_WIDTH-1:0] rq_b_e = rq_b_expected[i]; -wire [DATA_WIDTH-1:0] rq_b; +wire [DATA_WIDTH_B-1:0] rq_b; wire wce_b = wce_b_testvector[i]; -wire [ADDRESS_WIDTH-1:0] wa_b = wa_b_testvector[i]; -wire [DATA_WIDTH-1:0] wd_b = wd_b_testvector[i]; +wire [ADDRESS_WIDTH_B-1:0] wa_b = wa_b_testvector[i]; +wire [DATA_WIDTH_B-1:0] wd_b = wd_b_testvector[i]; `UUT_SUBMODULE From 3c5b0ab1641409a09252b488c7f08ced631753d8 Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Fri, 1 Dec 2023 10:47:39 +0100 Subject: [PATCH 34/39] fix test setup for synth_quicklogic memory tests --- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 5 +- .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 2 +- .../quicklogic/qlf_k6n10f/gen_memories.py | 47 +++++++------------ tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 2 +- tests/arch/quicklogic/qlf_k6n10f/run-test.sh | 1 + 5 files changed, 21 insertions(+), 36 deletions(-) diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys index 635769cc0d2..ccce5882f65 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys @@ -1,8 +1,7 @@ read_verilog bram_tdp.v hierarchy -top BRAM_TDP synth_quicklogic -family qlf_k6n10f -read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v read_verilog -formal bram_tdp_tb.v -hierarchy -top TB -proc +read_verilog -overwrite +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +prep -top TB sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v index 5d4fbe06779..351c334d035 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v @@ -57,7 +57,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i]; wire rce_b = rce_b_testvector[i]; wire [ADDR_WIDTH-1:0] ra_b = ra_b_testvector[i]; -wire [DATA_WIDTH-1:0] rq_b = rq_b_expected[i]; +wire [DATA_WIDTH-1:0] rq_b; wire wce_b = wce_b_testvector[i]; wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i]; diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py index 631289800f0..1d596b3c731 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py +++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py @@ -4,11 +4,11 @@ blockram_template = """# ====================================== +log ** GENERATING TEST {top} WITH PARAMS{param_str} design -reset; read_verilog -defer ../../common/blockram.v chparam{param_str} {top} hierarchy -top {top} -synth_quicklogic -family qlf_k6n10f -top {top}; cd {top} -log ** TESTING {top} WITH PARAMS{param_str}\ +synth_quicklogic -family qlf_k6n10f -top {top} """ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [ # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work @@ -103,8 +103,10 @@ ] sim_template = """\ -cd -read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +design -stash synthesized +design -copy-from synthesized -as {top}_synth {top} +design -delete synthesized +read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v read_verilog < Date: Fri, 1 Dec 2023 14:28:50 +0100 Subject: [PATCH 35/39] remove example test --- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v | 77 --------------- tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys | 7 -- .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v | 99 ------------------- 3 files changed, 183 deletions(-) delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys delete mode 100644 tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v deleted file mode 100644 index 536cce992f0..00000000000 --- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.v +++ /dev/null @@ -1,77 +0,0 @@ -// Copyright 2020-2022 F4PGA Authors -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 - -module BRAM_TDP #(parameter AWIDTH = 10, -parameter DWIDTH = 36)( - clk_a, - rce_a, - ra_a, - rq_a, - wce_a, - wa_a, - wd_a, - - clk_b, - rce_b, - ra_b, - rq_b, - wce_b, - wa_b, - wd_b -); - - input clk_a; - input rce_a; - input [AWIDTH-1:0] ra_a; - output reg [DWIDTH-1:0] rq_a; - input wce_a; - input [AWIDTH-1:0] wa_a; - input [DWIDTH-1:0] wd_a; - - input clk_b; - input rce_b; - input [AWIDTH-1:0] ra_b; - output reg [DWIDTH-1:0] rq_b; - input wce_b; - input [AWIDTH-1:0] wa_b; - input [DWIDTH-1:0] wd_b; - - (* no_rw_check = 1 *) - reg [DWIDTH-1:0] memory[0:(1< 0) begin - if($past(rce_a)) - assert(rq_a == rq_a_expected[i]); - if($past(rce_b)) - assert(rq_b == rq_b_expected[i]); - end - i <= i + 1; - end -end -endmodule \ No newline at end of file From 215a777eb32ea2c1d688b800af50e13c2851417b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 4 Dec 2023 09:24:19 +1300 Subject: [PATCH 36/39] qlf_tests: minor adjustment Renamed python script so that it sits next to the testbench file when alphabetically sorted. Reverted `MAX_WIDTH` to full precision for truncation testing. --- .../quicklogic/qlf_k6n10f/{gen_memories.py => mem_gen.py} | 0 tests/arch/quicklogic/qlf_k6n10f/mem_tb.v | 5 ++++- tests/arch/quicklogic/qlf_k6n10f/run-test.sh | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) rename tests/arch/quicklogic/qlf_k6n10f/{gen_memories.py => mem_gen.py} (100%) diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py similarity index 100% rename from tests/arch/quicklogic/qlf_k6n10f/gen_memories.py rename to tests/arch/quicklogic/qlf_k6n10f/mem_gen.py diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v index 89e41f8bc32..a0d15bd6222 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v @@ -8,7 +8,10 @@ parameter DATA_WIDTH_A = DATA_WIDTH; parameter DATA_WIDTH_B = DATA_WIDTH; parameter VECTORLEN = 16; parameter SHIFT_VAL = 0; -localparam MAX_WIDTH = DATA_WIDTH; + +// intentionally keep expected values at full width precision to allow testing +// of truncation +localparam MAX_WIDTH = 36; reg rce_a_testvector [VECTORLEN-1:0]; reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0]; diff --git a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh index be16b782916..2fe33619418 100755 --- a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh +++ b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh @@ -1,5 +1,5 @@ #!/usr/bin/env bash set -eu -python3 gen_memories.py +python3 mem_gen.py source ../../../gen-tests-makefile.sh run_tests --yosys-scripts --bash From 97354782c088f2cad3b4bae09c31b9ec32aac896 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 4 Dec 2023 11:16:50 +1300 Subject: [PATCH 37/39] Adding double_sync_ram_tdp to blockram.v --- tests/arch/common/blockram.v | 65 ++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/tests/arch/common/blockram.v b/tests/arch/common/blockram.v index 09bc7786346..4a9d45a6b4a 100644 --- a/tests/arch/common/blockram.v +++ b/tests/arch/common/blockram.v @@ -181,3 +181,68 @@ module sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) endmodule // sync_ram_tdp +module double_sync_ram_tdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10) +( + input wire clk_a_0, + input wire write_enable_a_0, read_enable_a_0, + input wire [DATA_WIDTH-1:0] write_data_a_0, + input wire [ADDRESS_WIDTH-1:0] addr_a_0, + output wire [DATA_WIDTH-1:0] read_data_a_0, + + input wire clk_a_1, + input wire write_enable_a_1, read_enable_a_1, + input wire [DATA_WIDTH-1:0] write_data_a_1, + input wire [ADDRESS_WIDTH-1:0] addr_a_1, + output wire [DATA_WIDTH-1:0] read_data_a_1, + + input wire clk_b_0, + input wire write_enable_b_0, read_enable_b_0, + input wire [DATA_WIDTH-1:0] write_data_b_0, + input wire [ADDRESS_WIDTH-1:0] addr_b_0, + output wire [DATA_WIDTH-1:0] read_data_b_0, + + input wire clk_b_1, + input wire write_enable_b_1, read_enable_b_1, + input wire [DATA_WIDTH-1:0] write_data_b_1, + input wire [ADDRESS_WIDTH-1:0] addr_b_1, + output wire [DATA_WIDTH-1:0] read_data_b_1 +); + + sync_ram_tdp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) ram_0 ( + .clk_a(clk_a_0), + .clk_b(clk_b_0), + .write_enable_a(write_enable_a_0), + .write_enable_b(write_enable_b_0), + .read_enable_a(read_enable_a_0), + .read_enable_b(read_enable_b_0), + .write_data_a(write_data_a_0), + .write_data_b(write_data_b_0), + .addr_a(addr_a_0), + .addr_b(addr_b_0), + .read_data_a(read_data_a_0), + .read_data_b(read_data_b_0) + ); + + sync_ram_tdp #( + .DATA_WIDTH(DATA_WIDTH), + .ADDRESS_WIDTH(ADDRESS_WIDTH) + ) ram_1 ( + .clk_a(clk_a_1), + .clk_b(clk_b_1), + .write_enable_a(write_enable_a_1), + .write_enable_b(write_enable_b_1), + .read_enable_a(read_enable_a_1), + .read_enable_b(read_enable_b_1), + .write_data_a(write_data_a_1), + .write_data_b(write_data_b_1), + .addr_a(addr_a_1), + .addr_b(addr_b_1), + .read_data_a(read_data_a_1), + .read_data_b(read_data_b_1) + ); + +endmodule // double_sync_ram_tdp + From e5c32f399a5efc49028f791315f7d87a7bff2dc8 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 4 Dec 2023 11:17:18 +1300 Subject: [PATCH 38/39] synth_quicklogic: Testing double_sync_ram_tdp --- tests/arch/quicklogic/qlf_k6n10f/mem_gen.py | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py b/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py index 1d596b3c731..226d6a1a0d7 100644 --- a/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py +++ b/tests/arch/quicklogic/qlf_k6n10f/mem_gen.py @@ -77,9 +77,20 @@ ([("ADDRESS_WIDTH_A", 9), ("DATA_WIDTH_A", 36), ("ADDRESS_WIDTH_B", 11), ("DATA_WIDTH_B", 9)], "double_sync_ram_sdp", ["-assert-count 2 t:TDP36K"]), + # also for tdp + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 16)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 8)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 12), ("DATA_WIDTH", 4)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 13), ("DATA_WIDTH", 2)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 14), ("DATA_WIDTH", 1)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K"]), + # still only if data width is <= 18 + ([("ADDRESS_WIDTH", 9), ("DATA_WIDTH", 36)], "double_sync_ram_tdp", ["-assert-count 2 t:TDP36K"]), + # sharing a TDP36K sets is_split=1 ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("ADDRESS_WIDTH_B", 10), ("DATA_WIDTH_B", 18)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", ["-assert-count 1 t:TDP36K a:is_split=1 %i"]), # an unshared TDP36K sets is_split=0 ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 36)], "sync_ram_*dp", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), ([("ADDRESS_WIDTH", 11), ("DATA_WIDTH", 18)], "sync_ram_sdp_w*r", ["-assert-count 1 t:TDP36K a:is_split=0 %i"]), @@ -88,6 +99,9 @@ ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 18), ("DATA_WIDTH_B", 18), ("ADDRESS_WIDTH_B", 10)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", "-assert-count 1 t:TDP36K"]), + ([("ADDRESS_WIDTH", 10), ("DATA_WIDTH", 18)], "double_sync_ram_tdp", + ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=18 %i", + "-assert-count 1 t:TDP36K"]), ([("ADDRESS_WIDTH_A", 10), ("DATA_WIDTH_A", 16), ("DATA_WIDTH_B", 8), ("ADDRESS_WIDTH_B", 11)], "double_sync_ram_sdp", ["-assert-count 1 t:TDP36K a:port_a1_width=18 %i a:port_a2_width=9 %i " + "t:TDP36K a:port_a2_width=18 %i a:port_a1_width=9 %i %u", From 22cc4aff5116fe51b63c0e78a381f53091044444 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Mon, 4 Dec 2023 15:47:50 +0100 Subject: [PATCH 39/39] quicklogic: Test TDP36K inference with initial data --- .../quicklogic/qlf_k6n10f/libmap_brams_map.v | 1 + tests/arch/quicklogic/qlf_k6n10f/meminit.v | 50 +++++++++++++++++++ tests/arch/quicklogic/qlf_k6n10f/meminit.ys | 14 ++++++ 3 files changed, 65 insertions(+) create mode 100644 tests/arch/quicklogic/qlf_k6n10f/meminit.v create mode 100644 tests/arch/quicklogic/qlf_k6n10f/meminit.ys diff --git a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v index f4f4420c1a2..3a5641bb880 100644 --- a/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v +++ b/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v @@ -178,6 +178,7 @@ defparam _TECHMAP_REPLACE_.MODE_BITS = { 1'b0, (* is_inferred = 1 *) (* is_split = 0 *) +(* was_split_candidate = OPTION_SPLIT *) (* port_a_width = PORT_A_WIDTH *) (* port_b_width = PORT_B_WIDTH *) TDP36K #( diff --git a/tests/arch/quicklogic/qlf_k6n10f/meminit.v b/tests/arch/quicklogic/qlf_k6n10f/meminit.v new file mode 100644 index 00000000000..46a7dcac710 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/meminit.v @@ -0,0 +1,50 @@ +module top(clk); +parameter DEPTH_LOG2 = 10; +parameter WIDTH = 36; +parameter PRIME = 237481091; +localparam DEPTH = 2**DEPTH_LOG2; + +input wire clk; + +(* syn_ramstyle = "block_ram" *) +reg [WIDTH-1:0] mem [DEPTH-1:0]; + +integer i; +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + // Make up data by multiplying a large prime with the address, + // then cropping and retaining the lower bits + mem[i] = PRIME * i; + end +end + +reg [DEPTH_LOG2-1:0] counter = 0; +reg done = 1'b0; + +reg did_read = 1'b0; +reg [DEPTH_LOG2-1:0] read_addr; +reg [WIDTH-1:0] read_val; + +always @(posedge clk) begin + if (!done) begin + did_read <= 1'b1; + read_addr <= counter; + read_val <= mem[counter]; + end else begin + did_read <= 1'b0; + end + + if (!done) + counter = counter + 1; + if (counter == 0) + done = 1; +end + +wire [WIDTH-1:0] expect_val = PRIME * read_addr; +always @(posedge clk) begin + if (did_read) begin + $display("addr %x expected %x actual %x", read_addr, expect_val, read_val); + assert(read_val == expect_val); + end +end +endmodule diff --git a/tests/arch/quicklogic/qlf_k6n10f/meminit.ys b/tests/arch/quicklogic/qlf_k6n10f/meminit.ys new file mode 100644 index 00000000000..2949e1590d9 --- /dev/null +++ b/tests/arch/quicklogic/qlf_k6n10f/meminit.ys @@ -0,0 +1,14 @@ +read_verilog -sv meminit.v +chparam -set DEPTH_LOG2 3 -set WIDTH 36 +prep +opt_dff +prep -rdff +synth_quicklogic -family qlf_k6n10f -run map_bram:map_bram +select -assert-none t:$mem_v2 t:$mem +select -assert-count 1 t:TDP36K +select -assert-count 1 t:TDP36K a:is_split=0 %i +select -assert-count 1 t:TDP36K a:was_split_candidate=0 %i +read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v +prep +hierarchy -top top +sim -assert -q -n 12 -clock clk