diff --git a/doc/components/adder.md b/doc/components/adder.md index 7df7867b..fb53164c 100644 --- a/doc/components/adder.md +++ b/doc/components/adder.md @@ -107,12 +107,12 @@ Here is an example of instantiating a `SignMagnitudeAdder`: ## Compound Adder A compound carry adder is a digital circuit used for binary addition. It produces sum and sum+1 outputs. -A trivial compound adder component [`TrivialCompoundAdder`] doesnt use any RTL code optimization. -Carry-select adder-based compound adder [`CarrySelectCompoundAdder`] uses carry-select adder as a basis. Like a carry-select adder it consists of a multiple blocks of two ripple-carry adders . But the first block has two ripple-carry adders and two separate carry-propagate chains are used to select sum and sum+1 output bits. sum selecting chain starts from carry input 'zero' driven block and sum+1 selecting chain starts from carry input 'one' driven block. +A trivial compound adder component `TrivialCompoundAdder` doesnt use any RTL code optimization. +Carry-select adder-based compound adder `CarrySelectCompoundAdder` uses carry-select adder as a basis. Like a carry-select adder it consists of a multiple blocks of two ripple-carry adders . But the first block has two ripple-carry adders and two separate carry-propagate chains are used to select sum and sum+1 output bits. sum selecting chain starts from carry input 'zero' driven block and sum+1 selecting chain starts from carry input 'one' driven block. The delay of the adder is defined by combination ripple-carry adder and accumulated carry-select chain delay. -The [`CarrySelectCompoundAdder`] module in ROHD-HCL accept input `Logic`s a and b as the input pin and the name of the module `name`. Note that the width of the inputs must be the same or a `RohdHclException` will be thrown. -Compound adder generator provides two alogithms for splitting adder into ripple-carry blocks. [CarrySelectCompoundAdder.splitSelectAdderAlgorithm4Bit] algoritm splits adder into blocks of 4-bit ripple-carry adders with the first one width adjusted down. [CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock] algorithm generates only one block of full bitwidth of the adder. Input List\ Function(int adderFullWidth) [widthGen] should be used to specify custom adder splitting algorithm that return a list of sub-adders width. The default one is [CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock]. +The `CarrySelectCompoundAdder` module in ROHD-HCL accept input `Logic`s a and b as the input pin and the name of the module `name`. Note that the width of the inputs must be the same or a `RohdHclException` will be thrown. +Compound adder generator provides two alogithms for splitting adder into ripple-carry blocks. "CarrySelectCompoundAdder.splitSelectAdderAlgorithm4Bit" algoritm splits adder into blocks of 4-bit ripple-carry adders with the first one width adjusted down. "CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock" algorithm generates only one block of full bitwidth of the adder. Input List\ Function(int adderFullWidth) 'widthGen' should be used to specify custom adder splitting algorithm that return a list of sub-adders width. The default one is "CarrySelectCompoundAdder.splitSelectAdderAlgorithmSingleBlock". An example is shown below to add two inputs of signals that have 8-bits of width. diff --git a/lib/src/component_config/components/component_registry.dart b/lib/src/component_config/components/component_registry.dart index 63842009..0f624073 100644 --- a/lib/src/component_config/components/component_registry.dart +++ b/lib/src/component_config/components/component_registry.dart @@ -28,4 +28,5 @@ List get componentRegistry => [ ParallelPrefixAdderConfigurator(), CompressionTreeMultiplierConfigurator(), ExtremaConfigurator(), + CompoundAdderConfigurator(), ];