From d70259be023fabf3a44a6e1d378604de896d43ba Mon Sep 17 00:00:00 2001 From: bunnie Date: Sun, 18 Dec 2022 16:03:10 +0800 Subject: [PATCH] fix numerical overflow in bit shift operation In `xsim`, the limited precision of the shift-right argument causes overflow when the shift amount is multiplied by data width, leading to a result of always 0. This creates an explicitly sized shift right argument to fix this small compatibility issue. --- rtl/axi_crossbar_rd.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/rtl/axi_crossbar_rd.v b/rtl/axi_crossbar_rd.v index 2b1410a..bda96ea 100644 --- a/rtl/axi_crossbar_rd.v +++ b/rtl/axi_crossbar_rd.v @@ -327,6 +327,8 @@ generate wire [M_COUNT_P1-1:0] r_grant; wire r_grant_valid; wire [CL_M_COUNT_P1-1:0] r_grant_encoded; + wire [CL_M_COUNT_P1-1 + DATA_WIDTH:0] r_grant_encoded_wide = {{DATA_WIDTH{1'b0}}, r_grant_encoded}; + wire [CL_M_COUNT_P1-1 + DATA_WIDTH:0] r_grant_encoded_wide_shift = r_grant_encoded_wide * DATA_WIDTH; arbiter #( .PORTS(M_COUNT_P1), @@ -347,7 +349,7 @@ generate // read response mux wire [S_ID_WIDTH-1:0] m_axi_rid_mux = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH; - wire [DATA_WIDTH-1:0] m_axi_rdata_mux = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH; + wire [DATA_WIDTH-1:0] m_axi_rdata_mux = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded_wide_shift; wire [1:0] m_axi_rresp_mux = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2; wire m_axi_rlast_mux = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded; wire [RUSER_WIDTH-1:0] m_axi_ruser_mux = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH;