Single Stage RISC-V 32-bit Processor made in RISC-V Lab (UE21EC352A - RISC-V Architecture)
| Module | Completed | Verified | EDA Playground Link |
|---|---|---|---|
| Inst. Fetch | Y | Y | Link |
| Inst. Decode | Y | Y | Link |
| Inst. Execute | Y | Y | Link |
| Mem. Access | Y | N | Link |
| Individual Modules | |||
| Program Counter | Y | Y | Link |
| Adder | Y | Y | Link |
| InstMem | Y | Y | Link |
| 2:1 MUX | Y | Y | Link |
| Decoder | Y | Y | Link |
| Register File | Y | Y | Link |
| Sign Extender | Y | Y | Link |
| ALU | Y | Y | Link |
| Branch Control | Y | Y | Link |
| 3:1 MUX | Y | Y | Link |
| Data Memory | Y | Y | Link |
| Control Unit | Y | Y | Link |
| Datapath | Y | N | Link |
| Memory Controller | Y | N | Link |