update readmes

* projects/pulsar_adc * projects/ad_gmsl2eth_sl * projects/ad_quadmxfe1_ebz * projects/ad411x_ad717x * Added template for readme: projects/common/README.md * projects/ad3552r_evb/Readme.md * projects/ad469x_fmc/Readme.md * projects/ad485x_fmcz/Readme.md * projects/ad719x_asdz/README.md * projects/ad738x_fmc/Readme.md * projects/ad777x_ardz/Readme.md Signed-off-by: Iulia Moldovan <Iulia.Moldovan@analog.com>
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diff --git a/projects/ad3552r_evb/Readme.md b/projects/ad3552r_evb/Readme.md
@@ -1,8 +1,18 @@
 # AD3552R-EVB HDL Project
 
-Here are some pointers to help you:
-  * [Board Product Page](https://www.analog.com/eval-ad3552r)
-  * Parts : [ AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC ](https://www.analog.com/en/products/ad3552r.html)
-  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed
-  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed
-  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-dac/axi-ad3552r
+  * Evaluation board product page: [EVAL-AD3552R-EVB](https://www.analog.com/eval-ad3552r)
+  * System documentation: https://wiki.analog.com/resources/eval/user-guides/dac/ad3552r_eval_zed
+  * HDL project documentation: [source code](../../docs/projects/ad3552r_evb/index.rst)
+    or [online](http://analogdevicesinc.github.io/hdl/projects/ad3552r_evb/index.html)
+
+## Supported parts
+
+  * [AD3552R](https://www.analog.com/ad3552r): Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC
+
+## Building the project
+
+This project is supported only on FPGA Avnet ZedBoard.
+
+```
+hdl/projects/ad3552r_evb/zed> make
+```
diff --git a/projects/ad411x_ad717x/README.md b/projects/ad411x_ad717x/README.md
@@ -0,0 +1,39 @@
+# AD411x-AD717x HDL project
+
+  * Evaluation board product pages:
+    * [EVAL-AD4111-ARDZ](https://www.analog.com/eval-ad4111-ardz)
+    * [EVAL-AD4112-ARDZ](https://www.analog.com/eval-ad4112-ardz)
+    * [EVAL-AD4114-SDZ](https://www.analog.com/eval-ad4114-sdz)
+    * [EVAL-AD4115-SDZ](https://www.analog.com/eval-ad4115-sdz)
+    * [EVAL-AD4116-ASDZ](https://www.analog.com/eval-ad4116-asdz)
+    * [EVAL-AD7173-8ARDZ](https://www.analog.com/eval-ad7173-8ardz)
+    * [EVAL-AD7175-8ARDZ](https://www.analog.com/eval-ad7175-8ardz)
+  * System documentation: https://wiki.analog.com/resources/eval/10-lead-pulsar-adc-evaluation-board
+  * HDL project documentation: [source code](../../docs/projects/ad411x_ad717x/index.rst)
+    or [online](https://analogdevicesinc.github.io/hdl/projects/ad411x_ad717x/index.html)
+
+## Supported parts
+
+| Part name                                   | Resolution | Description                                                                             |
+|---------------------------------------------|:----------:|-----------------------------------------------------------------------------------------|
+| [AD4111](https://www.analog.com/ad4111)     | 24-bit     | Single Supply, Sigma-Delta ADC with ±10 V and 0 mA to 20 mA Inputs, Open Wire Detection |
+| [AD4112](https://www.analog.com/ad4112)     | 24-bit     | Single Supply, Sigma-Delta ADC with ±10 V and 0 mA to 20 mA Inputs |
+| [AD4113](https://www.analog.com/ad4113)     | ?          |  ? |
+| [AD4114](https://www.analog.com/ad4114)     |            | Single Supply, Multichannel, 31.25 kSPS, Sigma-Delta ADC with ±10 V Inputs |
+| [AD4115](https://www.analog.com/ad4115)     | 24-bit     | Single-Supply, Multichannel, 125 kSPS, Sigma-Delta ADC with ±10 V Inputs |
+| [AD4116](https://www.analog.com/ad4116)     | 24-bit     | Single Supply, Sigma-Delta ADC with ±10 V, 10 MΩ Inputs and Buffered Low Level Inputs |
+| [AD7172-2](https://www.analog.com/ad7172-2) | 24-bit     | Low Power, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
+| [AD7172-4](https://www.analog.com/ad7172-4) | 24-bit     | Low Power,  with 4- or 8-channel, 31.25 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
+| [AD7173-8](https://www.analog.com/ad7173-8) | 24-bit     | Low Power, 8-/16-Channel, 31.25 kSPS, Highly Integrated Sigma-Delta ADC
+| [AD7175-2](https://www.analog.com/ad7175-2) | 24-bit     | 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers |
+| [AD7175-8](https://www.analog.com/ad7175-8) | 24-bit     | 8-/16-Channel, 250 kSPS, Sigma-Delta ADC with True Rail-to-Rail Buffers |
+| [AD7176-2](https://www.analog.com/ad7176-2) | 24-bit     | 250 kSPS Sigma Delta ADC with 20 µs Settling |
+| [AD7177-2](https://www.analog.com/ad7177-2) | 32-bit     | 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers |
+
+## Building the project
+
+This project is supported only on FPGA Intel DE10-Nano.
+
+```
+hdl/projects/ad411x_ad717x/de10nano> make
+```
diff --git a/projects/ad469x_fmc/Readme.md b/projects/ad469x_fmc/Readme.md
@@ -1,20 +1,29 @@
 # AD469X-FMC HDL Project
 
-Here are some pointers to help you:
-  * [Board Product Page](https://www.analog.com/eval-ad4696)
-  * Parts : [AD4696, 16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4696)
-  * Parts : [AD4695, 16-Bit, 16-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4695)
-  * Parts : [AD4697, 16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4697)
-  * Parts : [AD4698, 16-Bit, 8-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC](https://www.analog.com/ad4698)
-  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
-  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad469x
-  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
-# Building, Generating Bit Files
-
-How to use over-writable parameter from the environment:
+  * Evaluation board product page: [EVAL-AD4696](https://www.analog.com/eval-ad4696)
+  * System documentation: https://wiki.analog.com/resources/eval/user-guides/ad469x
+  * HDL project documentation: [source code](../../docs/projects/ad469x_fmc/index.rst)
+    or [online](https://analogdevicesinc.github.io/hdl/projects/ad469x_fmc/index.html)
+
+## Supported parts
+
+| Part name                               | Description                                                 |
+|-----------------------------------------|-------------------------------------------------------------|
+| [AD4696](https://www.analog.com/ad4696) | 16-Bit, 16-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC  |
+| [AD4695](https://www.analog.com/ad4695) | 16-Bit, 16-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC|
+| [AD4697](https://www.analog.com/ad4697) | 16-Bit, 8-Channel, 500 kSPS, Easy Drive Multiplexed SAR ADC |
+| [AD4698](https://www.analog.com/ad4698) | 16-Bit, 8-Channel, 1 MSPS, Easy Drive Multiplexed SAR ADC   |
+
+## Building the project
+
+This project is supported only on FPGA Avnet ZedBoard.
+
+How to use overwritable parameter from the environment:
+
+**SPI_4WIRE** - Defines if CNV signal is linked to PWM or to SPI_CS
+* 0 - CNV signal is linked to PWM (default option)
+* 1 - CNV signal is linked to SPI_CS
+
 ```
 hdl/projects/ad469x_fmc/zed> make SPI_4WIRE=0
 ```
-SPI_4WIRE - Defines if CNV signal is linked to PWM or to SPI_CS
-* 0 - CNV signal is linked to PWM
-* 1 - CNV signal is linked to SPI_CS
diff --git a/projects/ad485x_fmcz/Readme.md b/projects/ad485x_fmcz/Readme.md
@@ -1,8 +1,50 @@
 # AD485x HDL Project
 
-Here are some pointers to help you:
-  * [Board Product Page](https://www.analog.com/eval-ad4858)
-  * Parts : [AD485x(1-8)](https://www.analog.com/ad4858)
-  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz
-  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
-  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl
+  * Evaluation board product page: [EVAL-AD4858](https://www.analog.com/eval-ad4858)
+  * System documentation: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
+  * HDL project documentation: [source code](../../docs/projects/ad485x_fmcz/index.rst)
+    or [online](http://analogdevicesinc.github.io/hdl/projects/ad485x_fmcz/index.html)
+
+## Supported parts
+
+| Part name                               | No. of lanes | Resolution | Description                                           |
+|-----------------------------------------|:------------:|:----------:|-------------------------------------------------------|
+| [AD4858](https://www.analog.com/ad4858) | 8            | 20-bit     | Buffered, 8-Channel Simultaneous Sampling, 1 MSPS DAS |
+| [AD4857](https://www.analog.com/ad4857) | 8            | 16-bit     | Buffered, 8-Channel Simultaneous Sampling, 1 MSPS DAS |
+| AD4856                                  | 8            | 20-bit     | Buffered, 8-Channel Simultaneous Sampling, 250 kSPS DAS |
+| AD4855                                  | 8            | 16-bit     | Buffered, 8-Channel Simultaneous Sampling, 250 kSPS DAS |
+| AD4854                                  | 4            | 20-bit     | Buffered, 4-Channel Simultaneous Sampling, 1 MSPS DAS |
+| AD4853                                  | 4            | 16-bit     | Buffered, 4-Channel Simultaneous Sampling, 1 MSPS DAS |
+| AD4852                                  | 4            | 20-bit     | Buffered, 4-Channel Simultaneous Sampling, 250 kSPS DAS |
+| AD4851                                  | 4            | 16-bit     | Buffered, 4-Channel Simultaneous Sampling, 250 kSPS DAS |
+
+## Building the project
+
+This project is supported only on FPGA Avnet ZedBoard.
+
+How to use overwritable parameters from the environment:
+
+**LVDS_CMOS_N**:
+  * 0 - CMOS (default option)
+  * 1 - LVDS
+
+**DEVICE**:
+  * AD4858 (default option)
+  * AD4857
+  * AD4856
+  * AD4855
+  * AD4854
+  * AD4853
+  * AD4852
+  * AD4851
+
+```
+// default option is AD4858 and CMOS
+hdl/projects/ad485x_fmcz/zed> make
+
+// selected device is AD4857 and CMOS
+hdl/projects/ad485x_fmcz/zed> make DEVICE=AD4857
+
+// selected device is AD4858 and LVDS
+hdl/projects/ad485x_fmcz/zed> make DEVICE=AD4858 LVDS_CMOS_N=1
+```
diff --git a/projects/ad719x_asdz/README.md b/projects/ad719x_asdz/README.md
@@ -1,14 +1,25 @@
-# EVAL-AD719X-ASDZ HDL Project
-
-This project supports EVAL-AD7190, EVAL-AD7193 and EVAL-AD7195.
-
-Here are some pointers to help you:
-  * [EVAL-AD7190 Board Product Page](https://www.analog.com/eval-ad7190)
-  * [EVAL-AD7193 Board Product Page](https://www.analog.com/eval-ad7193)
-  * [EVAL-AD7195 Board Product Page](https://www.analog.com/eval-ad7195)
-  * Parts: AD7190 [Sigma-Delta ADC, SPI interface, 24-bit resolution, Data rate between 4.7Hz - 4.8kHz](https://www.analog.com/ad7190)
-  * Parts: AD7193 [4-channel Sigma-Delta ADC, SPI interface, 24-bit resolution, Data rate between 4.7Hz - 4.8kHz](https://www.analog.com/ad7193)
-  * Parts: AD7195 [Sigma-Delta ADC, SPI interface, 24-bit resolution, Data rate between 4.7Hz - 4.8kHz](https://www.analog.com/ad7195)
-  * Project Doc: https://wiki.analog.com/resources/eval/adc/ad719x_asdz
-  * HDL Doc: https://wiki.analog.com/resources/eval/adc/ad719x_asdz 
-  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all
+# AD719x-ASDZ HDL Project
+
+  * Evaluation board product pages:
+    * [EVAL-AD7190](https://www.analog.com/eval-ad7190)
+    * [EVAL-AD7193](https://www.analog.com/eval-ad7193)
+    * [EVAL-AD7195](https://www.analog.com/eval-ad7195)
+  * System documentation: https://wiki.analog.com/resources/eval/adc/ad719x_asdz 
+  * HDL project documentation: [source code](../../docs/projects/ad719x_asdz/index.rst)
+    or [online](http://analogdevicesinc.github.io/hdl/projects/ad719x_asdz/index.html)
+
+## Supported parts
+
+| Part name                               | Resolution | Description                                      |
+|-----------------------------------------|:----------:|--------------------------------------------------|
+| [AD7190](https://www.analog.com/ad7190) | 24-bit     | 4.8 kHz Ultralow Noise, Sigma-Delta ADC with PGA |
+| [AD7193](https://www.analog.com/ad7193) | 24-bit     | 4-Channel, 4.8 kHz, Ultralow Noise, Sigma-Delta ADC with PGA |
+| [AD7195](https://www.analog.com/ad7195) | 24-bit     | 4.8 kHz, Ultralow Noise, Sigma-Delta ADC with PGA and AC Excitation |
+
+## Building the project
+
+This project is supported only on FPGA Xilinx Cora Z7S.
+
+```
+hdl/projects/ad719x_asdz/cora> make
+```
diff --git a/projects/ad738x_fmc/Readme.md b/projects/ad738x_fmc/Readme.md
@@ -1,37 +1,54 @@
-# AD738X-FMC HDL Project
-
-Here are some pointers to help you:
-  * [Board Product Page](https://www.analog.com/eval-ad738xfmcz)
-  * Parts : [AD7380, 4MSPS Dual Simultaneous Sampling, 16-BIT SAR ADC, Differential Input](https://www.analog.com/ad7380)
-  * Parts : [AD7380-4, 4MSPS Quad, External Reference Simultaneous Sampling, 16-Bit, SAR ADC, Differential Input](https://www.analog.com/ad7380-4)
-  * Parts : [AD7381, 4MSPS Dual Simultaneous Sampling, 14-BIT SAR ADC, Differential Input](https://www.analog.com/ad7381)
-  * Parts : [AD7381-4, 4MSPS Quad, 14-Bit, Simultaneous Sampling, SAR ADC, Differential Input](https://www.analog.com/ad7381-4)
-  * Parts : [AD7383-4, 4MSPS Quad, Simultaneous Sampling, 16-Bit, SAR ADC, Pseudo Differential Input](https://www.analog.com/ad7383-4)
-  * Parts : [AD7384-4, 4MSPS Quad, Simultaneous Sampling, 14-Bit, SAR ADC, Pseudo Differential Input](https://www.analog.com/ad7384-4)
-  * Parts : [AD7386, 4-Channel, 4 MSPS, 16-Bit Dual Simultaneous Sampling SAR ADC](https://www.analog.com/ad7386)
-  * Parts : [AD7387, 4-Channel, 4 MSPS, 14-Bit, Dual, Simultaneous Sampling SAR ADC](https://www.analog.com/ad7387)
-  * Parts : [AD7388, 4-Channel, 4 MSPS, 12-Bit, Dual, Simultaneous Sampling SAR ADCs](https://www.analog.com/ad7388)
-  * Parts : [AD7389-4, 4MSPS Quad, Internal Reference Simultaneous Sampling, 16-Bit SAR ADC, Differential Input](https://www.analog.com/ad7389-4)
-  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad738x
-  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad738x
-  * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad738x
-# Building, Generating Bit Files
-
-How to use over-writable parameters from the environment:
+# AD738x-FMC HDL Project
+
+  * Evaluation board product page: [EVAL-AD738x-FMCZ](https://www.analog.com/eval-ad738xfmcz)
+  * System documentation: https://wiki.analog.com/resources/eval/user-guides/ad738x
+  * HDL project documentation: [source code](../../docs/projects/ad738x_fmc/index.rst)
+    or [online](http://analogdevicesinc.github.io/hdl/projects/ad738x_fmc/index.html)
+
+## Supported parts
+
+| Part name                                   | Resolution | Description                                                      |
+|---------------------------------------------|:----------:|------------------------------------------------------------------|
+| [AD7380](https://www.analog.com/ad7380)     | 16-bit     | 4MSPS Dual Simultaneous Sampling, SAR ADC, Differential Input |
+| [AD7380-4](https://www.analog.com/ad7380-4) | 16-bit     | 4MSPS Quad, External Reference Simultaneous Sampling, SAR ADC, Differential Input |
+| [AD7381](https://www.analog.com/ad7381)     | 14-bit     | 4MSPS Dual Simultaneous Sampling, SAR ADC, Differential Input |
+| [AD7381-4](https://www.analog.com/ad7381-4) | 14-bit     | 4MSPS Quad, Simultaneous Sampling, SAR ADC, Differential Input |
+| [AD7383-4](https://www.analog.com/ad7383-4) | 16-bit     | 4MSPS Quad, Simultaneous Sampling, SAR ADC, Pseudo Differential Input |
+| [AD7384-4](https://www.analog.com/ad7384-4) | 14-bit     | 4MSPS Quad, Simultaneous Sampling, SAR ADC, Pseudo Differential Input |
+| [AD7386](https://www.analog.com/ad7386)     | 16-bit     | 4-Channel, 4 MSPS, Dual Simultaneous Sampling SAR ADC |
+| [AD7387](https://www.analog.com/ad7387)     | 14-bit     | 4-Channel, 4 MSPS, Dual, Simultaneous Sampling SAR ADC |
+| [AD7388](https://www.analog.com/ad7388)     | 12-bit     | 4-Channel, 4 MSPS, Dual, Simultaneous Sampling SAR ADCs |
+| [AD7389-4](https://www.analog.com/ad7389-4) | 16-bit     | 4MSPS Quad, Internal Reference Simultaneous Sampling, SAR ADC, Differential Input |
+
+## Building the project
+
+This project is supported only on FPGA Avnet ZedBoard.
+
+How to use overwritable parameters from the environment:
+
+**ALERT_SPI_N** - SDOB-SDOD/ALERT pin can operate as a serial data output pin or alert indication output depending on its value:
+  * 0 - SDOB-SDOD (default option)
+  * 1 - ALERT
+
+**NUM_OF_SDI** - defines the number of SDI lines used:
+  * 1 (default option)
+  * 2
+  * 4
+
+> [!NOTE]
+> * For the ALERT functionality, the following parameters will be used in make command: ALERT_SPI_N
+> * For the serial data output functionality, the following parameters will be used in make command: ALERT_SPI_N, NUM_OF_SDI
+
 ```
+// default configuration
+hdl/projects/ad738x_fmc/zed> make
+
+// pin is in SDOB-SDOD and 4 lines of SDI are used
 hdl/projects/ad738x_fmc/zed> make ALERT_SPI_N=0 NUM_OF_SDI=4
 ```
 
-SDOB-SDOD/ALERT pin can operate as a serial data output pin or alert indication output depending on its value:
-* 0 - SDOB-SDOD
-* 1 - ALERT
-
-NUM_OF_SDI - Defines the number of SDI lines used: 1, 2, 4
-
-For the ALERT functionality, the following parameters will be used in make command: ALERT_SPI_N
-For the serial data output functionality, the following parameters will be used in make command: ALERT_SPI_N, NUM_OF_SDI
+### Example configurations
 
-**Example:**
 ```
 make ALERT_SPI_N=0 NUM_OF_SDI=1
 make ALERT_SPI_N=0 NUM_OF_SDI=2

diff --git a/projects/ad777x_ardz/Readme.md b/projects/ad777x_ardz/Readme.md
@@ -1,12 +1,28 @@
 # AD777x-ARDZ HDL Project
 
-Here are some pointers to help you:
-  * [Board Product Page](https://www.analog.com/EVAL-AD7770-AD7779)
-  * Parts : [AD7771: 8-Channel, 24-Bit, Simultaneous Sampling ADC](https://www.analog.com/AD7771)
-            [AD7779: 8-Channel, 24-Bit, Simultaneous Sampling ADC](https://www.analog.com/ad7779)
-            [AD7770: 8-Channel, 24-Bit, Simultaneous Sampling ADC](https://www.analog.com/AD7770)
-  * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad777x-ardz
-  * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad777x-ardz
-             [AXI_AD777x](https://wiki.analog.com/resources/fpga/docs/ad777x)
-  * NO-OS Drivers: [AD777x - No-OS Driver](https://wiki.analog.com/resources/tools-software/uc-drivers/ad7779)
-
+  * Evaluation board product page: [EVAL-AD7770-AD7779](https://www.analog.com/EVAL-AD7770-AD7779)
+  * System documentation: https://wiki.analog.com/resources/eval/user-guides/ad777x-ardz
+  * HDL project documentation: [source code](../../docs/projects/ad777x_ardz/index.rst)
+    or [online](http://analogdevicesinc.github.io/hdl/projects/ad777x_ardz/index.html)
+
+## Supported parts
+
+| Part name                             | Resolution | Description                                  |
+|---------------------------------------|:----------:|----------------------------------------------|
+[AD7770](https://www.analog.com/AD7770) | 24-Bit     | 8-Channel, 32 kSPS Simultaneous Sampling ADC |
+[AD7771](https://www.analog.com/AD7771) | 24-Bit     | 8-Channel, 128 kSPS Simultaneous Sampling ADC |
+[AD7779](https://www.analog.com/ad7779) | 24-Bit     | 8-Channel, 16 kSPS Simultaneous Sampling ADC |
+
+## Building the project
+
+### DE10-Nano
+
+```
+hdl/projects/ad777x_ardz/de10nano> make
+```
+
+### Zed
+
+```
+hdl/projects/ad777x_ardz/zed> make
+```