common: hotfix add use_smartconnect

[gastmaier]

Sets default value to use_smartconnenct.
Previously I thought it would take from somewhere else for every tb, but that preconception is false since #54 is failing rebased to main.

[IstvanZsSzekely]

Checked various projects to see why are they built with the latest changes and the DMA_SG project not. I dug a bit in the recent modifications in the HDL infrastructure updates as well, and I found that if the FPGA is set to be a 7-series one, then the HDL and Testbench projects are automatically built with Axi-Interconnect. In the DMA_SG case, the project was created using a 7-series FPGA, so the script was automatically waiting for old scripting commands. I request a change on the DMA_SG PR to solve this issue.

[IstvanZsSzekely]

I'll put this PR in draft, up until we get an answer from Xilinx to see if the Smart Connect can be used to connect 16+ modules to it in low-area mode. Currently this is not working in the design, but according to the docs, it should.

[IstvanZsSzekely]

The suggested change for the DMA_SG_PR worked and the Smart Connect cannot be used with 16+ slave interfaces due to some environment limitations. A PR has been created to address the 16+ slave interface issue for the ADRV9009 and future projects.
This PR is hence closed.