From da8039bdddf1cff658bd5c3db9629615d69b6f29 Mon Sep 17 00:00:00 2001 From: aofarmakis <125706387+aofarmakis@users.noreply.github.com> Date: Sat, 7 Dec 2024 18:34:28 +0200 Subject: [PATCH] Additional Instruction Memories for NibbleBuddy These ROM modules contain the binary versions of the additional NibbleBuddy Assembly programs written and in the Assembly directory of the repository, as produced by the Python assembler in the same directory. --- Verilog/instruction_memory_byte_addition.v | 34 ++++++++++++++ .../instruction_memory_circular_shift_left.v | 29 ++++++++++++ .../instruction_memory_infinite_counting.v | 26 +++++++++++ .../instruction_memory_logical_shift_left.v | 29 ++++++++++++ Verilog/instruction_memory_one-hot_detector.v | 42 ++++++++++++++++++ ...struction_memory_unsigned_multiplication.v | 44 +++++++++++++++++++ Verilog/instruction_memory_xor_xnor.v | 29 ++++++++++++ 7 files changed, 233 insertions(+) create mode 100644 Verilog/instruction_memory_byte_addition.v create mode 100644 Verilog/instruction_memory_circular_shift_left.v create mode 100644 Verilog/instruction_memory_infinite_counting.v create mode 100644 Verilog/instruction_memory_logical_shift_left.v create mode 100644 Verilog/instruction_memory_one-hot_detector.v create mode 100644 Verilog/instruction_memory_unsigned_multiplication.v create mode 100644 Verilog/instruction_memory_xor_xnor.v diff --git a/Verilog/instruction_memory_byte_addition.v b/Verilog/instruction_memory_byte_addition.v new file mode 100644 index 0000000..8655396 --- /dev/null +++ b/Verilog/instruction_memory_byte_addition.v @@ -0,0 +1,34 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00110101; + 01: data = 8'b00000000; + 02: data = 8'b00110100; + 03: data = 8'b00000001; + 04: data = 8'b00110001; + 05: data = 8'b00000010; + 06: data = 8'b00111111; + 07: data = 8'b00000011; + 08: data = 8'b1000xxxx; + 09: data = 8'b00100000; + 10: data = 8'b01000001; + 11: data = 8'b00000100; + 12: data = 8'b00100010; + 13: data = 8'b01000011; + 14: data = 8'b00000101; + 15: data = 8'b00110000; + 16: data = 8'b01010000; + 17: data = 8'b00000110; + 18: data = 8'b00100100; + 19: data = 8'b00100101; + 20: data = 8'b00100110; + 21: data = 8'b0001xxxx; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file diff --git a/Verilog/instruction_memory_circular_shift_left.v b/Verilog/instruction_memory_circular_shift_left.v new file mode 100644 index 0000000..fe1cde1 --- /dev/null +++ b/Verilog/instruction_memory_circular_shift_left.v @@ -0,0 +1,29 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00111001; + 01: data = 8'b00000000; + 02: data = 8'b00110010; + 03: data = 8'b00000001; + 04: data = 8'b10100110; + 05: data = 8'b11101111; + 06: data = 8'b1000xxxx; + 07: data = 8'b00100000; + 08: data = 8'b01000000; + 09: data = 8'b01010000; + 10: data = 8'b00000000; + 11: data = 8'b00100001; + 12: data = 8'b01011111; + 13: data = 8'b00000001; + 14: data = 8'b10100110; + 15: data = 8'b00100000; + 16: data = 8'b0001xxxx; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file diff --git a/Verilog/instruction_memory_infinite_counting.v b/Verilog/instruction_memory_infinite_counting.v new file mode 100644 index 0000000..b2e1d5c --- /dev/null +++ b/Verilog/instruction_memory_infinite_counting.v @@ -0,0 +1,26 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00110000; + 01: data = 8'b00000000; + 02: data = 8'b00000001; + 03: data = 8'b00100001; + 04: data = 8'b01010001; + 05: data = 8'b01000000; + 06: data = 8'b00000001; + 07: data = 8'b1000xxxx; + 08: data = 8'b10100011; + 09: data = 8'b00100000; + 10: data = 8'b01010001; + 11: data = 8'b1000xxxx; + 12: data = 8'b00000000; + 13: data = 8'b11100011; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file diff --git a/Verilog/instruction_memory_logical_shift_left.v b/Verilog/instruction_memory_logical_shift_left.v new file mode 100644 index 0000000..864d766 --- /dev/null +++ b/Verilog/instruction_memory_logical_shift_left.v @@ -0,0 +1,29 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00111001; + 01: data = 8'b00000000; + 02: data = 8'b00110010; + 03: data = 8'b00000001; + 04: data = 8'b10100110; + 05: data = 8'b11101111; + 06: data = 8'b1000xxxx; + 07: data = 8'b00100000; + 08: data = 8'b01000000; + 09: data = 8'b1000xxxx; + 10: data = 8'b00000000; + 11: data = 8'b00100001; + 12: data = 8'b01011111; + 13: data = 8'b00000001; + 14: data = 8'b10100110; + 15: data = 8'b00100000; + 16: data = 8'b0001xxxx; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file diff --git a/Verilog/instruction_memory_one-hot_detector.v b/Verilog/instruction_memory_one-hot_detector.v new file mode 100644 index 0000000..b385c3b --- /dev/null +++ b/Verilog/instruction_memory_one-hot_detector.v @@ -0,0 +1,42 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00111100; + 01: data = 8'b00000000; + 02: data = 8'b00111000; + 03: data = 8'b00000001; + 04: data = 8'b00110000; + 05: data = 8'b00000010; + 06: data = 8'b00100001; + 07: data = 8'b01110000; + 08: data = 8'b01010001; + 09: data = 8'b11001011; + 10: data = 8'b11111001; + 11: data = 8'b00100001; + 12: data = 8'b01000001; + 13: data = 8'b00000001; + 14: data = 8'b00100010; + 15: data = 8'b01010000; + 16: data = 8'b00000010; + 17: data = 8'b01011110; + 18: data = 8'b11010100; + 19: data = 8'b11111001; + 20: data = 8'b00100000; + 21: data = 8'b01010001; + 22: data = 8'b00000000; + 23: data = 8'b11001011; + 24: data = 8'b11111100; + 25: data = 8'b00110000; + 26: data = 8'b00000010; + 27: data = 8'b11111100; + 28: data = 8'b00100010; + 29: data = 8'b0001xxxx; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file diff --git a/Verilog/instruction_memory_unsigned_multiplication.v b/Verilog/instruction_memory_unsigned_multiplication.v new file mode 100644 index 0000000..b9cfb6b --- /dev/null +++ b/Verilog/instruction_memory_unsigned_multiplication.v @@ -0,0 +1,44 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00111100; + 01: data = 8'b00000000; + 02: data = 8'b00111000; + 03: data = 8'b00000001; + 04: data = 8'b00100000; + 05: data = 8'b00000010; + 06: data = 8'b01110000; + 07: data = 8'b01000010; + 08: data = 8'b11001101; + 09: data = 8'b00100001; + 10: data = 8'b00000000; + 11: data = 8'b00100010; + 12: data = 8'b00000001; + 13: data = 8'b00110000; + 14: data = 8'b00000010; + 15: data = 8'b00100001; + 16: data = 8'b10110010; + 17: data = 8'b11111101; + 18: data = 8'b1000xxxx; + 19: data = 8'b00100010; + 20: data = 8'b01000000; + 21: data = 8'b00000010; + 22: data = 8'b00100011; + 23: data = 8'b01010000; + 24: data = 8'b00000011; + 25: data = 8'b00100001; + 26: data = 8'b01011111; + 27: data = 8'b00000001; + 28: data = 8'b10110010; + 29: data = 8'b00100010; + 30: data = 8'b00100011; + 31: data = 8'b0001xxxx; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file diff --git a/Verilog/instruction_memory_xor_xnor.v b/Verilog/instruction_memory_xor_xnor.v new file mode 100644 index 0000000..f1ce13e --- /dev/null +++ b/Verilog/instruction_memory_xor_xnor.v @@ -0,0 +1,29 @@ +module instruction_memory_fibonacci (address, data); + + input [4:0] address; + output reg [7:0] data; + + always @(address) begin + case(address) + 00: data = 8'b00110101; + 01: data = 8'b00000000; + 02: data = 8'b00110011; + 03: data = 8'b00000001; + 04: data = 8'b01100000; + 05: data = 8'b00000010; + 06: data = 8'b01100000; + 07: data = 8'b00000011; + 08: data = 8'b00100010; + 09: data = 8'b01100001; + 10: data = 8'b01100011; + 11: data = 8'b00000010; + 12: data = 8'b01100010; + 13: data = 8'b00000011; + 14: data = 8'b00100010; + 15: data = 8'b00100011; + 16: data = 8'b0001xxxx; + default: data = 8'b00; + endcase + end + +endmodule \ No newline at end of file