From f680b967c183dd88dd7e7e65b867e1a9c2bec617 Mon Sep 17 00:00:00 2001 From: mwish Date: Sun, 10 Mar 2024 01:00:21 +0800 Subject: [PATCH 1/3] Extract common/port.h and optimize dbstats --- src/common/port.h | 48 ++++++++++++++++++++++++++++++++++++++++ src/storage/storage.cc | 8 +++---- src/storage/storage.h | 13 ++++++----- src/types/redis_bitmap.h | 5 +---- 4 files changed, 60 insertions(+), 14 deletions(-) create mode 100644 src/common/port.h diff --git a/src/common/port.h b/src/common/port.h new file mode 100644 index 00000000000..67c9067bae3 --- /dev/null +++ b/src/common/port.h @@ -0,0 +1,48 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + * + */ + +#pragma once + +#if defined(__sparc__) || defined(__arm__) +#define USE_ALIGNED_ACCESS +#endif + +#ifndef CACHE_LINE_SIZE +// To test behavior with non-native cache line size, e.g. for +// Bloom filters, set TEST_CACHE_LINE_SIZE to the desired test size. +// This disables ALIGN_AS to keep it from failing compilation. +#ifdef TEST_CACHE_LINE_SIZE +#define CACHE_LINE_SIZE TEST_CACHE_LINE_SIZE +#define ALIGN_AS(n) /*empty*/ +#else +#if defined(__s390__) +#if defined(__GNUC__) && __GNUC__ < 7 +#define CACHE_LINE_SIZE 64U +#else +#define CACHE_LINE_SIZE 256U +#endif +#elif defined(__powerpc__) || defined(__aarch64__) +#define CACHE_LINE_SIZE 128U +#else +#define CACHE_LINE_SIZE 64U +#endif +#define ALIGN_AS(n) alignas(n) +#endif +#endif diff --git a/src/storage/storage.cc b/src/storage/storage.cc index 56cda4aede7..69603023a15 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -707,16 +707,16 @@ Status Storage::ApplyWriteBatch(const rocksdb::WriteOptions &options, std::strin void Storage::RecordStat(StatType type, uint64_t v) { switch (type) { case StatType::FlushCount: - db_stats_.flush_count += v; + db_stats_.flush_count.fetch_add(v, std::memory_order_relaxed); break; case StatType::CompactionCount: - db_stats_.compaction_count += v; + db_stats_.compaction_count.fetch_add(v, std::memory_order_relaxed); break; case StatType::KeyspaceHits: - db_stats_.keyspace_hits += v; + db_stats_.keyspace_hits.fetch_add(v, std::memory_order_relaxed); break; case StatType::KeyspaceMisses: - db_stats_.keyspace_misses += v; + db_stats_.keyspace_misses.fetch_add(v, std::memory_order_relaxed); break; } } diff --git a/src/storage/storage.h b/src/storage/storage.h index e36e77bdb46..ff73243d579 100644 --- a/src/storage/storage.h +++ b/src/storage/storage.h @@ -36,6 +36,7 @@ #include #include +#include "common/port.h" #include "config/config.h" #include "lock_manager.h" #include "observer_or_unique.h" @@ -107,18 +108,18 @@ inline const std::vector CacheOptions = { {BlockCacheType::kCacheTypeHCC, "hcc", "kCacheTypeHCC"}, }; -enum class StatType { +enum class StatType : uint_fast8_t { CompactionCount, FlushCount, KeyspaceHits, KeyspaceMisses, }; -struct DBStats { - std::atomic compaction_count = 0; - std::atomic flush_count = 0; - std::atomic keyspace_hits = 0; - std::atomic keyspace_misses = 0; +struct alignas(CACHE_LINE_SIZE) DBStats { + std::atomic compaction_count = 0; + std::atomic flush_count = 0; + std::atomic keyspace_hits = 0; + std::atomic keyspace_misses = 0; }; class Storage { diff --git a/src/types/redis_bitmap.h b/src/types/redis_bitmap.h index 9466593deb6..349982d8ce6 100644 --- a/src/types/redis_bitmap.h +++ b/src/types/redis_bitmap.h @@ -25,13 +25,10 @@ #include #include "common/bitfield_util.h" +#include "common/port.h" #include "storage/redis_db.h" #include "storage/redis_metadata.h" -#if defined(__sparc__) || defined(__arm__) -#define USE_ALIGNED_ACCESS -#endif - enum BitOpFlags { kBitOpAnd, kBitOpOr, From ca9bef1f28b22a592388bd28e125d682e3443622 Mon Sep 17 00:00:00 2001 From: mwish Date: Sun, 10 Mar 2024 01:21:14 +0800 Subject: [PATCH 2/3] try to fix lint --- src/common/port.h | 17 ++++------------- 1 file changed, 4 insertions(+), 13 deletions(-) diff --git a/src/common/port.h b/src/common/port.h index 67c9067bae3..7d6ce9f6505 100644 --- a/src/common/port.h +++ b/src/common/port.h @@ -25,24 +25,15 @@ #endif #ifndef CACHE_LINE_SIZE -// To test behavior with non-native cache line size, e.g. for -// Bloom filters, set TEST_CACHE_LINE_SIZE to the desired test size. -// This disables ALIGN_AS to keep it from failing compilation. -#ifdef TEST_CACHE_LINE_SIZE -#define CACHE_LINE_SIZE TEST_CACHE_LINE_SIZE -#define ALIGN_AS(n) /*empty*/ -#else #if defined(__s390__) #if defined(__GNUC__) && __GNUC__ < 7 -#define CACHE_LINE_SIZE 64U +constexpr size_t CACHE_LINE_SIZE = 64U; #else -#define CACHE_LINE_SIZE 256U +constexpr size_t CACHE_LINE_SIZE = 256U; #endif #elif defined(__powerpc__) || defined(__aarch64__) -#define CACHE_LINE_SIZE 128U +constexpr size_t CACHE_LINE_SIZE = 128U; #else -#define CACHE_LINE_SIZE 64U -#endif -#define ALIGN_AS(n) alignas(n) +constexpr size_t CACHE_LINE_SIZE = 64U; #endif #endif From c1fad2009aaf4ede51a4d47900d7f626abc9f94f Mon Sep 17 00:00:00 2001 From: mwish Date: Sun, 10 Mar 2024 11:55:13 +0800 Subject: [PATCH 3/3] remove macro check in CACHE_LINE_SIZE, adjust DBstats, and changing DBStats to unique_ptr --- src/common/port.h | 2 -- src/storage/storage.cc | 14 +++++++++----- src/storage/storage.h | 14 +++++++------- 3 files changed, 16 insertions(+), 14 deletions(-) diff --git a/src/common/port.h b/src/common/port.h index 7d6ce9f6505..023e75447f1 100644 --- a/src/common/port.h +++ b/src/common/port.h @@ -24,7 +24,6 @@ #define USE_ALIGNED_ACCESS #endif -#ifndef CACHE_LINE_SIZE #if defined(__s390__) #if defined(__GNUC__) && __GNUC__ < 7 constexpr size_t CACHE_LINE_SIZE = 64U; @@ -36,4 +35,3 @@ constexpr size_t CACHE_LINE_SIZE = 128U; #else constexpr size_t CACHE_LINE_SIZE = 64U; #endif -#endif diff --git a/src/storage/storage.cc b/src/storage/storage.cc index 69603023a15..94a6e64da8d 100644 --- a/src/storage/storage.cc +++ b/src/storage/storage.cc @@ -75,7 +75,11 @@ const int64_t kIORateLimitMaxMb = 1024000; using rocksdb::Slice; Storage::Storage(Config *config) - : backup_creating_time_(util::GetTimeStamp()), env_(rocksdb::Env::Default()), config_(config), lock_mgr_(16) { + : backup_creating_time_(util::GetTimeStamp()), + env_(rocksdb::Env::Default()), + config_(config), + lock_mgr_(16), + db_stats_(std::make_unique()) { Metadata::InitVersionCounter(); SetWriteOptions(config->rocks_db.write_options); } @@ -707,16 +711,16 @@ Status Storage::ApplyWriteBatch(const rocksdb::WriteOptions &options, std::strin void Storage::RecordStat(StatType type, uint64_t v) { switch (type) { case StatType::FlushCount: - db_stats_.flush_count.fetch_add(v, std::memory_order_relaxed); + db_stats_->flush_count.fetch_add(v, std::memory_order_relaxed); break; case StatType::CompactionCount: - db_stats_.compaction_count.fetch_add(v, std::memory_order_relaxed); + db_stats_->compaction_count.fetch_add(v, std::memory_order_relaxed); break; case StatType::KeyspaceHits: - db_stats_.keyspace_hits.fetch_add(v, std::memory_order_relaxed); + db_stats_->keyspace_hits.fetch_add(v, std::memory_order_relaxed); break; case StatType::KeyspaceMisses: - db_stats_.keyspace_misses.fetch_add(v, std::memory_order_relaxed); + db_stats_->keyspace_misses.fetch_add(v, std::memory_order_relaxed); break; } } diff --git a/src/storage/storage.h b/src/storage/storage.h index ff73243d579..3627ad6441e 100644 --- a/src/storage/storage.h +++ b/src/storage/storage.h @@ -115,11 +115,11 @@ enum class StatType : uint_fast8_t { KeyspaceMisses, }; -struct alignas(CACHE_LINE_SIZE) DBStats { - std::atomic compaction_count = 0; - std::atomic flush_count = 0; - std::atomic keyspace_hits = 0; - std::atomic keyspace_misses = 0; +struct DBStats { + alignas(CACHE_LINE_SIZE) std::atomic compaction_count = 0; + alignas(CACHE_LINE_SIZE) std::atomic flush_count = 0; + alignas(CACHE_LINE_SIZE) std::atomic keyspace_hits = 0; + alignas(CACHE_LINE_SIZE) std::atomic keyspace_misses = 0; }; class Storage { @@ -196,7 +196,7 @@ class Storage { bool IsSlotIdEncoded() const { return config_->slot_id_encoded; } Config *GetConfig() const { return config_; } - const DBStats *GetDBStats() const { return &db_stats_; } + const DBStats *GetDBStats() const { return db_stats_.get(); } void RecordStat(StatType type, uint64_t v); Status BeginTxn(); @@ -262,7 +262,7 @@ class Storage { LockManager lock_mgr_; std::atomic db_size_limit_reached_{false}; - DBStats db_stats_; + std::unique_ptr db_stats_; std::shared_mutex db_rw_lock_; bool db_closing_ = true;