From 907d68ce69a0a7ab106740ef24607069a0a6b43b Mon Sep 17 00:00:00 2001 From: iabdalkader Date: Fri, 10 May 2024 14:46:00 +0200 Subject: [PATCH] libraries/Arduino_H7_Video: Fix the DSI PLL configuration. With the current configuration (NDIV=125, PLLIDF=3, PLLODF=1) the DSI PLL outputs an out of spec 83MHz clock. This fix sets the output clock to the max supported clock of 62.5MHz, according to the datasheet. Signed-off-by: iabdalkader --- libraries/Arduino_H7_Video/src/dsi.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/libraries/Arduino_H7_Video/src/dsi.cpp b/libraries/Arduino_H7_Video/src/dsi.cpp index b79a0a9d8..77541d71c 100644 --- a/libraries/Arduino_H7_Video/src/dsi.cpp +++ b/libraries/Arduino_H7_Video/src/dsi.cpp @@ -48,7 +48,7 @@ static void dsi_layerInit(uint16_t LayerIndex, uint32_t FB_Address); int dsi_init(uint8_t bus, struct edid *edid, struct display_timing *dt) { #ifdef ARDUINO_GIGA static const uint32_t DSI_PLLNDIV = 125; - static const uint32_t DSI_PLLIDF = DSI_PLL_IN_DIV3; + static const uint32_t DSI_PLLIDF = DSI_PLL_IN_DIV4; static const uint32_t DSI_PLLODF = DSI_PLL_OUT_DIV1; static const uint32_t DSI_TXEXCAPECLOCKDIV = 4; #undef HSE_VALUE @@ -412,4 +412,4 @@ extern "C" void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc) { reloadLTDC_status = 1; } -/**** END OF FILE ****/ \ No newline at end of file +/**** END OF FILE ****/