chore: clippy and fmt

core/src/alu/divrem/mod.rs

@@ -375,7 +375,7 @@ impl<F: PrimeField> MachineAir<F> for DivRemChip {
                                 opcode: Opcode::ADD,
                                 a: 0,
                                 b: event.c,
-                                c: (event.c as i32).abs() as u32,
+                                c: (event.c as i32).unsigned_abs(),
                                 sub_lookups: create_alu_lookups(),
                             })
                         }
@@ -388,7 +388,7 @@ impl<F: PrimeField> MachineAir<F> for DivRemChip {
                                 opcode: Opcode::ADD,
                                 a: 0,
                                 b: remainder,
-                                c: (remainder as i32).abs() as u32,
+                                c: (remainder as i32).unsigned_abs(),
                                 sub_lookups: create_alu_lookups(),
                             })
                         }

core/src/cpu/air/branch.rs

@@ -1,7 +1,7 @@
 use p3_air::AirBuilder;
 use p3_field::AbstractField;
 
-use crate::air::{AluAirBuilder, BaseAirBuilder, SphinxAirBuilder, Word, WordAirBuilder};
+use crate::air::{AluAirBuilder, BaseAirBuilder, Word, WordAirBuilder};
 use crate::cpu::columns::{CpuCols, OpcodeSelectorCols};
 use crate::operations::BabyBearWordRangeChecker;
 use crate::{cpu::CpuChip, runtime::Opcode};
@@ -31,7 +31,7 @@ impl CpuChip {
     pub(crate) fn eval_branch_ops<AB: AluAirBuilder>(
         &self,
         builder: &mut AB,
-        is_branch_instruction: AB::Expr,
+        is_branch_instruction: &AB::Expr,
         local: &CpuCols<AB::Var>,
         next: &CpuCols<AB::Var>,
     ) {

core/src/cpu/air/ecall.rs

@@ -41,7 +41,7 @@ impl CpuChip {
         // - is_ecall_instruction = 0 => ecall_mul_send_to_table == 0
         builder.assert_eq(
             local.ecall_mul_send_to_table,
-            send_to_table * is_ecall_instruction.clone(),
+            send_to_table * is_ecall_instruction,
         );
 
         builder.send_syscall(

core/src/cpu/air/mod.rs

@@ -95,7 +95,7 @@ where
         );
 
         // Branch instructions.
-        self.eval_branch_ops::<AB>(builder, is_branch_instruction.clone(), local, next);
+        self.eval_branch_ops::<AB>(builder, &is_branch_instruction, local, next);
 
         // Jump instructions.
         self.eval_jump_ops::<AB>(builder, local, next);

core/src/cpu/trace.rs

@@ -12,7 +12,7 @@ use super::{CpuChip, CpuEvent};
 use crate::air::Word;
 use crate::air::{EventLens, MachineAir, WithEvents};
 use crate::alu::create_alu_lookups;
-use crate::alu::{self, AluEvent};
+use crate::alu::AluEvent;
 use crate::bytes::event::ByteRecord;
 use crate::bytes::{ByteLookupEvent, ByteOpcode};
 use crate::cpu::columns::CpuCols;
@@ -48,7 +48,7 @@ impl<F: PrimeField32> MachineAir<F> for CpuChip {
         // Generate the trace rows for each event.
         let mut rows_with_events = events
             .par_iter()
-            .map(|op: &CpuEvent| self.event_to_row::<F>(*op, &nonce_lookup))
+            .map(|op: &CpuEvent| self.event_to_row::<F>(*op, nonce_lookup))
             .collect::<Vec<_>>();
 
         // No need to sort by the shard, since the cpu events are already partitioned by that.
@@ -97,13 +97,13 @@ impl<F: PrimeField32> MachineAir<F> for CpuChip {
             .map(|ops: &[CpuEvent]| {
                 let mut alu = HashMap::new();
                 let mut blu: Vec<_> = Vec::default();
-                ops.iter().for_each(|op| {
+                for op in ops.iter() {
                     let (_, alu_events, blu_events) = self.event_to_row::<F>(*op, &HashMap::new());
-                    alu_events.into_iter().for_each(|(key, value)| {
+                    for (key, value) in alu_events {
                         alu.entry(key).or_insert(Vec::default()).extend(value);
-                    });
+                    }
                     blu.extend(blu_events);
-                });
+                }
                 (alu, blu)
             })
             .collect::<Vec<_>>();
@@ -187,7 +187,7 @@ impl CpuChip {
         new_blu_events.push(ByteLookupEvent {
             shard: event.shard,
             channel: event.channel,
-            opcode: ByteOpcode::U8Range,
+            opcode: U8Range,
             a1: 0,
             a2: 0,
             b: a_bytes[0],
@@ -196,7 +196,7 @@ impl CpuChip {
         new_blu_events.push(ByteLookupEvent {
             shard: event.shard,
             channel: event.channel,
-            opcode: ByteOpcode::U8Range,
+            opcode: U8Range,
             a1: 0,
             a2: 0,
             b: a_bytes[2],
@@ -439,7 +439,7 @@ impl CpuChip {
         &self,
         cols: &mut CpuCols<F>,
         event: CpuEvent,
-        alu_events: &mut HashMap<Opcode, Vec<alu::AluEvent>>,
+        alu_events: &mut HashMap<Opcode, Vec<AluEvent>>,
         nonce_lookup: &HashMap<usize, u32>,
     ) {
         if event.instruction.is_branch_instruction() {
@@ -568,7 +568,7 @@ impl CpuChip {
         &self,
         cols: &mut CpuCols<F>,
         event: CpuEvent,
-        alu_events: &mut HashMap<Opcode, Vec<alu::AluEvent>>,
+        alu_events: &mut HashMap<Opcode, Vec<AluEvent>>,
         nonce_lookup: &HashMap<usize, u32>,
     ) {
         if event.instruction.is_jump_instruction() {
@@ -645,7 +645,7 @@ impl CpuChip {
         &self,
         cols: &mut CpuCols<F>,
         event: CpuEvent,
-        alu_events: &mut HashMap<Opcode, Vec<alu::AluEvent>>,
+        alu_events: &mut HashMap<Opcode, Vec<AluEvent>>,
         nonce_lookup: &HashMap<usize, u32>,
     ) {
         if matches!(event.instruction.opcode, Opcode::AUIPC) {

core/src/memory/global.rs

@@ -8,7 +8,7 @@ use p3_matrix::{dense::RowMajorMatrix, Matrix};
 use sphinx_derive::AlignedBorrow;
 
 use super::MemoryInitializeFinalizeEvent;
-use crate::air::{AirInteraction, BaseAirBuilder, SphinxAirBuilder};
+use crate::air::{AirInteraction, BaseAirBuilder};
 use crate::air::{EventLens, MachineAir, WithEvents};
 use crate::operations::BabyBearBitDecomposition;
 use crate::runtime::{ExecutionRecord, Program};

core/src/operations/baby_bear_range.rs

@@ -4,7 +4,7 @@ use p3_air::AirBuilder;
 use p3_field::{AbstractField, Field};
 use sphinx_derive::AlignedBorrow;
 
-use crate::{air::ByteAirBuilder, stark::SphinxAirBuilder};
+use crate::air::ByteAirBuilder;
 
 #[derive(AlignedBorrow, Default, Debug, Clone, Copy)]
 #[repr(C)]

core/src/operations/baby_bear_word.rs

@@ -4,10 +4,7 @@ use p3_air::AirBuilder;
 use p3_field::{AbstractField, Field};
 use sphinx_derive::AlignedBorrow;
 
-use crate::{
-    air::{ByteAirBuilder, Word},
-    stark::SphinxAirBuilder,
-};
+use crate::air::{ByteAirBuilder, Word};
 
 /// A set of columns needed to compute the add of two words.
 #[derive(AlignedBorrow, Default, Debug, Clone, Copy)]

core/src/operations/field/field_op.rs

@@ -452,7 +452,7 @@ mod tests {
 
             let mut challenger = config.challenger();
 
-            let chip: FieldOpChip<Ed25519BaseField> = FieldOpChip::new(*op);
+            let chip: FieldOpChip<F> = FieldOpChip::new(*op);
             let shard = ExecutionRecord::default();
             let trace: RowMajorMatrix<BabyBear> =
                 chip.generate_trace(&shard, &mut ExecutionRecord::default());

core/src/operations/field/field_sqrt.rs

@@ -9,7 +9,6 @@ use super::params::Limbs;
 use super::range::FieldRangeCols;
 use crate::air::WordAirBuilder;
 use crate::bytes::event::ByteRecord;
-use crate::bytes::{ByteLookupEvent, ByteOpcode};
 use crate::operations::field::params::FieldParameters;
 
 /// A set of columns to compute the square root in emulated arithmetic.
@@ -87,9 +86,9 @@ impl<V: Copy, P: FieldParameters> FieldSqrtCols<V, P> {
         &self,
         builder: &mut AB,
         a: &Limbs<AB::Var, P::NB_LIMBS>,
-        shard: impl Into<AB::Expr> + Clone,
-        channel: impl Into<AB::Expr> + Clone,
-        is_real: impl Into<AB::Expr> + Clone,
+        shard: &(impl Into<AB::Expr> + Clone),
+        channel: &(impl Into<AB::Expr> + Clone),
+        is_real: &(impl Into<AB::Expr> + Clone),
     ) where
         V: Into<AB::Expr>,
     {
@@ -264,9 +263,13 @@ mod tests {
             let local: &TestCols<AB::Var, P> = (*local).borrow();
 
             // eval verifies that local.sqrt.result is indeed the square root of local.a.
-            local
-                .sqrt
-                .eval(builder, &local.a, AB::F::one(), AB::F::zero(), AB::F::one());
+            local.sqrt.eval(
+                builder,
+                &local.a,
+                &AB::F::one(),
+                &AB::F::zero(),
+                &AB::F::one(),
+            );
         }
     }
 

core/src/runtime/mod.rs

@@ -893,17 +893,17 @@ impl Runtime {
             }
             Opcode::MULH => {
                 (rd, b, c) = self.alu_rr(instruction);
-                a = (((b as i32) as i64).wrapping_mul((c as i32) as i64) >> 32) as u32;
+                a = (i64::from(b as i32).wrapping_mul(i64::from(c as i32)) >> 32) as u32;
                 self.alu_rw(instruction, rd, a, b, c, lookup_id);
             }
             Opcode::MULHU => {
                 (rd, b, c) = self.alu_rr(instruction);
-                a = ((b as u64).wrapping_mul(c as u64) >> 32) as u32;
+                a = (u64::from(b).wrapping_mul(u64::from(c)) >> 32) as u32;
                 self.alu_rw(instruction, rd, a, b, c, lookup_id);
             }
             Opcode::MULHSU => {
                 (rd, b, c) = self.alu_rr(instruction);
-                a = (((b as i32) as i64).wrapping_mul(c as i64) >> 32) as u32;
+                a = (i64::from(b as i32).wrapping_mul(i64::from(c)) >> 32) as u32;
                 self.alu_rw(instruction, rd, a, b, c, lookup_id);
             }
             Opcode::DIV => {

core/src/runtime/record.rs

@@ -904,38 +904,37 @@ impl MachineRecord for ExecutionRecord {
         let first = shards.first_mut().unwrap();
 
         // SHA-256 extend events.
-        first.sha_extend_events = std::mem::take(&mut self.sha_extend_events);
+        first.sha_extend_events = take(&mut self.sha_extend_events);
         for (i, event) in first.sha_extend_events.iter().enumerate() {
             self.nonce_lookup.insert(event.lookup_id, (i * 48) as u32);
         }
 
         // SHA-256 compress events.
-        first.sha_compress_events = std::mem::take(&mut self.sha_compress_events);
+        first.sha_compress_events = take(&mut self.sha_compress_events);
         for (i, event) in first.sha_compress_events.iter().enumerate() {
             self.nonce_lookup.insert(event.lookup_id, (i * 80) as u32);
         }
 
         // Edwards curve add events.
-        first.ed_add_events = std::mem::take(&mut self.ed_add_events);
+        first.ed_add_events = take(&mut self.ed_add_events);
         for (i, event) in first.ed_add_events.iter().enumerate() {
             self.nonce_lookup.insert(event.lookup_id, i as u32);
         }
 
         // Edwards curve decompress events.
-        first.ed_decompress_events = std::mem::take(&mut self.ed_decompress_events);
+        first.ed_decompress_events = take(&mut self.ed_decompress_events);
         for (i, event) in first.ed_decompress_events.iter().enumerate() {
             self.nonce_lookup.insert(event.lookup_id, i as u32);
         }
 
         // K256 curve decompress events.
-        first.secp256k1_decompress_events = std::mem::take(&mut self.secp256k1_decompress_events);
+        first.secp256k1_decompress_events = take(&mut self.secp256k1_decompress_events);
         for (i, event) in first.secp256k1_decompress_events.iter().enumerate() {
             self.nonce_lookup.insert(event.lookup_id, i as u32);
         }
 
         // Bls12-381 decompress events.
-        first.bls12381_g1_decompress_events =
-            std::mem::take(&mut self.bls12381_g1_decompress_events);
+        first.bls12381_g1_decompress_events = take(&mut self.bls12381_g1_decompress_events);
         for (i, event) in first.bls12381_g1_decompress_events.iter().enumerate() {
             self.nonce_lookup.insert(event.lookup_id, i as u32);
         }

core/src/runtime/syscall.rs

@@ -487,12 +487,6 @@ mod tests {
                 SyscallCode::BLS12381_FP2_MUL => {
                     assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_FP2_MUL)
                 }
-                SyscallCode::BLS12381_G1_ADD => {
-                    assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_G1_ADD)
-                }
-                SyscallCode::BLS12381_G1_DOUBLE => {
-                    assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_G1_DOUBLE)
-                }
                 SyscallCode::COMMIT => assert_eq!(code as u32, sphinx_zkvm::syscalls::COMMIT),
                 SyscallCode::BLS12381_G1_DECOMPRESS => {
                     assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_G1_DECOMPRESS)

core/src/stark/air.rs

@@ -188,13 +188,13 @@ impl<F: PrimeField32> RiscvAir<F> {
         chips.push(RiscvAir::Bls12381G2Add(bls12381_g2_add));
         let bls12381_g2_double = Bls12381G2AffineDoubleChip::new();
         chips.push(RiscvAir::Bls12381G2AffineDouble(bls12381_g2_double));
-        let div_rem = DivRemChip::default();
+        let div_rem = DivRemChip;
         chips.push(RiscvAir::DivRem(div_rem));
-        let add = AddSubChip::default();
+        let add = AddSubChip;
         chips.push(RiscvAir::Add(add));
         let bitwise = BitwiseChip;
         chips.push(RiscvAir::Bitwise(bitwise));
-        let mul = MulChip::default();
+        let mul = MulChip;
         chips.push(RiscvAir::Mul(mul));
         let shift_right = ShiftRightChip;
         chips.push(RiscvAir::ShiftRight(shift_right));

core/src/syscall/precompiles/bls12_381/g1_decompress.rs

@@ -444,9 +444,9 @@ where
         row.y.eval(
             builder,
             &row.x_3_plus_b.result,
-            row.shard,
-            row.channel,
-            row.is_real,
+            &row.shard,
+            &row.channel,
+            &row.is_real,
         );
         row.two_y.eval(
             builder,

core/src/syscall/precompiles/edwards/ed_add.rs

@@ -20,7 +20,6 @@ use sphinx_derive::AlignedBorrow;
 
 use crate::air::BaseAirBuilder;
 use crate::bytes::ByteLookupEvent;
-use crate::memory::MemoryCols;
 use crate::memory::MemoryReadCols;
 use crate::memory::MemoryWriteCols;
 use crate::operations::field::field_den::FieldDenCols;

core/src/syscall/precompiles/edwards/ed_decompress.rs

@@ -237,9 +237,9 @@ impl<V: Copy, P: FieldParameters> EdDecompressCols<V, P> {
         self.x.eval(
             builder,
             &self.u_div_v.result,
-            self.shard,
-            self.channel,
-            self.is_real,
+            &self.shard,
+            &self.channel,
+            &self.is_real,
         );
         self.neg_x.eval(
             builder,

core/src/syscall/precompiles/keccak256/columns.rs

@@ -16,11 +16,11 @@ pub(crate) struct KeccakMemCols<T> {
     /// Keccak columns from p3_keccak_air. Note it is assumed in trace gen to be the first field.
     pub(crate) keccak: KeccakCols<T>,
 
-    pub shard: T,
-    pub channel: T,
-    pub clk: T,
-    pub nonce: T,
-    pub state_addr: T,
+    pub(crate) shard: T,
+    pub(crate) channel: T,
+    pub(crate) clk: T,
+    pub(crate) nonce: T,
+    pub(crate) state_addr: T,
 
     /// Memory columns for the state.
     pub(crate) state_mem: [MemoryReadWriteCols<T>; STATE_NUM_WORDS],

core/src/syscall/precompiles/secp256k1/decompress.rs

@@ -383,9 +383,9 @@ where
         row.y.eval(
             builder,
             &row.x_3_plus_b.result,
-            row.shard,
-            row.channel,
-            row.is_real,
+            &row.shard,
+            &row.channel,
+            &row.is_real,
         );
         row.neg_y.eval(
             builder,

core/src/syscall/precompiles/sha256/extend/flags.rs

@@ -6,7 +6,6 @@ use p3_field::{AbstractField, Field, PrimeField32, TwoAdicField};
 use p3_matrix::Matrix;
 
 use crate::air::BaseAirBuilder;
-use crate::air::SphinxAirBuilder;
 use crate::operations::IsZeroOperation;
 
 use super::ShaExtendChip;

recursion/core/src/poseidon2/external.rs

@@ -4,7 +4,7 @@ use p3_air::AirBuilder;
 use p3_air::{Air, BaseAir};
 use p3_field::{AbstractField, Field};
 use p3_matrix::Matrix;
-use sphinx_core::air::{BaseAirBuilder, ExtensionAirBuilder, SphinxAirBuilder};
+use sphinx_core::air::{BaseAirBuilder, ExtensionAirBuilder};
 use sphinx_primitives::RC_16_30_U32;
 use std::marker::PhantomData;