From 680a0953efd7e7f1920770aaa3bf93afd2b86262 Mon Sep 17 00:00:00 2001 From: wwared Date: Tue, 18 Jun 2024 17:35:50 -0300 Subject: [PATCH] chore: clippy and fmt --- core/src/alu/divrem/mod.rs | 4 ++-- core/src/cpu/air/branch.rs | 4 ++-- core/src/cpu/air/ecall.rs | 2 +- core/src/cpu/air/mod.rs | 2 +- core/src/cpu/trace.rs | 22 +++++++++---------- core/src/memory/global.rs | 2 +- core/src/operations/baby_bear_range.rs | 2 +- core/src/operations/baby_bear_word.rs | 5 +---- core/src/operations/field/field_op.rs | 2 +- core/src/operations/field/field_sqrt.rs | 17 ++++++++------ core/src/runtime/mod.rs | 6 ++--- core/src/runtime/record.rs | 13 +++++------ core/src/runtime/syscall.rs | 6 ----- core/src/stark/air.rs | 6 ++--- .../precompiles/bls12_381/g1_decompress.rs | 6 ++--- .../src/syscall/precompiles/edwards/ed_add.rs | 1 - .../precompiles/edwards/ed_decompress.rs | 6 ++--- .../syscall/precompiles/keccak256/columns.rs | 10 ++++----- .../precompiles/secp256k1/decompress.rs | 6 ++--- .../precompiles/sha256/extend/flags.rs | 1 - recursion/core/src/poseidon2/external.rs | 2 +- 21 files changed, 58 insertions(+), 67 deletions(-) diff --git a/core/src/alu/divrem/mod.rs b/core/src/alu/divrem/mod.rs index 261248952..ebcbd8c4a 100644 --- a/core/src/alu/divrem/mod.rs +++ b/core/src/alu/divrem/mod.rs @@ -375,7 +375,7 @@ impl MachineAir for DivRemChip { opcode: Opcode::ADD, a: 0, b: event.c, - c: (event.c as i32).abs() as u32, + c: (event.c as i32).unsigned_abs(), sub_lookups: create_alu_lookups(), }) } @@ -388,7 +388,7 @@ impl MachineAir for DivRemChip { opcode: Opcode::ADD, a: 0, b: remainder, - c: (remainder as i32).abs() as u32, + c: (remainder as i32).unsigned_abs(), sub_lookups: create_alu_lookups(), }) } diff --git a/core/src/cpu/air/branch.rs b/core/src/cpu/air/branch.rs index c7a45645f..8f3040c03 100644 --- a/core/src/cpu/air/branch.rs +++ b/core/src/cpu/air/branch.rs @@ -1,7 +1,7 @@ use p3_air::AirBuilder; use p3_field::AbstractField; -use crate::air::{AluAirBuilder, BaseAirBuilder, SphinxAirBuilder, Word, WordAirBuilder}; +use crate::air::{AluAirBuilder, BaseAirBuilder, Word, WordAirBuilder}; use crate::cpu::columns::{CpuCols, OpcodeSelectorCols}; use crate::operations::BabyBearWordRangeChecker; use crate::{cpu::CpuChip, runtime::Opcode}; @@ -31,7 +31,7 @@ impl CpuChip { pub(crate) fn eval_branch_ops( &self, builder: &mut AB, - is_branch_instruction: AB::Expr, + is_branch_instruction: &AB::Expr, local: &CpuCols, next: &CpuCols, ) { diff --git a/core/src/cpu/air/ecall.rs b/core/src/cpu/air/ecall.rs index 9dd7e208b..1cbb630f8 100644 --- a/core/src/cpu/air/ecall.rs +++ b/core/src/cpu/air/ecall.rs @@ -41,7 +41,7 @@ impl CpuChip { // - is_ecall_instruction = 0 => ecall_mul_send_to_table == 0 builder.assert_eq( local.ecall_mul_send_to_table, - send_to_table * is_ecall_instruction.clone(), + send_to_table * is_ecall_instruction, ); builder.send_syscall( diff --git a/core/src/cpu/air/mod.rs b/core/src/cpu/air/mod.rs index e6bfec9e6..3a0b02989 100644 --- a/core/src/cpu/air/mod.rs +++ b/core/src/cpu/air/mod.rs @@ -95,7 +95,7 @@ where ); // Branch instructions. - self.eval_branch_ops::(builder, is_branch_instruction.clone(), local, next); + self.eval_branch_ops::(builder, &is_branch_instruction, local, next); // Jump instructions. self.eval_jump_ops::(builder, local, next); diff --git a/core/src/cpu/trace.rs b/core/src/cpu/trace.rs index 960ff722c..db9e7f5ec 100644 --- a/core/src/cpu/trace.rs +++ b/core/src/cpu/trace.rs @@ -12,7 +12,7 @@ use super::{CpuChip, CpuEvent}; use crate::air::Word; use crate::air::{EventLens, MachineAir, WithEvents}; use crate::alu::create_alu_lookups; -use crate::alu::{self, AluEvent}; +use crate::alu::AluEvent; use crate::bytes::event::ByteRecord; use crate::bytes::{ByteLookupEvent, ByteOpcode}; use crate::cpu::columns::CpuCols; @@ -48,7 +48,7 @@ impl MachineAir for CpuChip { // Generate the trace rows for each event. let mut rows_with_events = events .par_iter() - .map(|op: &CpuEvent| self.event_to_row::(*op, &nonce_lookup)) + .map(|op: &CpuEvent| self.event_to_row::(*op, nonce_lookup)) .collect::>(); // No need to sort by the shard, since the cpu events are already partitioned by that. @@ -97,13 +97,13 @@ impl MachineAir for CpuChip { .map(|ops: &[CpuEvent]| { let mut alu = HashMap::new(); let mut blu: Vec<_> = Vec::default(); - ops.iter().for_each(|op| { + for op in ops.iter() { let (_, alu_events, blu_events) = self.event_to_row::(*op, &HashMap::new()); - alu_events.into_iter().for_each(|(key, value)| { + for (key, value) in alu_events { alu.entry(key).or_insert(Vec::default()).extend(value); - }); + } blu.extend(blu_events); - }); + } (alu, blu) }) .collect::>(); @@ -187,7 +187,7 @@ impl CpuChip { new_blu_events.push(ByteLookupEvent { shard: event.shard, channel: event.channel, - opcode: ByteOpcode::U8Range, + opcode: U8Range, a1: 0, a2: 0, b: a_bytes[0], @@ -196,7 +196,7 @@ impl CpuChip { new_blu_events.push(ByteLookupEvent { shard: event.shard, channel: event.channel, - opcode: ByteOpcode::U8Range, + opcode: U8Range, a1: 0, a2: 0, b: a_bytes[2], @@ -439,7 +439,7 @@ impl CpuChip { &self, cols: &mut CpuCols, event: CpuEvent, - alu_events: &mut HashMap>, + alu_events: &mut HashMap>, nonce_lookup: &HashMap, ) { if event.instruction.is_branch_instruction() { @@ -568,7 +568,7 @@ impl CpuChip { &self, cols: &mut CpuCols, event: CpuEvent, - alu_events: &mut HashMap>, + alu_events: &mut HashMap>, nonce_lookup: &HashMap, ) { if event.instruction.is_jump_instruction() { @@ -645,7 +645,7 @@ impl CpuChip { &self, cols: &mut CpuCols, event: CpuEvent, - alu_events: &mut HashMap>, + alu_events: &mut HashMap>, nonce_lookup: &HashMap, ) { if matches!(event.instruction.opcode, Opcode::AUIPC) { diff --git a/core/src/memory/global.rs b/core/src/memory/global.rs index 272cbdd25..5bad9d087 100644 --- a/core/src/memory/global.rs +++ b/core/src/memory/global.rs @@ -8,7 +8,7 @@ use p3_matrix::{dense::RowMajorMatrix, Matrix}; use sphinx_derive::AlignedBorrow; use super::MemoryInitializeFinalizeEvent; -use crate::air::{AirInteraction, BaseAirBuilder, SphinxAirBuilder}; +use crate::air::{AirInteraction, BaseAirBuilder}; use crate::air::{EventLens, MachineAir, WithEvents}; use crate::operations::BabyBearBitDecomposition; use crate::runtime::{ExecutionRecord, Program}; diff --git a/core/src/operations/baby_bear_range.rs b/core/src/operations/baby_bear_range.rs index 8636bab8f..aa7b0b0f4 100644 --- a/core/src/operations/baby_bear_range.rs +++ b/core/src/operations/baby_bear_range.rs @@ -4,7 +4,7 @@ use p3_air::AirBuilder; use p3_field::{AbstractField, Field}; use sphinx_derive::AlignedBorrow; -use crate::{air::ByteAirBuilder, stark::SphinxAirBuilder}; +use crate::air::ByteAirBuilder; #[derive(AlignedBorrow, Default, Debug, Clone, Copy)] #[repr(C)] diff --git a/core/src/operations/baby_bear_word.rs b/core/src/operations/baby_bear_word.rs index b892339ff..087d16ed0 100644 --- a/core/src/operations/baby_bear_word.rs +++ b/core/src/operations/baby_bear_word.rs @@ -4,10 +4,7 @@ use p3_air::AirBuilder; use p3_field::{AbstractField, Field}; use sphinx_derive::AlignedBorrow; -use crate::{ - air::{ByteAirBuilder, Word}, - stark::SphinxAirBuilder, -}; +use crate::air::{ByteAirBuilder, Word}; /// A set of columns needed to compute the add of two words. #[derive(AlignedBorrow, Default, Debug, Clone, Copy)] diff --git a/core/src/operations/field/field_op.rs b/core/src/operations/field/field_op.rs index 9ae0335d5..b85c45fc7 100644 --- a/core/src/operations/field/field_op.rs +++ b/core/src/operations/field/field_op.rs @@ -452,7 +452,7 @@ mod tests { let mut challenger = config.challenger(); - let chip: FieldOpChip = FieldOpChip::new(*op); + let chip: FieldOpChip = FieldOpChip::new(*op); let shard = ExecutionRecord::default(); let trace: RowMajorMatrix = chip.generate_trace(&shard, &mut ExecutionRecord::default()); diff --git a/core/src/operations/field/field_sqrt.rs b/core/src/operations/field/field_sqrt.rs index 14ad76b63..b5f3e284e 100644 --- a/core/src/operations/field/field_sqrt.rs +++ b/core/src/operations/field/field_sqrt.rs @@ -9,7 +9,6 @@ use super::params::Limbs; use super::range::FieldRangeCols; use crate::air::WordAirBuilder; use crate::bytes::event::ByteRecord; -use crate::bytes::{ByteLookupEvent, ByteOpcode}; use crate::operations::field::params::FieldParameters; /// A set of columns to compute the square root in emulated arithmetic. @@ -87,9 +86,9 @@ impl FieldSqrtCols { &self, builder: &mut AB, a: &Limbs, - shard: impl Into + Clone, - channel: impl Into + Clone, - is_real: impl Into + Clone, + shard: &(impl Into + Clone), + channel: &(impl Into + Clone), + is_real: &(impl Into + Clone), ) where V: Into, { @@ -264,9 +263,13 @@ mod tests { let local: &TestCols = (*local).borrow(); // eval verifies that local.sqrt.result is indeed the square root of local.a. - local - .sqrt - .eval(builder, &local.a, AB::F::one(), AB::F::zero(), AB::F::one()); + local.sqrt.eval( + builder, + &local.a, + &AB::F::one(), + &AB::F::zero(), + &AB::F::one(), + ); } } diff --git a/core/src/runtime/mod.rs b/core/src/runtime/mod.rs index 012a95b9d..f453e205e 100644 --- a/core/src/runtime/mod.rs +++ b/core/src/runtime/mod.rs @@ -893,17 +893,17 @@ impl Runtime { } Opcode::MULH => { (rd, b, c) = self.alu_rr(instruction); - a = (((b as i32) as i64).wrapping_mul((c as i32) as i64) >> 32) as u32; + a = (i64::from(b as i32).wrapping_mul(i64::from(c as i32)) >> 32) as u32; self.alu_rw(instruction, rd, a, b, c, lookup_id); } Opcode::MULHU => { (rd, b, c) = self.alu_rr(instruction); - a = ((b as u64).wrapping_mul(c as u64) >> 32) as u32; + a = (u64::from(b).wrapping_mul(u64::from(c)) >> 32) as u32; self.alu_rw(instruction, rd, a, b, c, lookup_id); } Opcode::MULHSU => { (rd, b, c) = self.alu_rr(instruction); - a = (((b as i32) as i64).wrapping_mul(c as i64) >> 32) as u32; + a = (i64::from(b as i32).wrapping_mul(i64::from(c)) >> 32) as u32; self.alu_rw(instruction, rd, a, b, c, lookup_id); } Opcode::DIV => { diff --git a/core/src/runtime/record.rs b/core/src/runtime/record.rs index fb9a19c8e..8101e8436 100644 --- a/core/src/runtime/record.rs +++ b/core/src/runtime/record.rs @@ -904,38 +904,37 @@ impl MachineRecord for ExecutionRecord { let first = shards.first_mut().unwrap(); // SHA-256 extend events. - first.sha_extend_events = std::mem::take(&mut self.sha_extend_events); + first.sha_extend_events = take(&mut self.sha_extend_events); for (i, event) in first.sha_extend_events.iter().enumerate() { self.nonce_lookup.insert(event.lookup_id, (i * 48) as u32); } // SHA-256 compress events. - first.sha_compress_events = std::mem::take(&mut self.sha_compress_events); + first.sha_compress_events = take(&mut self.sha_compress_events); for (i, event) in first.sha_compress_events.iter().enumerate() { self.nonce_lookup.insert(event.lookup_id, (i * 80) as u32); } // Edwards curve add events. - first.ed_add_events = std::mem::take(&mut self.ed_add_events); + first.ed_add_events = take(&mut self.ed_add_events); for (i, event) in first.ed_add_events.iter().enumerate() { self.nonce_lookup.insert(event.lookup_id, i as u32); } // Edwards curve decompress events. - first.ed_decompress_events = std::mem::take(&mut self.ed_decompress_events); + first.ed_decompress_events = take(&mut self.ed_decompress_events); for (i, event) in first.ed_decompress_events.iter().enumerate() { self.nonce_lookup.insert(event.lookup_id, i as u32); } // K256 curve decompress events. - first.secp256k1_decompress_events = std::mem::take(&mut self.secp256k1_decompress_events); + first.secp256k1_decompress_events = take(&mut self.secp256k1_decompress_events); for (i, event) in first.secp256k1_decompress_events.iter().enumerate() { self.nonce_lookup.insert(event.lookup_id, i as u32); } // Bls12-381 decompress events. - first.bls12381_g1_decompress_events = - std::mem::take(&mut self.bls12381_g1_decompress_events); + first.bls12381_g1_decompress_events = take(&mut self.bls12381_g1_decompress_events); for (i, event) in first.bls12381_g1_decompress_events.iter().enumerate() { self.nonce_lookup.insert(event.lookup_id, i as u32); } diff --git a/core/src/runtime/syscall.rs b/core/src/runtime/syscall.rs index 5c61d0b6c..a77d53b5e 100644 --- a/core/src/runtime/syscall.rs +++ b/core/src/runtime/syscall.rs @@ -487,12 +487,6 @@ mod tests { SyscallCode::BLS12381_FP2_MUL => { assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_FP2_MUL) } - SyscallCode::BLS12381_G1_ADD => { - assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_G1_ADD) - } - SyscallCode::BLS12381_G1_DOUBLE => { - assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_G1_DOUBLE) - } SyscallCode::COMMIT => assert_eq!(code as u32, sphinx_zkvm::syscalls::COMMIT), SyscallCode::BLS12381_G1_DECOMPRESS => { assert_eq!(code as u32, sphinx_zkvm::syscalls::BLS12381_G1_DECOMPRESS) diff --git a/core/src/stark/air.rs b/core/src/stark/air.rs index 3f9bd5245..85fb40895 100644 --- a/core/src/stark/air.rs +++ b/core/src/stark/air.rs @@ -188,13 +188,13 @@ impl RiscvAir { chips.push(RiscvAir::Bls12381G2Add(bls12381_g2_add)); let bls12381_g2_double = Bls12381G2AffineDoubleChip::new(); chips.push(RiscvAir::Bls12381G2AffineDouble(bls12381_g2_double)); - let div_rem = DivRemChip::default(); + let div_rem = DivRemChip; chips.push(RiscvAir::DivRem(div_rem)); - let add = AddSubChip::default(); + let add = AddSubChip; chips.push(RiscvAir::Add(add)); let bitwise = BitwiseChip; chips.push(RiscvAir::Bitwise(bitwise)); - let mul = MulChip::default(); + let mul = MulChip; chips.push(RiscvAir::Mul(mul)); let shift_right = ShiftRightChip; chips.push(RiscvAir::ShiftRight(shift_right)); diff --git a/core/src/syscall/precompiles/bls12_381/g1_decompress.rs b/core/src/syscall/precompiles/bls12_381/g1_decompress.rs index 1aa027a40..731398572 100644 --- a/core/src/syscall/precompiles/bls12_381/g1_decompress.rs +++ b/core/src/syscall/precompiles/bls12_381/g1_decompress.rs @@ -444,9 +444,9 @@ where row.y.eval( builder, &row.x_3_plus_b.result, - row.shard, - row.channel, - row.is_real, + &row.shard, + &row.channel, + &row.is_real, ); row.two_y.eval( builder, diff --git a/core/src/syscall/precompiles/edwards/ed_add.rs b/core/src/syscall/precompiles/edwards/ed_add.rs index ab68cbe25..9e630806b 100644 --- a/core/src/syscall/precompiles/edwards/ed_add.rs +++ b/core/src/syscall/precompiles/edwards/ed_add.rs @@ -20,7 +20,6 @@ use sphinx_derive::AlignedBorrow; use crate::air::BaseAirBuilder; use crate::bytes::ByteLookupEvent; -use crate::memory::MemoryCols; use crate::memory::MemoryReadCols; use crate::memory::MemoryWriteCols; use crate::operations::field::field_den::FieldDenCols; diff --git a/core/src/syscall/precompiles/edwards/ed_decompress.rs b/core/src/syscall/precompiles/edwards/ed_decompress.rs index 632debe4b..07dabdaa2 100644 --- a/core/src/syscall/precompiles/edwards/ed_decompress.rs +++ b/core/src/syscall/precompiles/edwards/ed_decompress.rs @@ -237,9 +237,9 @@ impl EdDecompressCols { self.x.eval( builder, &self.u_div_v.result, - self.shard, - self.channel, - self.is_real, + &self.shard, + &self.channel, + &self.is_real, ); self.neg_x.eval( builder, diff --git a/core/src/syscall/precompiles/keccak256/columns.rs b/core/src/syscall/precompiles/keccak256/columns.rs index bb067e145..3cad2f5f1 100644 --- a/core/src/syscall/precompiles/keccak256/columns.rs +++ b/core/src/syscall/precompiles/keccak256/columns.rs @@ -16,11 +16,11 @@ pub(crate) struct KeccakMemCols { /// Keccak columns from p3_keccak_air. Note it is assumed in trace gen to be the first field. pub(crate) keccak: KeccakCols, - pub shard: T, - pub channel: T, - pub clk: T, - pub nonce: T, - pub state_addr: T, + pub(crate) shard: T, + pub(crate) channel: T, + pub(crate) clk: T, + pub(crate) nonce: T, + pub(crate) state_addr: T, /// Memory columns for the state. pub(crate) state_mem: [MemoryReadWriteCols; STATE_NUM_WORDS], diff --git a/core/src/syscall/precompiles/secp256k1/decompress.rs b/core/src/syscall/precompiles/secp256k1/decompress.rs index 8f4c99307..4e47d91aa 100644 --- a/core/src/syscall/precompiles/secp256k1/decompress.rs +++ b/core/src/syscall/precompiles/secp256k1/decompress.rs @@ -383,9 +383,9 @@ where row.y.eval( builder, &row.x_3_plus_b.result, - row.shard, - row.channel, - row.is_real, + &row.shard, + &row.channel, + &row.is_real, ); row.neg_y.eval( builder, diff --git a/core/src/syscall/precompiles/sha256/extend/flags.rs b/core/src/syscall/precompiles/sha256/extend/flags.rs index 4cf62e79c..51ceb1018 100644 --- a/core/src/syscall/precompiles/sha256/extend/flags.rs +++ b/core/src/syscall/precompiles/sha256/extend/flags.rs @@ -6,7 +6,6 @@ use p3_field::{AbstractField, Field, PrimeField32, TwoAdicField}; use p3_matrix::Matrix; use crate::air::BaseAirBuilder; -use crate::air::SphinxAirBuilder; use crate::operations::IsZeroOperation; use super::ShaExtendChip; diff --git a/recursion/core/src/poseidon2/external.rs b/recursion/core/src/poseidon2/external.rs index c84d44ad9..3db722f0d 100644 --- a/recursion/core/src/poseidon2/external.rs +++ b/recursion/core/src/poseidon2/external.rs @@ -4,7 +4,7 @@ use p3_air::AirBuilder; use p3_air::{Air, BaseAir}; use p3_field::{AbstractField, Field}; use p3_matrix::Matrix; -use sphinx_core::air::{BaseAirBuilder, ExtensionAirBuilder, SphinxAirBuilder}; +use sphinx_core::air::{BaseAirBuilder, ExtensionAirBuilder}; use sphinx_primitives::RC_16_30_U32; use std::marker::PhantomData;