From 82ffdf317ee52e8679d58361dfe39930600839d1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sun, 29 Dec 2024 12:44:30 -0800 Subject: [PATCH] [RISCV] Swap rs1 and rs2 names in TH_ADDSL patterns. NFC The names should match the operand order of the final instruction. I assume these patterns were somewhat copied from Zba where rs1 is shifted, but for th.addsl, rs2 is shifted. --- llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td index 9df889a50c3d..942ced8c6481 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td @@ -538,16 +538,16 @@ multiclass VPatTernaryVMAQA_VV_VX; -def : Pat<(XLenVT (riscv_shl_add GPR:$rs1, uimm2:$uimm2, GPR:$rs2)), - (TH_ADDSL GPR:$rs2, GPR:$rs1, uimm2:$uimm2)>; +def : Pat<(XLenVT (riscv_shl_add GPR:$rs2, uimm2:$uimm2, GPR:$rs1)), + (TH_ADDSL GPR:$rs1, GPR:$rs2, uimm2:$uimm2)>; // Reuse complex patterns from StdExtZba -def : Pat<(add_like_non_imm12 sh1add_op:$rs1, (XLenVT GPR:$rs2)), - (TH_ADDSL GPR:$rs2, sh1add_op:$rs1, 1)>; -def : Pat<(add_like_non_imm12 sh2add_op:$rs1, (XLenVT GPR:$rs2)), - (TH_ADDSL GPR:$rs2, sh2add_op:$rs1, 2)>; -def : Pat<(add_like_non_imm12 sh3add_op:$rs1, (XLenVT GPR:$rs2)), - (TH_ADDSL GPR:$rs2, sh3add_op:$rs1, 3)>; +def : Pat<(add_like_non_imm12 sh1add_op:$rs2, (XLenVT GPR:$rs1)), + (TH_ADDSL GPR:$rs1, sh1add_op:$rs2, 1)>; +def : Pat<(add_like_non_imm12 sh2add_op:$rs2, (XLenVT GPR:$rs1)), + (TH_ADDSL GPR:$rs1, sh2add_op:$rs2, 2)>; +def : Pat<(add_like_non_imm12 sh3add_op:$rs2, (XLenVT GPR:$rs1)), + (TH_ADDSL GPR:$rs1, sh3add_op:$rs2, 3)>; def : Pat<(add_like (XLenVT GPR:$r), CSImm12MulBy4:$i), (TH_ADDSL GPR:$r, (XLenVT (ADDI (XLenVT X0), CSImm12MulBy4:$i)), 2)>;