From 962b631c603c4f5e884e05a3fdb709fdb62adc4e Mon Sep 17 00:00:00 2001 From: Rafael Silva Date: Thu, 19 Dec 2024 12:14:06 +0000 Subject: [PATCH] riscv_debug: document the misa mxl field --- src/target/riscv_debug.c | 17 +++++++---------- src/target/riscv_debug.h | 13 +++++++++++++ 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/src/target/riscv_debug.c b/src/target/riscv_debug.c index d8516668cce..8ed85dcb7fb 100644 --- a/src/target/riscv_debug.c +++ b/src/target/riscv_debug.c @@ -124,8 +124,6 @@ #define RV_CSRW_A0 0x00051073U #define RV_EBREAK 0x00100073U -#define RV_ISA_EXTENSIONS_MASK 0x03ffffffU - #define RV_VENDOR_JEP106_CONT_MASK 0x7fffff80U #define RV_VENDOR_JEP106_CODE_MASK 0x7fU @@ -383,18 +381,17 @@ static void riscv_dm_init(riscv_dm_s *const dbg_module) static uint8_t riscv_isa_address_width(const uint32_t isa) { - switch (isa >> 30U) { - case 1: + switch ((isa & RV_ISA_MXL_MASK) >> RV_ISA_MXL_SHIFT) { + case RV_ISA_MXL_32: return 32U; - case 2: + case RV_ISA_MXL_64: return 64U; - case 3: + case RV_ISA_MXL_128: return 128U; default: - break; + DEBUG_INFO("Unknown address width, defaulting to 32\n"); + return 32U; } - DEBUG_INFO("Unknown address width, defaulting to 32\n"); - return 32U; } static void riscv_hart_read_ids(riscv_hart_s *const hart) @@ -423,7 +420,7 @@ static void riscv_hart_read_ids(riscv_hart_s *const hart) } static size_t riscv_snprint_isa_subset( - char *const string_buffer, const size_t buffer_size, const uint32_t access_width, const uint32_t extensions) + char *const string_buffer, const size_t buffer_size, const uint8_t access_width, const uint32_t extensions) { size_t offset = snprintf(string_buffer, buffer_size, "rv%" PRIu8, access_width); diff --git a/src/target/riscv_debug.h b/src/target/riscv_debug.h index 305c357216b..9db24a4993e 100644 --- a/src/target/riscv_debug.h +++ b/src/target/riscv_debug.h @@ -203,6 +203,18 @@ typedef struct riscv_hart { /* The FP base defines the starting register space address for the floating point registers */ #define RV_FP_BASE 0x1020U +/** + * The MXL (Machine XLEN) field encodes the native base integer ISA width + * + * The RISC-V Machine ISA register is MXLEN bits wide so the MXL offset is not fixed + * To work around this we convert the register to it's canonical 32-bit form internally + */ +#define RV_ISA_MXL_SHIFT 30U /* misa Machine XLEN field shift (for 32-bit misa) */ +#define RV_ISA_MXL_MASK (0x3U << RV_ISA_MXL_SHIFT) /* misa Machine XLEN field mask (for 32-bit misa) */ +#define RV_ISA_MXL_32 0x1U /* misa Machine XLEN field value for 32-bit ISA */ +#define RV_ISA_MXL_64 0x2U /* misa Machine XLEN field value for 64-bit ISA */ +#define RV_ISA_MXL_128 0x3U /* misa Machine XLEN field value for 128-bit ISA */ + /* * The Extensions field encodes the presence of standard extensions, with a single bit per alphabet letter * (bit 0 encodes presence of extension “A” through to bit 25 which encodes “Z”) @@ -211,6 +223,7 @@ typedef struct riscv_hart { * * The list order is the canonical representation order in the ISA subset string */ +#define RV_ISA_EXTENSIONS_MASK 0x03ffffffU /* misa extensions field mask */ /* Base ISA */ #define RV_ISA_EXT_INTEGER (1U << 8U) /* 'I': RV32I/64I/128I integer base ISA */