From e63facbdde98e007858b6152827700d18e3c2fad Mon Sep 17 00:00:00 2001 From: trdthg Date: Mon, 18 Dec 2023 21:05:43 +0800 Subject: [PATCH 1/2] zacas --- bfd/elfxx-riscv.c | 6 ++++++ binutils/.vscode/c_cpp_properties.json | 17 +++++++++++++++++ binutils/.vscode/settings.json | 5 +++++ gas/testsuite/gas/riscv/zacas-32.d | 11 +++++++++++ gas/testsuite/gas/riscv/zacas-32.s | 2 ++ gas/testsuite/gas/riscv/zacas-64.d | 11 +++++++++++ gas/testsuite/gas/riscv/zacas-64.s | 2 ++ include/opcode/riscv-opc.h | 7 +++++++ include/opcode/riscv.h | 1 + opcodes/riscv-opc.c | 8 ++++++++ 10 files changed, 70 insertions(+) create mode 100644 binutils/.vscode/c_cpp_properties.json create mode 100644 binutils/.vscode/settings.json create mode 100644 gas/testsuite/gas/riscv/zacas-32.d create mode 100644 gas/testsuite/gas/riscv/zacas-32.s create mode 100644 gas/testsuite/gas/riscv/zacas-64.d create mode 100644 gas/testsuite/gas/riscv/zacas-64.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index e121a59a373b..332a14dbddd4 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1118,6 +1118,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"v", "d", check_implicit_always}, {"v", "zve64d", check_implicit_always}, {"v", "zvl128b", check_implicit_always}, + {"zacas", "a", check_implicit_always}, {"zvfh", "zvfhmin", check_implicit_always}, {"zvfh", "zfhmin", check_implicit_always}, {"zvfhmin", "zve32f", check_implicit_always}, @@ -1275,6 +1276,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, @@ -2439,6 +2441,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, return riscv_subset_supports (rps, "a"); case INSN_CLASS_ZAWRS: return riscv_subset_supports (rps, "zawrs"); + case INSN_CLASS_ZACAS: + return riscv_subset_supports (rps, "zacas"); case INSN_CLASS_F: return riscv_subset_supports (rps, "f"); case INSN_CLASS_D: @@ -2661,6 +2665,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return "a"; case INSN_CLASS_ZAWRS: return "zawrs"; + case INSN_CLASS_ZACAS: + return "zacas"; case INSN_CLASS_F: return "f"; case INSN_CLASS_D: diff --git a/binutils/.vscode/c_cpp_properties.json b/binutils/.vscode/c_cpp_properties.json new file mode 100644 index 000000000000..3ac37f9f1286 --- /dev/null +++ b/binutils/.vscode/c_cpp_properties.json @@ -0,0 +1,17 @@ +{ + "configurations": [ + { + "name": "Linux", + "includePath": [ + "${workspaceFolder}/**", + "/home/trdthg/plct/riscv-gnu-toolchain/build-binutils-newlib/bfd" + ], + "defines": [], + "compilerPath": "/etc/profiles/per-user/trdthg/bin/clang", + "cStandard": "c17", + "cppStandard": "c++17", + "intelliSenseMode": "linux-clang-x64" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/binutils/.vscode/settings.json b/binutils/.vscode/settings.json new file mode 100644 index 000000000000..dd4074ab2d61 --- /dev/null +++ b/binutils/.vscode/settings.json @@ -0,0 +1,5 @@ +{ + "files.associations": { + "bfd.h": "c" + } +} \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/zacas-32.d b/gas/testsuite/gas/riscv/zacas-32.d new file mode 100644 index 000000000000..fe57dc8252b5 --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas-32.d @@ -0,0 +1,11 @@ +#as: -march=rv32g_zacas +#source: zacas-32.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+28c5a52f[ ]+amocas.w[ ]+a0,a1,a2 \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/zacas-32.s b/gas/testsuite/gas/riscv/zacas-32.s new file mode 100644 index 000000000000..99c3d112d875 --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas-32.s @@ -0,0 +1,2 @@ +target: + amocas.w a0,a1,a2 diff --git a/gas/testsuite/gas/riscv/zacas-64.d b/gas/testsuite/gas/riscv/zacas-64.d new file mode 100644 index 000000000000..55aee0478fee --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas-64.d @@ -0,0 +1,11 @@ +#as: -march=rv64i_zacas +#source: zacas-64.s +#objdump: -d + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+28c5b52f[ ]+amocas.d[ ]+a0,a1,a2 \ No newline at end of file diff --git a/gas/testsuite/gas/riscv/zacas-64.s b/gas/testsuite/gas/riscv/zacas-64.s new file mode 100644 index 000000000000..595b461d8d89 --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas-64.s @@ -0,0 +1,2 @@ +target: + amocas.d a0,a1,a2 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 25b7a96dab43..427b5d767d91 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2320,6 +2320,13 @@ #define MASK_WRS_NTO 0xffffffff #define MATCH_WRS_STO 0x01d00073 #define MASK_WRS_STO 0xffffffff +/* Zacas intructions */ +#define MATCH_CAS_W 0x2800202F +#define MASK_CAS_W 0xFE00707F +#define MATCH_CAS_D 0x2800302F +#define MASK_CAS_D 0xFE00707F +#define MATCH_CAS_Q 0x2800602F +#define MASK_CAS_Q 0xFE00707F /* Vendor-specific (CORE-V) Xcvmac instructions. */ #define MATCH_CV_MAC 0x9000302b #define MASK_CV_MAC 0xfe00707f diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 6687b4340744..c947cca96619 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -413,6 +413,7 @@ enum riscv_insn_class INSN_CLASS_ZIHINTPAUSE, INSN_CLASS_ZMMUL, INSN_CLASS_ZAWRS, + INSN_CLASS_ZACAS, INSN_CLASS_F_INX, INSN_CLASS_D_INX, INSN_CLASS_Q_INX, diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index bf388cdaa2f8..15318d79f8c7 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -988,6 +988,14 @@ const struct riscv_opcode riscv_opcodes[] = {"wrs.nto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_NTO, MASK_WRS_NTO, match_opcode, 0 }, {"wrs.sto", 0, INSN_CLASS_ZAWRS, "", MATCH_WRS_STO, MASK_WRS_STO, match_opcode, 0 }, +/* Zacas instructions */ +{"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W, MASK_CAS_W, match_opcode, 0 }, +{"amocas.d", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D, MASK_CAS_D, match_opcode, 0 }, +{"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q, MASK_CAS_Q, match_opcode, 0 }, +// {"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_AQRL, MASK_CAS_W|MASK_AQRL, match_opcode, 0 }, +// {"amocas.d.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_AQRL, MASK_CAS_D|MASK_AQRL, match_opcode, 0 }, +// {"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_AQRL, MASK_CAS_Q|MASK_AQRL, match_opcode, 0 }, + /* Zfa instructions. */ {"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 }, {"fli.d", 0, INSN_CLASS_D_AND_ZFA, "D,Wfv", MATCH_FLI_D, MASK_FLI_D, match_opcode, 0 }, From 3c2fe4749fcbd4abd112926952779c113761c9ad Mon Sep 17 00:00:00 2001 From: trdthg Date: Tue, 2 Jan 2024 15:57:57 +0800 Subject: [PATCH 2/2] add aqrl --- gas/testsuite/gas/riscv/zacas-128.d | 17 +++++++++++++++++ gas/testsuite/gas/riscv/zacas-128.s | 9 +++++++++ gas/testsuite/gas/riscv/zacas-32.d | 19 +++++++++++++++++-- gas/testsuite/gas/riscv/zacas-32.s | 17 ++++++++++++++++- gas/testsuite/gas/riscv/zacas-64.d | 17 ++++++++++++++++- gas/testsuite/gas/riscv/zacas-64.s | 17 ++++++++++++++++- opcodes/riscv-opc.c | 12 +++++++++--- 7 files changed, 100 insertions(+), 8 deletions(-) create mode 100644 gas/testsuite/gas/riscv/zacas-128.d create mode 100644 gas/testsuite/gas/riscv/zacas-128.s diff --git a/gas/testsuite/gas/riscv/zacas-128.d b/gas/testsuite/gas/riscv/zacas-128.d new file mode 100644 index 000000000000..69e2f57e7a94 --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas-128.d @@ -0,0 +1,17 @@ +#as: -march=rv64i_zacas +#source: zacas-128.s +#objdump: -d + +.*:[ ]+file format .* + +Disassembly of section .text: + +0+000 : +[ ]+[0-9a-f]+:[ ]+28b6652f[ ]+amocas.q[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6652f[ ]+amocas.q[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6652f[ ]+amocas.q.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6652f[ ]+amocas.q.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6652f[ ]+amocas.q.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6652f[ ]+amocas.q.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6652f[ ]+amocas.q.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6652f[ ]+amocas.q.aqrl[ ]+a0,a1,\(a2\) diff --git a/gas/testsuite/gas/riscv/zacas-128.s b/gas/testsuite/gas/riscv/zacas-128.s new file mode 100644 index 000000000000..734b064b419f --- /dev/null +++ b/gas/testsuite/gas/riscv/zacas-128.s @@ -0,0 +1,9 @@ +target: + amocas.q a0,a1,0(a2) + amocas.q a0,a1,(a2) + amocas.q.aq a0,a1,0(a2) + amocas.q.aq a0,a1,(a2) + amocas.q.rl a0,a1,0(a2) + amocas.q.rl a0,a1,(a2) + amocas.q.aqrl a0,a1,0(a2) + amocas.q.aqrl a0,a1,(a2) diff --git a/gas/testsuite/gas/riscv/zacas-32.d b/gas/testsuite/gas/riscv/zacas-32.d index fe57dc8252b5..fc938eabdbeb 100644 --- a/gas/testsuite/gas/riscv/zacas-32.d +++ b/gas/testsuite/gas/riscv/zacas-32.d @@ -1,4 +1,4 @@ -#as: -march=rv32g_zacas +#as: -march=rv32i_zacas #source: zacas-32.s #objdump: -d @@ -8,4 +8,19 @@ Disassembly of section .text: 0+000 : -[ ]+[0-9a-f]+:[ ]+28c5a52f[ ]+amocas.w[ ]+a0,a1,a2 \ No newline at end of file +[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\) diff --git a/gas/testsuite/gas/riscv/zacas-32.s b/gas/testsuite/gas/riscv/zacas-32.s index 99c3d112d875..65c918f63f0d 100644 --- a/gas/testsuite/gas/riscv/zacas-32.s +++ b/gas/testsuite/gas/riscv/zacas-32.s @@ -1,2 +1,17 @@ target: - amocas.w a0,a1,a2 + amocas.w a0,a1,0(a2) + amocas.w a0,a1,(a2) + amocas.w.aq a0,a1,0(a2) + amocas.w.aq a0,a1,(a2) + amocas.w.rl a0,a1,0(a2) + amocas.w.rl a0,a1,(a2) + amocas.w.aqrl a0,a1,0(a2) + amocas.w.aqrl a0,a1,(a2) + amocas.d a0,a1,0(a2) + amocas.d a0,a1,(a2) + amocas.d.aq a0,a1,0(a2) + amocas.d.aq a0,a1,(a2) + amocas.d.rl a0,a1,0(a2) + amocas.d.rl a0,a1,(a2) + amocas.d.aqrl a0,a1,0(a2) + amocas.d.aqrl a0,a1,(a2) diff --git a/gas/testsuite/gas/riscv/zacas-64.d b/gas/testsuite/gas/riscv/zacas-64.d index 55aee0478fee..b47dad4fa80e 100644 --- a/gas/testsuite/gas/riscv/zacas-64.d +++ b/gas/testsuite/gas/riscv/zacas-64.d @@ -8,4 +8,19 @@ Disassembly of section .text: 0+000 : -[ ]+[0-9a-f]+:[ ]+28c5b52f[ ]+amocas.d[ ]+a0,a1,a2 \ No newline at end of file +[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6252f[ ]+amocas.w[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6252f[ ]+amocas.w.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6252f[ ]+amocas.w.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6252f[ ]+amocas.w.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+28b6352f[ ]+amocas.d[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2cb6352f[ ]+amocas.d.aq[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2ab6352f[ ]+amocas.d.rl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\) +[ ]+[0-9a-f]+:[ ]+2eb6352f[ ]+amocas.d.aqrl[ ]+a0,a1,\(a2\) diff --git a/gas/testsuite/gas/riscv/zacas-64.s b/gas/testsuite/gas/riscv/zacas-64.s index 595b461d8d89..65c918f63f0d 100644 --- a/gas/testsuite/gas/riscv/zacas-64.s +++ b/gas/testsuite/gas/riscv/zacas-64.s @@ -1,2 +1,17 @@ target: - amocas.d a0,a1,a2 + amocas.w a0,a1,0(a2) + amocas.w a0,a1,(a2) + amocas.w.aq a0,a1,0(a2) + amocas.w.aq a0,a1,(a2) + amocas.w.rl a0,a1,0(a2) + amocas.w.rl a0,a1,(a2) + amocas.w.aqrl a0,a1,0(a2) + amocas.w.aqrl a0,a1,(a2) + amocas.d a0,a1,0(a2) + amocas.d a0,a1,(a2) + amocas.d.aq a0,a1,0(a2) + amocas.d.aq a0,a1,(a2) + amocas.d.rl a0,a1,0(a2) + amocas.d.rl a0,a1,(a2) + amocas.d.aqrl a0,a1,0(a2) + amocas.d.aqrl a0,a1,(a2) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 15318d79f8c7..f2c3af0f3e52 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -992,9 +992,15 @@ const struct riscv_opcode riscv_opcodes[] = {"amocas.w", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W, MASK_CAS_W, match_opcode, 0 }, {"amocas.d", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D, MASK_CAS_D, match_opcode, 0 }, {"amocas.q", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q, MASK_CAS_Q, match_opcode, 0 }, -// {"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_AQRL, MASK_CAS_W|MASK_AQRL, match_opcode, 0 }, -// {"amocas.d.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_AQRL, MASK_CAS_D|MASK_AQRL, match_opcode, 0 }, -// {"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_AQRL, MASK_CAS_Q|MASK_AQRL, match_opcode, 0 }, +{"amocas.w.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_AQ, MASK_CAS_W|MASK_AQ, match_opcode, 0 }, +{"amocas.d.aq", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_AQ, MASK_CAS_D|MASK_AQ, match_opcode, 0 }, +{"amocas.q.aq", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_AQ, MASK_CAS_Q|MASK_AQ, match_opcode, 0 }, +{"amocas.w.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_RL, MASK_CAS_W|MASK_RL, match_opcode, 0 }, +{"amocas.d.rl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_RL, MASK_CAS_D|MASK_RL, match_opcode, 0 }, +{"amocas.q.rl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_RL, MASK_CAS_Q|MASK_RL, match_opcode, 0 }, +{"amocas.w.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_W|MASK_AQRL, MASK_CAS_W|MASK_AQRL, match_opcode, 0 }, +{"amocas.d.aqrl", 0, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_D|MASK_AQRL, MASK_CAS_D|MASK_AQRL, match_opcode, 0 }, +{"amocas.q.aqrl", 64, INSN_CLASS_ZACAS, "d,t,0(s)", MATCH_CAS_Q|MASK_AQRL, MASK_CAS_Q|MASK_AQRL, match_opcode, 0 }, /* Zfa instructions. */ {"fli.s", 0, INSN_CLASS_ZFA, "D,Wfv", MATCH_FLI_S, MASK_FLI_S, match_opcode, 0 },