From 828c2ec23fe4d50737a96a3e679e9c06ffb88397 Mon Sep 17 00:00:00 2001
From: Alex Crichton <alex@alexcrichton.com>
Date: Fri, 10 Mar 2023 12:00:42 -0800
Subject: [PATCH] Special-case zero left-shifts as well

---
 cranelift/codegen/src/isa/aarch64/lower.isle           | 10 ++++++++--
 .../filetests/isa/aarch64/simd-arithmetic.clif         |  8 --------
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle
index 54a498187e75..cc72b9475cf1 100644
--- a/cranelift/codegen/src/isa/aarch64/lower.isle
+++ b/cranelift/codegen/src/isa/aarch64/lower.isle
@@ -1177,14 +1177,20 @@
           (csel (Cond.Ne) lo_lshift maybe_hi)))))
 
 ;; Shift for vector types.
-(rule -3 (lower (has_type (ty_vec128 ty) (ishl x y)))
+(rule -4 (lower (has_type (ty_vec128 ty) (ishl x y)))
       (let ((size VectorSize (vector_size ty))
             (masked_shift_amt Reg (and_imm $I32 y (shift_mask ty)))
             (shift Reg (vec_dup masked_shift_amt size)))
         (sshl x shift size)))
-(rule -2 (lower (has_type (ty_vec128 ty) (ishl x (iconst (u64_from_imm64 n)))))
+(rule -3 (lower (has_type (ty_vec128 ty) (ishl x (iconst (u64_from_imm64 n)))))
         (ushl_vec_imm x (shift_masked_imm ty n) (vector_size ty)))
 
+;; If left-shifting by zero don't generate a shift instruction and return the
+;; original value
+(rule -2 (lower (has_type (ty_vec128 ty) (ishl x (iconst (u64_from_imm64 n)))))
+        (if-let 0 (shift_masked_imm ty n))
+        x)
+
 (decl pure shift_masked_imm (Type u64) u8)
 (extern constructor shift_masked_imm shift_masked_imm)
 
diff --git a/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif b/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif
index 7bcac47556b3..3751ee7e0a2f 100644
--- a/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif
+++ b/cranelift/filetests/filetests/isa/aarch64/simd-arithmetic.clif
@@ -341,12 +341,10 @@ block0(v0: i8x16):
 
 ; VCode:
 ; block0:
-;   shl v0.16b, v0.16b, #0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   shl v0.16b, v0.16b, #0
 ;   ret
 
 function %ishl_i16x8_full_width(i16x8) -> i16x8 {
@@ -358,12 +356,10 @@ block0(v0: i16x8):
 
 ; VCode:
 ; block0:
-;   shl v0.8h, v0.8h, #0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   shl v0.8h, v0.8h, #0
 ;   ret
 
 function %ishl_i32x4_full_width(i32x4) -> i32x4 {
@@ -375,12 +371,10 @@ block0(v0: i32x4):
 
 ; VCode:
 ; block0:
-;   shl v0.4s, v0.4s, #0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   shl v0.4s, v0.4s, #0
 ;   ret
 
 function %ishl_i64x2_full_width(i64x2) -> i64x2 {
@@ -392,12 +386,10 @@ block0(v0: i64x2):
 
 ; VCode:
 ; block0:
-;   shl v0.2d, v0.2d, #0
 ;   ret
 ; 
 ; Disassembled:
 ; block0: ; offset 0x0
-;   shl v0.2d, v0.2d, #0
 ;   ret
 
 function %sshr_i8x16_full_width(i8x16) -> i8x16 {