$date
	Sat Mar  9 11:53:13 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module TOP $end
$scope module main $end
$var wire 1 ! _guard0 $end
$var wire 1 " _guard1 $end
$var wire 1 # _guard11 $end
$var wire 1 $ _guard12 $end
$var wire 1 % _guard14 $end
$var wire 1 & _guard15 $end
$var wire 1 ' _guard16 $end
$var wire 1 ( _guard17 $end
$var wire 1 ) _guard18 $end
$var wire 1 * _guard19 $end
$var wire 1 + _guard2 $end
$var wire 1 , _guard21 $end
$var wire 1 - _guard22 $end
$var wire 1 . _guard23 $end
$var wire 1 / _guard26 $end
$var wire 1 0 _guard27 $end
$var wire 1 1 _guard28 $end
$var wire 1 2 _guard30 $end
$var wire 1 3 _guard31 $end
$var wire 1 4 _guard33 $end
$var wire 1 5 _guard34 $end
$var wire 1 6 _guard37 $end
$var wire 1 7 _guard38 $end
$var wire 1 8 _guard39 $end
$var wire 1 9 _guard4 $end
$var wire 1 : _guard40 $end
$var wire 1 ; _guard41 $end
$var wire 1 < _guard43 $end
$var wire 1 = _guard44 $end
$var wire 1 > _guard45 $end
$var wire 1 ? _guard46 $end
$var wire 1 @ _guard47 $end
$var wire 1 A _guard49 $end
$var wire 1 B _guard5 $end
$var wire 1 C _guard50 $end
$var wire 1 D _guard51 $end
$var wire 1 E _guard52 $end
$var wire 1 F _guard55 $end
$var wire 1 G _guard56 $end
$var wire 1 H _guard57 $end
$var wire 1 I _guard58 $end
$var wire 1 J _guard6 $end
$var wire 1 K _guard60 $end
$var wire 1 L _guard61 $end
$var wire 1 M _guard62 $end
$var wire 1 N _guard64 $end
$var wire 1 O _guard65 $end
$var wire 1 P _guard67 $end
$var wire 1 Q _guard68 $end
$var wire 1 R _guard69 $end
$var wire 1 S _guard7 $end
$var wire 1 T _guard70 $end
$var wire 1 U _guard71 $end
$var wire 1 V _guard72 $end
$var wire 1 W _guard74 $end
$var wire 1 X _guard75 $end
$var wire 1 Y _guard76 $end
$var wire 1 Z _guard77 $end
$var wire 1 [ _guard78 $end
$var wire 1 \ _guard8 $end
$var wire 1 ] _guard80 $end
$var wire 1 ^ _guard81 $end
$var wire 1 _ _guard83 $end
$var wire 1 ` _guard84 $end
$var wire 1 a _guard86 $end
$var wire 1 b _guard87 $end
$var wire 1 c _guard89 $end
$var wire 1 d _guard9 $end
$var wire 1 e _guard90 $end
$var wire 1 f _guard92 $end
$var wire 1 g _guard93 $end
$var wire 1 h _guard94 $end
$var wire 32 i add_left [31:0] $end
$var wire 32 j add_right [31:0] $end
$var wire 1 k clk $end
$var wire 1 l done $end
$var wire 1 m early_reset_static_seq_done_in $end
$var wire 1 n early_reset_static_seq_go_in $end
$var wire 1 o fsm0_clk $end
$var wire 1 p fsm0_reset $end
$var wire 1 q fsm0_write_en $end
$var wire 1 r fsm_clk $end
$var wire 1 s fsm_reset $end
$var wire 1 t fsm_write_en $end
$var wire 1 u go $end
$var wire 1 v mem_write_en $end
$var wire 1 w reset $end
$var wire 1 x signal_reg_clk $end
$var wire 1 y signal_reg_reset $end
$var wire 1 z signal_reg_write_en $end
$var wire 1 { tdcc_done_in $end
$var wire 1 | tdcc_go_in $end
$var wire 1 } ud_out $end
$var wire 1 ~ val_clk $end
$var wire 1 !" val_reset $end
$var wire 1 "" val_write_en $end
$var wire 1 #" wrapper_early_reset_static_seq_done_in $end
$var wire 1 $" wrapper_early_reset_static_seq_go_in $end
$var wire 1 %" write_done_in $end
$var wire 1 &" write_go_in $end
$var wire 1 '" write_go_out $end
$var wire 1 (" write_done_out $end
$var wire 1 )" wrapper_early_reset_static_seq_go_out $end
$var wire 1 *" wrapper_early_reset_static_seq_done_out $end
$var wire 32 +" val_out [31:0] $end
$var wire 32 ," val_in [31:0] $end
$var wire 1 -" val_done $end
$var wire 1 ." tdcc_go_out $end
$var wire 1 /" tdcc_done_out $end
$var wire 1 0" signal_reg_out $end
$var wire 1 1" signal_reg_in $end
$var wire 1 2" signal_reg_done $end
$var wire 32 3" mem_write_data [31:0] $end
$var wire 32 4" mem_read_data [31:0] $end
$var wire 1 5" mem_done $end
$var wire 1 6" mem_addr0 $end
$var wire 2 7" fsm_out [1:0] $end
$var wire 2 8" fsm_in [1:0] $end
$var wire 1 9" fsm_done $end
$var wire 2 :" fsm0_out [1:0] $end
$var wire 2 ;" fsm0_in [1:0] $end
$var wire 1 <" fsm0_done $end
$var wire 1 =" early_reset_static_seq_go_out $end
$var wire 1 >" early_reset_static_seq_done_out $end
$var wire 2 ?" adder_right [1:0] $end
$var wire 2 @" adder_out [1:0] $end
$var wire 2 A" adder_left [1:0] $end
$var wire 32 B" add_out [31:0] $end
$var wire 1 C" _guard91 $end
$var wire 1 D" _guard88 $end
$var wire 1 E" _guard85 $end
$var wire 1 F" _guard82 $end
$var wire 1 G" _guard79 $end
$var wire 1 H" _guard73 $end
$var wire 1 I" _guard66 $end
$var wire 1 J" _guard63 $end
$var wire 1 K" _guard59 $end
$var wire 1 L" _guard54 $end
$var wire 1 M" _guard53 $end
$var wire 1 N" _guard48 $end
$var wire 1 O" _guard42 $end
$var wire 1 P" _guard36 $end
$var wire 1 Q" _guard35 $end
$var wire 1 R" _guard32 $end
$var wire 1 S" _guard3 $end
$var wire 1 T" _guard29 $end
$var wire 1 U" _guard25 $end
$var wire 1 V" _guard24 $end
$var wire 1 W" _guard20 $end
$var wire 1 X" _guard13 $end
$var wire 1 Y" _guard10 $end
$scope module add $end
$var wire 32 Z" left [31:0] $end
$var wire 32 [" right [31:0] $end
$var wire 32 \" out [31:0] $end
$var parameter 32 ]" WIDTH $end
$upscope $end
$scope module adder $end
$var wire 2 ^" left [1:0] $end
$var wire 2 _" right [1:0] $end
$var wire 2 `" out [1:0] $end
$var parameter 32 a" WIDTH $end
$upscope $end
$scope module early_reset_static_seq_done $end
$var wire 1 m in $end
$var wire 1 >" out $end
$var parameter 32 b" WIDTH $end
$upscope $end
$scope module early_reset_static_seq_go $end
$var wire 1 n in $end
$var wire 1 =" out $end
$var parameter 32 c" WIDTH $end
$upscope $end
$scope module fsm $end
$var wire 1 r clk $end
$var wire 2 d" in [1:0] $end
$var wire 1 s reset $end
$var wire 1 t write_en $end
$var parameter 32 e" WIDTH $end
$var reg 1 9" done $end
$var reg 2 f" out [1:0] $end
$upscope $end
$scope module fsm0 $end
$var wire 1 o clk $end
$var wire 2 g" in [1:0] $end
$var wire 1 p reset $end
$var wire 1 q write_en $end
$var parameter 32 h" WIDTH $end
$var reg 1 <" done $end
$var reg 2 i" out [1:0] $end
$upscope $end
$scope module signal_reg $end
$var wire 1 x clk $end
$var wire 1 1" in $end
$var wire 1 y reset $end
$var wire 1 z write_en $end
$var parameter 32 j" WIDTH $end
$var reg 1 2" done $end
$var reg 1 0" out $end
$upscope $end
$scope module tdcc_done $end
$var wire 1 { in $end
$var wire 1 /" out $end
$var parameter 32 k" WIDTH $end
$upscope $end
$scope module tdcc_go $end
$var wire 1 | in $end
$var wire 1 ." out $end
$var parameter 32 l" WIDTH $end
$upscope $end
$scope module ud $end
$var wire 1 } out $end
$var parameter 32 m" WIDTH $end
$upscope $end
$scope module val $end
$var wire 1 ~ clk $end
$var wire 32 n" in [31:0] $end
$var wire 1 !" reset $end
$var wire 1 "" write_en $end
$var parameter 32 o" WIDTH $end
$var reg 1 -" done $end
$var reg 32 p" out [31:0] $end
$upscope $end
$scope module wrapper_early_reset_static_seq_done $end
$var wire 1 #" in $end
$var wire 1 *" out $end
$var parameter 32 q" WIDTH $end
$upscope $end
$scope module wrapper_early_reset_static_seq_go $end
$var wire 1 $" in $end
$var wire 1 )" out $end
$var parameter 32 r" WIDTH $end
$upscope $end
$scope module write_done $end
$var wire 1 %" in $end
$var wire 1 (" out $end
$var parameter 32 s" WIDTH $end
$upscope $end
$scope module write_go $end
$var wire 1 &" in $end
$var wire 1 '" out $end
$var parameter 32 t" WIDTH $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b1 t"
b1 s"
b1 r"
b1 q"
b100000 o"
b1 m"
b1 l"
b1 k"
b1 j"
b10 h"
b10 e"
b1 c"
b1 b"
b10 a"
b100000 ]"
$end
#0
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$end
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