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Change generated kernel.xml axi manager port width to 512 #1074

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merged 5 commits into from
Jul 7, 2022
Merged

Change generated kernel.xml axi manager port width to 512 #1074

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4bb2b11
Changed axi manager port width to 512
nathanielnrn Jul 5, 2022
a336bdf
Merge branch 'master' into kernel-axi-manager-width-fix
nathanielnrn Jul 6, 2022
03350e2
Merge branch 'master' into kernel-axi-manager-width-fix
nathanielnrn Jul 7, 2022
153341f
Added comments regarding kernel width
nathanielnrn Jul 7, 2022
883dcf4
Merge branch 'master' into kernel-axi-manager-width-fix
nathanielnrn Jul 7, 2022
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5 changes: 4 additions & 1 deletion src/backend/xilinx/xml.rs
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Expand Up @@ -150,7 +150,10 @@ impl Backend for XilinxXmlBackend {
name: axi_name,
mode: "master",
range: "0xFFFFFFFFFFFFFFFF",
data_width: 64,
// Width should match the bus data width of memory modules
// described in hardware, for example see
// https://github.com/cucapra/calyx/blob/c2b12a0fe6b1ee3aaaae0c66e7c4619ee6c82614/src/backend/xilinx/toplevel.rs#L58
data_width: 512,
port_type: "addressable",
base: "0x0",
});
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