[xilinx] Logic for parsing AXI memory ports from kernel #958
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Starting with Alex's XML parsing stuff, we now actually pass this stuff to our `gen_xo.tcl` script. This also uses the `mode` attribute on the `port` XML elements to distinguish which ports are relevant.
It's a test with 3 external memories, so it tests our new ability to support more than 1 such interface.
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This has gone green, and I think it's ready to ship! ⛵ ✨ I started with @yn224's XML parsing snippet, made it a little more specific, did some refactoring, and hooked it into the command-line interpolation to correctly invoke the TCL script. I added a second test to the new Xilinx-specific suite: this time the This would check the first currently-unchecked checkbox in #876. |
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Ah, yes. |
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Great, thanks for wrapping this up! |
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This PR suggests the method in which AXI ports can be parsed out of generated
kernel.xmlfile of the Xilinx tool (relates to PR #888).