Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Initial PR for Wasm.Simd. Includes build/extract and binary arithmetic ops. #2736

Merged
merged 12 commits into from
Apr 5, 2017
Merged

Initial PR for Wasm.Simd. Includes build/extract and binary arithmetic ops. #2736

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
12 commits
Select commit Hold shift + click to select a range
2ea6c86
Adding WASM-SIMD feature flag
arunetm Feb 6, 2017
79c541b
arithmetics tests
Krovatkin Mar 10, 2017
e87d84f
fixes after Mike's changes to writers to handle unreachable code veri…
Krovatkin Mar 23, 2017
6bbabaf
CI failures
Krovatkin Mar 23, 2017
6b89b85
CI fixes 2
Krovatkin Mar 23, 2017
1e30eec
CI 3 fixing win7 failures
Krovatkin Mar 24, 2017
65f235c
llvm fixes 2
Krovatkin Mar 29, 2017
952760c
constantsize the magic number representing the max num of lanes
Krovatkin Mar 30, 2017
5564041
initial switch to m128
Krovatkin Mar 30, 2017
501145b
addressing mike's feedback
Krovatkin Mar 30, 2017
347d683
mike's feedback p2
Krovatkin Apr 3, 2017
e373f82
linking errors on osx/static
Krovatkin Apr 4, 2017
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions lib/Backend/LowerMDShared.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -374,6 +374,7 @@ class LowererMD
BYTE Simd128GetTypedArrBytesPerElem(ValueType arrType);
IR::Instr* Simd128CanonicalizeToBools(IR::Instr* instr, const Js::OpCode& cmpOpcode, IR::Opnd& dstOpnd);
IR::Opnd* EnregisterIntConst(IR::Instr* instr, IR::Opnd *constOpnd, IRType type = TyInt32);
IR::Opnd* EnregisterBoolConst(IR::Instr* instr, IR::Opnd *opnd, IRType type);
SList<IR::Opnd*> * Simd128GetExtendedArgs(IR::Instr *instr);
void GenerateCheckedSimdLoad(IR::Instr * instr);
void GenerateSimdStore(IR::Instr * instr);
Expand Down
41 changes: 37 additions & 4 deletions lib/Backend/LowerMDSharedSimd128.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -435,7 +435,10 @@ IR::Instr* LowererMD::Simd128LowerConstructor_8(IR::Instr *instr)
{
srcs[i] = args->Pop();
// src's might have been constant prop'ed. Enregister them if so.
srcs[i] = EnregisterIntConst(instr, srcs[i], TyInt16);
srcs[i] = (instr->m_opcode == Js::OpCode::Simd128_IntsToB8) ?
EnregisterBoolConst(instr, srcs[i], TyInt16) :
EnregisterIntConst(instr, srcs[i], TyInt16);

Assert(srcs[i]->GetType() == TyInt16 && srcs[i]->IsRegOpnd());
// PINSRW dst, srcs[i], i
instr->InsertBefore(IR::Instr::New(Js::OpCode::PINSRW, dst, srcs[i], IR::IntConstOpnd::New(i, TyInt8, m_func, true), m_func));
Expand Down Expand Up @@ -474,7 +477,9 @@ IR::Instr* LowererMD::Simd128LowerConstructor_16(IR::Instr *instr)
{
srcs[i] = args->Pop();
// src's might have been constant prop'ed. Enregister them if so.
srcs[i] = EnregisterIntConst(instr, srcs[i], TyInt8);
srcs[i] = (instr->m_opcode == Js::OpCode::Simd128_IntsToB16) ?
EnregisterBoolConst(instr, srcs[i], TyInt8) :
EnregisterIntConst(instr, srcs[i], TyInt8);
Assert(srcs[i]->GetType() == TyInt8 && srcs[i]->IsRegOpnd());

address = tempSIMD + i;
Expand Down Expand Up @@ -737,7 +742,7 @@ IR::Instr* LowererMD::Simd128LowerLdLane(IR::Instr *instr)

// dst has the 4-byte lane
if (instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I8 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_U8 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B8 ||
instr->m_opcode == Js::OpCode::Simd128_ExtractLane_U16|| instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I16|| instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B16)
instr->m_opcode == Js::OpCode::Simd128_ExtractLane_U16 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_I16 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B16)
{
// extract the 1/2 bytes sublane
IR::Instr *newInstr = nullptr;
Expand Down Expand Up @@ -777,7 +782,7 @@ IR::Instr* LowererMD::Simd128LowerLdLane(IR::Instr *instr)
if (instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B4 || instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B8 ||
instr->m_opcode == Js::OpCode::Simd128_ExtractLane_B16)
{
IR::Instr* pInstr = nullptr;
IR::Instr* pInstr = nullptr;
IR::RegOpnd* tmp = IR::RegOpnd::New(TyInt8, m_func);

// cmp dst, -1
Expand Down Expand Up @@ -3017,6 +3022,34 @@ SList<IR::Opnd*> * LowererMD::Simd128GetExtendedArgs(IR::Instr *instr)
return args;
}



IR::Opnd*
LowererMD::EnregisterBoolConst(IR::Instr* instr, IR::Opnd *opnd, IRType type)
{

if (opnd->IsIntConstOpnd() || opnd->IsInt64ConstOpnd())
{
bool isSet = opnd->GetImmediateValue(instr->m_func) != 0;
IR::RegOpnd *tempReg = IR::RegOpnd::New(type, m_func);
instr->InsertBefore(IR::Instr::New(Js::OpCode::MOV, tempReg, IR::IntConstOpnd::New(isSet ? -1 : 0, type, m_func, true), m_func));
return tempReg;
}

IRType origType = opnd->GetType();
IR::RegOpnd *tempReg = IR::RegOpnd::New(origType, m_func);
IR::Instr* cmovInstr = IR::Instr::New(Js::OpCode::MOV, tempReg, IR::IntConstOpnd::New(0, origType, m_func, true), m_func);
instr->InsertBefore(cmovInstr);
Legalize(cmovInstr);
cmovInstr = IR::Instr::New(Js::OpCode::SUB, tempReg, tempReg, opnd->UseWithNewType(origType, m_func), m_func);
instr->InsertBefore(cmovInstr);
Legalize(cmovInstr);
cmovInstr = IR::Instr::New(Js::OpCode::CMOVS, tempReg, tempReg, IR::IntConstOpnd::New(-1, origType, m_func, true), m_func);
instr->InsertBefore(cmovInstr);
Legalize(cmovInstr);
return tempReg->UseWithNewType(type, m_func);
}

IR::Opnd*
LowererMD::EnregisterIntConst(IR::Instr* instr, IR::Opnd *constOpnd, IRType type /* = TyInt32*/)
{
Expand Down
2 changes: 2 additions & 0 deletions lib/Common/ConfigFlagsList.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -389,6 +389,7 @@ PHASE(All)
#endif
#define DEFAULT_CONFIG_WasmCheckVersion (true)
#define DEFAULT_CONFIG_WasmFold (true)
#define DEFAULT_CONFIG_WasmSimd (false)
#define DEFAULT_CONFIG_BgJitDelayFgBuffer (0)
#define DEFAULT_CONFIG_BgJitPendingFuncCap (31)
#define DEFAULT_CONFIG_CurrentSourceInfo (true)
Expand Down Expand Up @@ -859,6 +860,7 @@ FLAGNR(Boolean, AsmJsEdge , "Enable asm.js features which may have b
FLAGNR(Boolean, WasmI64 , "Enable Int64 testing for WebAssembly. ArgIns can be [number,string,{low:number,high:number}]. Return values will be {low:number,high:number}", DEFAULT_CONFIG_WasmI64)
FLAGNR(Boolean, WasmFastArray , "Enable fast array implementation for WebAssembly", DEFAULT_CONFIG_WasmFastArray)
FLAGNR(Boolean, WasmCheckVersion , "Check the binary version for WebAssembly", DEFAULT_CONFIG_WasmCheckVersion)
FLAGNR(Boolean, WasmSimd, "Enable SIMD in WebAssembly", DEFAULT_CONFIG_WasmSimd)

#ifndef COMPILE_DISABLE_Simdjs
#define COMPILE_DISABLE_Simdjs 0
Expand Down
8 changes: 4 additions & 4 deletions lib/Runtime/ByteCode/AsmJsByteCodeWriter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,20 +46,20 @@ namespace Js
IMP_IWASM void MarkAsmJsLabel(ByteCodeLabel labelID);
IMP_IWASM uint EnterLoop(ByteCodeLabel loopEntrance);
IMP_IWASM void ExitLoop(uint loopId);
IMP_IWASM void AsmReg5(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4);
IMP_IWASM void AsmReg9(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8);
IMP_IWASM void AsmReg17(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8,
RegSlot R9, RegSlot R10, RegSlot R11, RegSlot R12, RegSlot R13, RegSlot R14, RegSlot R15, RegSlot R16);

#ifdef WASM_BYTECODE_WRITER
// We don't want to expose api not in IWasmByteCodeWriter, but it's easier to compile them anyway
private:
#endif
void AsmReg4(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3);
void AsmReg5(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4);
void AsmReg6(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5);
void AsmReg7(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6);
void AsmReg9(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8);
void AsmReg10(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8, RegSlot R9);
void AsmReg11(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8, RegSlot R9, RegSlot R10);
void AsmReg17(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8,
RegSlot R9, RegSlot R10, RegSlot R11, RegSlot R12, RegSlot R13, RegSlot R14, RegSlot R15, RegSlot R16);
void AsmReg18(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8,
RegSlot R9, RegSlot R10, RegSlot R11, RegSlot R12, RegSlot R13, RegSlot R14, RegSlot R15, RegSlot R16, RegSlot R17);
void AsmReg19(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8,
Expand Down
5 changes: 5 additions & 0 deletions lib/Runtime/ByteCode/IWasmByteCodeWriter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,11 @@ namespace Js
virtual void AsmReg1(OpCodeAsmJs op, RegSlot R0) = 0;
virtual void AsmReg2(OpCodeAsmJs op, RegSlot R0, RegSlot R1) = 0;
virtual void AsmReg3(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2) = 0;
virtual void AsmReg5(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4) = 0;
virtual void AsmReg9(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8) = 0;
virtual void AsmReg17(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8,
RegSlot R9, RegSlot R10, RegSlot R11, RegSlot R12, RegSlot R13, RegSlot R14, RegSlot R15, RegSlot R16) = 0;

virtual void AsmSlot(OpCodeAsmJs op, RegSlot value, RegSlot instance, int32 slotId) = 0;
virtual void AsmBr(ByteCodeLabel labelID, OpCodeAsmJs op = OpCodeAsmJs::AsmBr) = 0;
virtual void AsmBrReg1(OpCodeAsmJs op, ByteCodeLabel labelID, RegSlot R1) = 0;
Expand Down
11 changes: 9 additions & 2 deletions lib/Runtime/ByteCode/OpCodesSimd.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -129,6 +129,14 @@ MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_LdSlot_F4 , ElementSlo
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_StSlot_F4 , ElementSlot , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_Return_F4 , Float32x4_2 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_I_ArgOut_F4 , Reg1Float32x4_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_F4 , Reg1Float32x4_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_I4 , Reg1Int32x4_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_B4 , Reg1Bool32x4_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_I8 , Reg1Int16x8_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_B8 , Reg1Bool16x8_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_I16 , Reg1Int8x16_1 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_ArgOut_B16 , Reg1Bool8x16_1 , None , None )

MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_I_Conv_VTF4 , Float32x4_2 , None , None )

// Float64x2
Expand Down Expand Up @@ -498,8 +506,7 @@ MACRO_SIMD_EXTEND_WMS ( Simd128_AllTrue_B16 , Int1Bool8x16_1
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_Ld_B16 , Bool8x16_2 , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_LdSlot_B16 , ElementSlot , None , None )
MACRO_SIMD_ASMJS_ONLY_EXTEND_WMS( Simd128_StSlot_B16 , ElementSlot , None , None )

MACRO_SIMD_EXTEND ( Simd128_End_Extend , Empty , None , None , 0) // Just a marker to indicate SIMD opcodes region
MACRO_SIMD_EXTEND ( Simd128_End_Extend , Empty , None , None , 0) // Just a marker to indicate SIMD opcodes region
#undef T_F4
#undef T_I4
#undef T_INT
Expand Down
12 changes: 7 additions & 5 deletions lib/Runtime/Language/InterpreterHandlerAsmJs.inl
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -38,8 +38,8 @@ EXDEF2 (NOPASMJS , InvalidOpCode, Empty
DEF2_WMS( R1toF1Mem , Conv_VTF , JavascriptConversion::ToNumber ) // convert var to float
DEF2_WMS( I1toI1Mem , I_Conv_VTI , (int) )
DEF2_WMS( R1toI1Mem , Conv_VTI , JavascriptMath::ToInt32 ) // convert var to int
DEF3_WMS( CUSTOM_ASMJS , ArgOut_Long , OP_InvalidWasmTypeConversion<true> , Reg1Long1 ) // convert int64 to Var
DEF3_WMS( CUSTOM_ASMJS , Conv_VTL , OP_InvalidWasmTypeConversion<false> , Long1Reg1 ) // convert var to int64
DEF3_WMS( CUSTOM_ASMJS , ArgOut_Long , (OP_InvalidWasmTypeConversion<Wasm::WasmTypes::I64,true>) , Reg1Long1 ) // convert int64 to Var
DEF3_WMS( CUSTOM_ASMJS , Conv_VTL , (OP_InvalidWasmTypeConversion<Wasm::WasmTypes::I64,false>) , Long1Reg1 ) // convert var to int64

DEF3_WMS( CUSTOM_ASMJS , LdArr_Func , OP_LdArrFunc , ElementSlot )
DEF3_WMS( CUSTOM_ASMJS , LdArr_WasmFunc,OP_LdArrWasmFunc , ElementSlot )
Expand Down Expand Up @@ -366,6 +366,8 @@ EXDEF2_WMS( SIMD_B8_1U8_2toU8_1 , Simd128_Select_U8 , Js::SIMDInt32x4Opera
EXDEF2_WMS( SIMD_B16_1U16_2toU16_1 , Simd128_Select_U16 , Js::SIMDInt32x4Operation::OpSelect )

// args out, copy value to outParams
EXDEF3_WMS ( CUSTOM_ASMJS , Simd128_ArgOut_F4 , (OP_InvalidWasmTypeConversion<Wasm::WasmTypes::M128,true>) , Reg1Float32x4_1)

EXDEF2_WMS ( SIMD_F4_1toR1Mem , Simd128_I_ArgOut_F4 , OP_I_SetOutAsmSimd )
DEF2_WMS ( SIMD_I4_1toR1Mem , Simd128_I_ArgOut_I4 , OP_I_SetOutAsmSimd )

Expand Down Expand Up @@ -439,9 +441,9 @@ EXDEF2_WMS ( SIMD_I8_1I1toI1 , Simd128_ExtractLane_I8 , SIMDUtils::SIMD128I
EXDEF2_WMS ( SIMD_U4_1I1toI1 , Simd128_ExtractLane_U4 , SIMDUtils::SIMD128InnerExtractLaneI4 )
EXDEF2_WMS ( SIMD_U8_1I1toI1 , Simd128_ExtractLane_U8 , SIMDUtils::SIMD128InnerExtractLaneI8 )
EXDEF2_WMS ( SIMD_U16_1I1toI1 , Simd128_ExtractLane_U16 , SIMDUtils::SIMD128InnerExtractLaneI16 )
EXDEF2_WMS ( SIMD_B4_1I1toI1 , Simd128_ExtractLane_B4 , SIMDUtils::SIMD128InnerExtractLaneI4 )
EXDEF2_WMS ( SIMD_B8_1I1toI1 , Simd128_ExtractLane_B8 , SIMDUtils::SIMD128InnerExtractLaneI8 )
EXDEF2_WMS ( SIMD_B16_1I1toI1 , Simd128_ExtractLane_B16 , SIMDUtils::SIMD128InnerExtractLaneI16 )
EXDEF2_WMS ( SIMD_B4_1I1toI1 , Simd128_ExtractLane_B4 , SIMDUtils::SIMD128InnerExtractLaneB4 )
EXDEF2_WMS ( SIMD_B8_1I1toI1 , Simd128_ExtractLane_B8 , SIMDUtils::SIMD128InnerExtractLaneB8 )
EXDEF2_WMS ( SIMD_B16_1I1toI1 , Simd128_ExtractLane_B16 , SIMDUtils::SIMD128InnerExtractLaneB16 )

EXDEF2_WMS ( SIMD_I4_1I2toI4_1 , Simd128_ReplaceLane_I4 , SIMDUtils::SIMD128InnerReplaceLaneI4 )
EXDEF2_WMS ( SIMD_F4_1I1F1toF4_1 , Simd128_ReplaceLane_F4 , SIMDUtils::SIMD128InnerReplaceLaneF4 )
Expand Down
15 changes: 10 additions & 5 deletions lib/Runtime/Language/InterpreterStackFrame.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@
#include "Language/InterpreterStackFrame.h"
#include "Library/JavascriptGeneratorFunction.h"
#include "Library/ForInObjectEnumerator.h"

#include "../../WasmReader/WasmParseTree.h"
///----------------------------------------------------------------------------
///
/// macros PROCESS_INtoOUT
Expand Down Expand Up @@ -2322,13 +2322,18 @@ namespace Js
*(AsmJsSIMDValue*)(&(m_outParams[outRegisterID])) = val;
}

template<bool toJs>
template<int type, bool toJs>
void InterpreterStackFrame::OP_InvalidWasmTypeConversion(...)
{
// Right now the only invalid wasm type conversion is with int64
const char16* fromType = toJs ? _u("int64") : _u("Javascript Variable");
const char16* toType = toJs ? _u("Javascript Variable") : _u("int64");
#ifdef ENABLE_WASM
CompileAssert(type < Wasm::WasmTypes::Limit);
const char16* fromType = toJs ? Wasm::WasmTypes::GetStrId(static_cast<Wasm::WasmTypes::WasmType>(type)) : _u("Javascript Variable");
const char16* toType = toJs ? _u("Javascript Variable") : Wasm::WasmTypes::GetStrId(static_cast<Wasm::WasmTypes::WasmType>(type));
JavascriptError::ThrowTypeErrorVar(scriptContext, WASMERR_InvalidTypeConversion, fromType, toType);
#else
Assert(UNREACHED); //shouldn't get there
JavascriptError::ThrowTypeErrorVar(scriptContext, WASMERR_InvalidTypeConversion, _u("unknown"), _u("unknown")); //throw for a release build
#endif
}

// This will be called in the beginning of the try_finally.
Expand Down
2 changes: 1 addition & 1 deletion lib/Runtime/Language/InterpreterStackFrame.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -177,7 +177,7 @@ namespace Js
void OP_I_SetOutAsmFlt(RegSlot outRegisterID, float val);
void OP_I_SetOutAsmLong(RegSlot outRegisterID, int64 val);
void OP_I_SetOutAsmSimd(RegSlot outRegisterID, AsmJsSIMDValue val);
template<bool toJs>
template<int type, bool toJs> //type is int to avoid including Wasm headers
void OP_InvalidWasmTypeConversion(...);

void SetOut(ArgSlot outRegisterID, Var bValue);
Expand Down
18 changes: 18 additions & 0 deletions lib/Runtime/Language/SimdUtils.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -243,6 +243,24 @@ namespace Js {
return simdVal;
};

static inline int32 SIMD128InnerExtractLaneB4(const SIMDValue src1, const uint32 lane)
{
int val = SIMD128InnerExtractLaneI4(src1, lane);
return val ? 1 : 0;
};

static inline int16 SIMD128InnerExtractLaneB8(const SIMDValue src1, const uint32 lane)
{
int16 val = SIMD128InnerExtractLaneI8(src1, lane);
return val ? 1 : 0;
};

static inline int8 SIMD128InnerExtractLaneB16(const SIMDValue src1, const uint32 lane)
{
int8 val = SIMD128InnerExtractLaneI16(src1, lane);
return val ? 1 : 0;
};

static inline float SIMD128InnerExtractLaneF4(const SIMDValue src1, const uint32 lane) { return src1.f32[lane]; };
static inline int32 SIMD128InnerExtractLaneI4(const SIMDValue src1, const uint32 lane) { return src1.i32[lane]; };
static inline int16 SIMD128InnerExtractLaneI8(const SIMDValue src1, const uint32 lane) { return src1.i16[lane]; };
Expand Down
1 change: 1 addition & 0 deletions lib/WasmReader/Chakra.WasmReader.vcxproj
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@
<ClInclude Include="WasmSignature.h" />
<ClInclude Include="WasmBinaryReader.h" />
<ClInclude Include="WasmBinaryOpcodes.h" />
<ClInclude Include="WasmBinaryOpcodesSimd.h" />
</ItemGroup>
<ItemGroup>
<ProjectReference Include="..\JITIDL\Chakra.JITIDL.vcxproj">
Expand Down
1 change: 1 addition & 0 deletions lib/WasmReader/Chakra.WasmReader.vcxproj.filters
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@
<ClInclude Include="WasmBytecodeGenerator.h" />
<ClInclude Include="WasmBinaryReader.h" />
<ClInclude Include="WasmBinaryOpcodes.h" />
<ClInclude Include="WasmBinaryOpcodesSimd.h" />
<ClInclude Include="WasmSignature.h" />
<ClInclude Include="WasmSections.h" />
<ClInclude Include="WasmSection.h" />
Expand Down
5 changes: 5 additions & 0 deletions lib/WasmReader/EmptyWasmByteCodeWriter.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,11 @@ namespace Js
virtual void AsmReg1(OpCodeAsmJs op, RegSlot R0) override {}
virtual void AsmReg2(OpCodeAsmJs op, RegSlot R0, RegSlot R1) override {}
virtual void AsmReg3(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2) override {}
virtual void AsmReg5(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4) override {}
virtual void AsmReg9(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8) override {}
virtual void AsmReg17(OpCodeAsmJs op, RegSlot R0, RegSlot R1, RegSlot R2, RegSlot R3, RegSlot R4, RegSlot R5, RegSlot R6, RegSlot R7, RegSlot R8,
RegSlot R9, RegSlot R10, RegSlot R11, RegSlot R12, RegSlot R13, RegSlot R14, RegSlot R15, RegSlot R16) override {}

virtual void AsmSlot(OpCodeAsmJs op, RegSlot value, RegSlot instance, int32 slotId) override {}
virtual void AsmBr(ByteCodeLabel labelID, OpCodeAsmJs op = OpCodeAsmJs::AsmBr) override {}
virtual void AsmBrReg1(OpCodeAsmJs op, ByteCodeLabel labelID, RegSlot R1) override {}
Expand Down
Loading