From 287cf001e74d4e202a799edd98fb229bd3a65f48 Mon Sep 17 00:00:00 2001 From: Liu Xiaoyi Date: Fri, 11 Feb 2022 10:29:15 +0800 Subject: [PATCH] Add width check in LSBOr and MSBOr --- .../experimental/util/algorithm/Bitwise.scala | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala b/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala index 77ba3beb925..011c29c94e9 100644 --- a/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala +++ b/src/main/scala/chisel3/experimental/util/algorithm/Bitwise.scala @@ -13,9 +13,15 @@ import chisel3._ * This circuit seems to be high fan out, but synthesis tool should handle this. */ object LSBOr { - def apply(data: UInt): UInt = VecInit(Seq.tabulate(data.getWidth) { i: Int => - VecInit(data.asBools().dropRight(data.getWidth - i - 1)).asUInt().orR() - }).asUInt() + def apply(data: UInt): UInt = { + val width = data.widthOption match { + case Some(w) => w + case None => throw new IllegalArgumentException("Cannot call LSBOr on data with unknown width.") + } + VecInit(Seq.tabulate(width) { i: Int => + VecInit(data.asBools().dropRight(width - i - 1)).asUInt().orR() + }).asUInt() + } } /** Map each bits to logical or of itself and all bits more siginificant than it. @@ -27,7 +33,13 @@ object LSBOr { * This circuit seems to be high fan out, but synthesis tool should handle this. */ object MSBOr { - def apply(data: UInt): UInt = VecInit(Seq.tabulate(data.getWidth) { i: Int => - VecInit(data.asBools().drop(i)).asUInt().orR() - }).asUInt() + def apply(data: UInt): UInt = { + val width = data.widthOption match { + case Some(w) => w + case None => throw new IllegalArgumentException("Cannot call MSBOr on data with unknown width.") + } + VecInit(Seq.tabulate(width) { i: Int => + VecInit(data.asBools().drop(i)).asUInt().orR() + }).asUInt() + } }