From b961900dd74302eed3aed0e3d480d2f4786ac9e0 Mon Sep 17 00:00:00 2001
From: "mergify[bot]" <37929162+mergify[bot]@users.noreply.github.com>
Date: Tue, 20 Sep 2022 23:32:17 +0000
Subject: [PATCH] Change description for SInt unary negation (#2729) (#2733)

Referenced to: chipsalliance/chisel3#2728

(cherry picked from commit a4dae9c340c71c063cf0fdec290a6e011b82746d)

Co-authored-by: Marco Origlia <30799310+moriglia@users.noreply.github.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
---
 core/src/main/scala/chisel3/Bits.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
index 00f0afaa391..03bc31acb85 100644
--- a/core/src/main/scala/chisel3/Bits.scala
+++ b/core/src/main/scala/chisel3/Bits.scala
@@ -732,7 +732,7 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
   private[chisel3] override def cloneTypeWidth(w: Width): this.type =
     new SInt(w).asInstanceOf[this.type]
 
-  /** Unary negation (expanding width)
+  /** Unary negation (constant width)
     *
     * @return a hardware $coll equal to zero minus this $coll
     * $constantWidth