From c161fccdc2341201f4c240cb38654d75aaaceadd Mon Sep 17 00:00:00 2001
From: Deborah Soung <debs@sifive.com>
Date: Tue, 27 Feb 2024 16:20:52 -0800
Subject: [PATCH] Add `suggestName` method to `HasTarget` (#3881)

---
 core/src/main/scala/chisel3/package.scala     | 11 +++++++-
 .../scala/chiselTests/util/SRAMSpec.scala     | 28 +++++++++++++++++++
 2 files changed, 38 insertions(+), 1 deletion(-)

diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index bb7e04a1831..9485054ef49 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -414,12 +414,19 @@ package object chisel3 {
 
   final val deprecatedPublicAPIMsg = "APIs in chisel3.internal are not intended to be public"
 
-  /** Contains universal methods for target accesses.
+  /** Exposes target information and suggestName functionality of a NamedComponent.
     */
   sealed trait HasTarget {
     def toTarget:         ReferenceTarget
     def toAbsoluteTarget: ReferenceTarget
     def toRelativeTarget(root: Option[BaseModule]): ReferenceTarget
+
+    /** Exposes the suggestName method of the NamedComponent so users can
+      * provide a seed to influence the name generation of this component.
+      *
+      * @param seed seed for the name of this component
+      */
+    def suggestName(seed: String): Unit
   }
 
   object HasTarget {
@@ -431,6 +438,8 @@ package object chisel3 {
       def toTarget = t.toTarget
       def toAbsoluteTarget = t.toAbsoluteTarget
       def toRelativeTarget(root: Option[BaseModule]) = t.toRelativeTarget(root)
+
+      def suggestName(seed: String): Unit = t.suggestName(seed)
     }
 
   }
diff --git a/src/test/scala/chiselTests/util/SRAMSpec.scala b/src/test/scala/chiselTests/util/SRAMSpec.scala
index 79974e1d1ea..117356bf197 100644
--- a/src/test/scala/chiselTests/util/SRAMSpec.scala
+++ b/src/test/scala/chiselTests/util/SRAMSpec.scala
@@ -42,4 +42,32 @@ class SRAMSpec extends ChiselFlatSpec {
     dummyAnno should be(Some("~Top|Top>sram_mem"))
   }
 
+  it should "Get emitted with a custom name when one is suggested" in {
+
+    class Top extends Module {
+      val sramInterface = SRAM(
+        size = 32,
+        tpe = UInt(8.W),
+        numReadPorts = 0,
+        numWritePorts = 0,
+        numReadwritePorts = 1
+      )
+      require(sramInterface.underlying.nonEmpty)
+      sramInterface.underlying.get.suggestName("carrot")
+      annotate(new ChiselAnnotation {
+        override def toFirrtl: Annotation = DummyAnno(sramInterface.underlying.get.toTarget)
+      })
+    }
+    val (chirrtlCircuit, annos) = getFirrtlAndAnnos(new Top)
+    val chirrtl = chirrtlCircuit.serialize
+    chirrtl should include("module Top :")
+    chirrtl should include("smem carrot : UInt<8> [32]")
+    chirrtl should include(
+      "wire sramInterface : { readPorts : { flip address : UInt<5>, flip enable : UInt<1>, data : UInt<8>}[0], writePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip data : UInt<8>}[0], readwritePorts : { flip address : UInt<5>, flip enable : UInt<1>, flip isWrite : UInt<1>, readData : UInt<8>, flip writeData : UInt<8>}[1]}"
+    )
+
+    val dummyAnno = annos.collectFirst { case DummyAnno(t) => (t.toString) }
+    dummyAnno should be(Some("~Top|Top>carrot"))
+  }
+
 }