One-file-per-module is incompatible with ChiselStage.emit*

[seldridge]

The following fails and it shouldn't:

import chisel3._
import chisel3.stage.ChiselStage

class Foo extends Module {
  val io = IO(new Bundle {
    val in = Input(Bool())
    val out = Output(Bool())
  })

  io.out := ~io.in
}

println((new ChiselStage).emitVerilog(new Foo, Array("-e", "verilog")))

This does a None.get because the -e results in one-file-per-module and the match is narrowly looking for an EmittedCircuitAnnotation.

Change the behavior here so that this works with -e by appending the individual emitted modules together.

Type of issue: bug report

Impact: no functional change

Development Phase: proposal

Other information

https://gitter.im/freechipsproject/chisel3?at=5f90959ca7e77a0ff1602e6e

If the current behavior is a bug, please provide the steps to reproduce the problem:

Compile the example above.

What is the current behavior?

None.get exception.

What is the expected behavior?

No match error.

Please tell us about your environment:

3.4.0

What is the use case for changing the behavior?

This is an extremely confusing error for an end user...