Add --targetDir option and verilog generation to Makefile and chiselTests. #16
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Add the Chisel2 --targetDir option to control where output is created.
Add Stack.scala to chiselTests (sole purpose is to generate .fir output file).
Add main.scala to chiselTests to elaborate tests and generate .fir files.
Update Makefile to use current tooling to generate Verilog output (firrtl).