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Tweaks to the Verilog-vs-Chisel Page #2432

Merged
merged 4 commits into from
Mar 7, 2022
Merged

Tweaks to the Verilog-vs-Chisel Page #2432

merged 4 commits into from
Mar 7, 2022

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mwachs5
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@mwachs5 mwachs5 commented Mar 4, 2022 •
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Contributor Checklist

  • [N/A] Did you add Scaladoc to every public function/method?
  • [N/A] Did you add at least one test demonstrating the PR?
  • Did you delete any extraneous printlns/debugging code?
  • Did you specify the type of improvement?
  • Did you add appropriate documentation in docs/src?
  • Did you state the API impact?
  • Did you specify the code generation impact?
  • Did you request a desired merge strategy?
  • Did you add text to be included in the Release Notes for this change?

Type of Improvement

  • bug fix
  • documentation

API Impact

No impact

Backend Code Generation Impact

No impact

Desired Merge Strategy

  • Squash: The PR will be squashed and merged (choose this if you have no preference.

Release Notes

Minor tweaks to the Verilog-vs-Chisel Documentation page

@Shorla FYI

Reviewer Checklist (only modified by reviewer)

  • Did you add the appropriate labels?
  • Did you mark the proper milestone (Bug fix: 3.4.x, [small] API extension: 3.5.x, API modification or big change: 3.6.0)?
  • Did you review?
  • Did you check whether all relevant Contributor checkboxes have been checked?
  • Did you mark as Please Merge?

@mwachs5 mwachs5 requested a review from debs-sifive March 4, 2022 17:21
@mwachs5 mwachs5 requested a review from jackkoenig March 4, 2022 17:24
@mwachs5 mwachs5 added this to the 3.5.x milestone Mar 4, 2022
@mwachs5 mwachs5 added the Please Merge Accepted PRs that are ready to be merged. Useful when waiting on CI. label Mar 7, 2022
@mergify mergify bot merged commit 7432bdf into master Mar 7, 2022
@mergify mergify bot deleted the verilog-vs-chisel-patches branch March 7, 2022 07:21
mergify bot pushed a commit that referenced this pull request Mar 7, 2022
@mwachs5
Tweaks to the Verilog-vs-Chisel Page (#2432)
76f08fd 
* Tweaks to the Verilog-vs-Chisel Page

* Update cookbook.md

* Update verilog-vs-chisel.md

* Update verilog-vs-chisel.md

(cherry picked from commit 7432bdf)
@mergify mergify bot mentioned this pull request Mar 7, 2022
Merged
@mergify mergify bot added the Backported This PR has been backported label Mar 7, 2022
mergify bot added a commit that referenced this pull request Mar 7, 2022
@mergify @mwachs5
Tweaks to the Verilog-vs-Chisel Page (#2432) (#2433)
6c64093 
* Tweaks to the Verilog-vs-Chisel Page

* Update cookbook.md

* Update verilog-vs-chisel.md

* Update verilog-vs-chisel.md

(cherry picked from commit 7432bdf)

Co-authored-by: Megan Wachs <megan@sifive.com>
@sequencer sequencer mentioned this pull request May 3, 2022
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@jackkoenig jackkoenig jackkoenig approved these changes

@debs-sifive debs-sifive Awaiting requested review from debs-sifive

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