From 38a0f97f07134ed785f3157a2c87948cc8f80136 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 4 Mar 2022 09:21:39 -0800 Subject: [PATCH 1/4] Tweaks to the Verilog-vs-Chisel Page --- docs/src/cookbooks/verilog-vs-chisel.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/src/cookbooks/verilog-vs-chisel.md b/docs/src/cookbooks/verilog-vs-chisel.md index 93fd531681f..bf2e08df949 100644 --- a/docs/src/cookbooks/verilog-vs-chisel.md +++ b/docs/src/cookbooks/verilog-vs-chisel.md @@ -1,3 +1,9 @@ +--- +layout: docs +title: "Verilog-vs-Chisel" +section: "chisel3" +--- + From 986a8ce5e04a90f535545df36e62bf2201eb192b Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 4 Mar 2022 09:23:23 -0800 Subject: [PATCH 2/4] Update cookbook.md --- docs/src/cookbooks/cookbook.md | 1 - 1 file changed, 1 deletion(-) diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md index ea5892c3734..118db228037 100644 --- a/docs/src/cookbooks/cookbook.md +++ b/docs/src/cookbooks/cookbook.md @@ -31,7 +31,6 @@ Please note that these examples make use of [Chisel's scala-style printing](../e * [How can I dynamically set/parametrize the name of a module?](#how-can-i-dynamically-setparametrize-the-name-of-a-module) * Directionality * [How do I strip directions from a bidirectional Bundle (or other Data)?](#how-do-i-strip-directions-from-a-bidirectional-bundle-or-other-data) - * [Side-by-Side Comparison of Verilog to Chisel](verilog-vs-chisel.md) ## Type Conversions From be31ffd1a659179c041999b9bacd23fece02388f Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 4 Mar 2022 09:27:51 -0800 Subject: [PATCH 3/4] Update verilog-vs-chisel.md --- docs/src/cookbooks/verilog-vs-chisel.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/src/cookbooks/verilog-vs-chisel.md b/docs/src/cookbooks/verilog-vs-chisel.md index bf2e08df949..e952c3dd67b 100644 --- a/docs/src/cookbooks/verilog-vs-chisel.md +++ b/docs/src/cookbooks/verilog-vs-chisel.md @@ -8,6 +8,7 @@ section: "chisel3" # Verilog vs Chisel Side-By-Side + This page serves as a quick introduction to Chisel for those familiar with Verilog. It is by no means a comprehensive guide of everything Chisel can do. Feel free to file an issue with suggestions of things you'd like to see added to this page. ```scala mdoc:invisible @@ -694,8 +695,7 @@ ChiselStage.emitVerilog(new ReadWriteMem) Verilog Chisel - Generated Verilog - + From 6012362df0be76ee498093bd3a618a891189c3b8 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 4 Mar 2022 09:30:05 -0800 Subject: [PATCH 4/4] Update verilog-vs-chisel.md --- docs/src/cookbooks/verilog-vs-chisel.md | 5 ----- 1 file changed, 5 deletions(-) diff --git a/docs/src/cookbooks/verilog-vs-chisel.md b/docs/src/cookbooks/verilog-vs-chisel.md index e952c3dd67b..1adf609e4d1 100644 --- a/docs/src/cookbooks/verilog-vs-chisel.md +++ b/docs/src/cookbooks/verilog-vs-chisel.md @@ -133,11 +133,6 @@ class ParameterizedWidthAdder( ``` - - - - -