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Tweaks to the Verilog-vs-Chisel Page #2432

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Mar 7, 2022
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Tweaks to the Verilog-vs-Chisel Page #2432

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Tweaks to the Verilog-vs-Chisel Page
mwachs5 Mar 4, 2022
986a8ce
Update cookbook.md
mwachs5 Mar 4, 2022
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Update verilog-vs-chisel.md
mwachs5 Mar 4, 2022
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Update verilog-vs-chisel.md
mwachs5 Mar 4, 2022
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1 change: 0 additions & 1 deletion docs/src/cookbooks/cookbook.md
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Expand Up @@ -31,7 +31,6 @@ Please note that these examples make use of [Chisel's scala-style printing](../e
* [How can I dynamically set/parametrize the name of a module?](#how-can-i-dynamically-setparametrize-the-name-of-a-module)
* Directionality
* [How do I strip directions from a bidirectional Bundle (or other Data)?](#how-do-i-strip-directions-from-a-bidirectional-bundle-or-other-data)
* [Side-by-Side Comparison of Verilog to Chisel](verilog-vs-chisel.md)

## Type Conversions

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15 changes: 8 additions & 7 deletions docs/src/cookbooks/verilog-vs-chisel.md
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@@ -1,7 +1,14 @@
---
layout: docs
title: "Verilog-vs-Chisel"
section: "chisel3"
---

<!Doctype html>
<html>

# Verilog vs Chisel Side-By-Side

This page serves as a quick introduction to Chisel for those familiar with Verilog. It is by no means a comprehensive guide of everything Chisel can do. Feel free to file an issue with suggestions of things you'd like to see added to this page.

```scala mdoc:invisible
Expand Down Expand Up @@ -126,11 +133,6 @@ class ParameterizedWidthAdder(
```
</td>
</tr>
<tr>
<td>

</td>
</tr>
</table>
<html>
<body>
Expand Down Expand Up @@ -688,8 +690,7 @@ ChiselStage.emitVerilog(new ReadWriteMem)
<tr>
<td><b style="font-size:30px">Verilog</b></td>
<td><b style="font-size:30px">Chisel</b></td>
<td><b style="font-size:30px">Generated Verilog</b></td>
</tr>
</tr>
<tr>
<td>

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