From 83a434b10de3eaa39ba5f00eabe59e90fdade516 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Mon, 29 Aug 2022 09:57:46 -0700 Subject: [PATCH] Fix OpaqueSlot handling of contextual names We need to ensure that contextual names stay contextual (ie. sensitive to the module context which is important for naming ports). --- .../scala/chisel3/internal/firrtl/IR.scala | 2 +- src/test/scala/chiselTests/RecordSpec.scala | 35 ++++++++++--------- 2 files changed, 19 insertions(+), 18 deletions(-) diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index d177c85943e..ddad6b10ffd 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -220,7 +220,7 @@ case class Slot(imm: Node, name: String) extends Arg { } case class OpaqueSlot(imm: Node) extends Arg { - override def contextualName(ctx: Component): String = imm.name + override def contextualName(ctx: Component): String = imm.contextualName(ctx) override def name: String = imm.name } diff --git a/src/test/scala/chiselTests/RecordSpec.scala b/src/test/scala/chiselTests/RecordSpec.scala index 5c0b490f217..31914867a27 100644 --- a/src/test/scala/chiselTests/RecordSpec.scala +++ b/src/test/scala/chiselTests/RecordSpec.scala @@ -150,16 +150,18 @@ trait RecordSpecUtils { val in = IO(Input(new InnerRecord)) val out = IO(Output(new InnerRecord)) val inst = Module(new InnerModule) - inst.foo := in - out := inst.bar + inst.io.foo := in + out := inst.io.bar } class InnerModule extends Module { - val foo = IO(Input(new InnerRecord)) - val bar = IO(Output(new InnerRecord)) + val io = IO(new Bundle { + val foo = Input(new InnerRecord) + val bar = Output(new InnerRecord) + }) // DO NOT do this; just for testing element connections - bar.elements.head._2 := foo.elements.head._2 + io.bar.elements.head._2 := io.foo.elements.head._2 } class NamedSingleElementRecord extends Record { @@ -239,25 +241,24 @@ class RecordSpec extends ChiselFlatSpec with RecordSpecUtils with Utils { var mod: NestedRecordModule = null ChiselStage.elaborate { mod = new NestedRecordModule; mod } val testStrings = Seq( - mod.in.toTarget.toString(), - mod.in.k.toTarget.toString(), - mod.in.k.k.toTarget.toString(), - mod.in.elements.head._2.toTarget.toString(), - mod.in.k.elements.head._2.toTarget.toString(), - mod.in.k.k.elements.head._2.toTarget.toString() + mod.inst.io.foo.toTarget.serialize, + mod.inst.io.foo.k.toTarget.serialize, + mod.inst.io.foo.k.k.toTarget.serialize, + mod.inst.io.foo.elements.head._2.toTarget.serialize, + mod.inst.io.foo.k.elements.head._2.toTarget.serialize, + mod.inst.io.foo.k.k.elements.head._2.toTarget.serialize ) - testStrings.foreach(x => assert(x == "~NestedRecordModule|NestedRecordModule>in")) + testStrings.foreach(x => assert(x == "~NestedRecordModule|InnerModule>io.foo")) } they should "work correctly when connecting nested opaque type elements" in { val nestedRecordChirrtl = ChiselStage.emitChirrtl { new NestedRecordModule } nestedRecordChirrtl should include("input in : UInt<8>") nestedRecordChirrtl should include("output out : UInt<8>") - nestedRecordChirrtl should include("inst.foo <= in") - nestedRecordChirrtl should include("out <= inst.bar") - nestedRecordChirrtl should include("input foo : UInt<8>") - nestedRecordChirrtl should include("output bar : UInt<8>") - nestedRecordChirrtl should include("bar <= foo") + nestedRecordChirrtl should include("inst.io.foo <= in") + nestedRecordChirrtl should include("out <= inst.io.bar") + nestedRecordChirrtl should include("output io : { flip foo : UInt<8>, bar : UInt<8>}") + nestedRecordChirrtl should include("io.bar <= io.foo") } they should "throw an error when map contains a named element and opaqueType is overriden to true" in {