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Rocket Chip Generator 🚀 Build Status

This repository contains the Rocket chip generator necessary to instantiate the RISC-V Rocket Core. For more information on Rocket Chip, please consult our technical report.

RocketChip Dev Meeting

RocketChip development meetings happen every 2 weeks on Wednesday 17:00 – 18:00am CST (Pacific Time - Los Angeles) with meeting notes here:

  • Click here to subscribe Meeting Schedule(iCal format)
  • Click here to view Meeting Schedule via Google Calendar
  • Click here to join Zoom meeting (ID: 93899365000, passcode: 754340)

For possible time adjustments, they will be negotiated in Slack and published in the calendar.

Table of Contents

Quick Instructions

Checkout The Code

$ git clone https://github.com/ucb-bar/rocket-chip.git
$ cd rocket-chip
$ git submodule update --init

Install Necessary Dependencies

You may need to install some additional packages to use this repository. Rather than list all dependencies here, please see the appropriate section of the READMEs for each of the subprojects:

Building The Project

Generating verilog

$ make verilog

Generating verilog for a specific Config

$ make verilog CONFIG=DefaultSmallConfig

Keeping Your Repo Up-to-Date

If you are trying to keep your repo up to date with this GitHub repo, you also need to keep the submodules and tools up to date.

$ # Get the newest versions of the files in this repo
$ git pull origin master
$ # Make sure the submodules have the correct versions
$ git submodule update --init --recursive

If rocket-tools version changes, you should recompile and install rocket-tools according to the directions in the rocket-tools/README.

$ cd rocket-tools
$ ./build.sh
$ ./build-rv32ima.sh (if you are using RV32)

What's in the Rocket chip generator repository?

The rocket-chip repository is a meta-repository that points to several sub-repositories using Git submodules. Those repositories contain tools needed to generate and test SoC designs. This respository also contains code that is used to generate RTL. Hardware generation is done using Chisel, a hardware construction language embedded in Scala. The rocket-chip generator is a Scala program that invokes the Chisel compiler in order to emit RTL describing a complete SoC. The following sections describe the components of this repository.

Git Submodules

Git submodules allow you to keep a Git repository as a subdirectory of another Git repository. For projects being co-developed with the Rocket Chip Generator, we have often found it expedient to track them as submodules, allowing for rapid exploitation of new features while keeping commit histories separate. As submoduled projects adopt stable public APIs, we transition them to external dependencies. Here are the submodules that are currently being tracked in the rocket-chip repository:

Scala Packages

In addition to submodules that track independent Git repositories, the rocket-chip code base is itself factored into a number of Scala packages. These packages are all found within the src/main/scala directory. Some of these packages provide Scala utilities for generator configuration, while other contain the actual Chisel RTL generators themselves. Here is a brief description of what can be found in each package:

  • amba This RTL package uses diplomacy to generate bus implementations of AMBA protocols, including AXI4, AHB-lite, and APB.
  • config This utility package provides Scala interfaces for configuring a generator via a dynamically-scoped parameterization library.
  • coreplex This RTL package generates a complete coreplex by gluing together a variety of components from other packages, including: tiled Rocket cores, a system bus network, coherence agents, debug devices, interrupt handlers, externally-facing peripherals, clock-crossers and converters from TileLink to external bus protocols (e.g. AXI or AHB).
  • devices This RTL package contains implementations for peripheral devices, including the Debug module and various TL slaves.
  • diplomacy This utility package extends Chisel by allowing for two-phase hardware elaboration, in which certain parameters are dynamically negotiated between modules. For more information about diplomacy, see this paper.
  • groundtest This RTL package generates synthesizable hardware testers that emit randomized memory access streams in order to stress-tests the uncore memory hierarchy.
  • jtag This RTL package provides definitions for generating JTAG bus interfaces.
  • regmapper This utility package generates slave devices with a standardized interface for accessing their memory-mapped registers.
  • rocket This RTL package generates the Rocket in-order pipelined core, as well as the L1 instruction and data caches. This library is intended to be used by a chip generator that instantiates the core within a memory system and connects it to the outside world.
  • tile This RTL package contains components that can be combined with cores to construct tiles, such as FPUs and accelerators.
  • tilelink This RTL package uses diplomacy to generate bus implementations of the TileLink protocol. It also contains a variety of adapters and protocol converters.
  • system This top-level utility package invokes Chisel to elaborate a particular configuration of a coreplex, along with the appropriate testing collateral.
  • unittest This utility package contains a framework for generateing synthesizable hardware testers of individual modules.
  • util This utility package provides a variety of common Scala and Chisel constructs that are re-used across multiple other packages,

Other Resources

Outside of Scala, we also provide a variety of resources to create a complete SoC implementation and test the generated designs.

  • bootrom Sources for the first-stage bootloader included in the BootROM.
  • csrc C sources for use with Verilator simulation.
  • docs Documentation, tutorials, etc for specific parts of the codebase.
  • emulator Directory in which Verilator simulations are compiled and run.
  • regression Defines continuous integration and nightly regression suites.
  • scripts Utilities for parsing the output of simulations or manipulating the contents of source files.
  • vsim Directory in which Synopsys VCS simulations are compiled and run.
  • vsrc Verilog sources containing interfaces, harnesses and VPI.

IDEs Support

The Rocket Chip Scala build uses mill as build tool.

IDEs like IntelliJ and VSCode are popular in the Scala community and work with Rocket Chip.

The Rocket Chip currently uses nix to configure the build and/or development environment, you need to install it first depending on your OS distro.

Then follow the steps:

  1. Generate BSP config by running:

    mill mill.bsp.BSP/install

  2. Patch the argv in .bsp/mill-bsp.json, from

    {"name":"mill-bsp","argv":["/usr/bin/mill","--bsp","--disable-ticker","--color","false","--jobs","1"],"millVersion":"0.10.9","bspVersion":"2.0.0","languages":["scala","java"]}

    to

    {"name":"mill-bsp","argv":["/usr/bin/nix","develop","-c","mill","--bsp","--disable-ticker","--color","false","--jobs","1"],"millVersion":"0.10.9","bspVersion":"2.0.0","languages":["scala","java"]}

For IntelliJ users

  1. Install and configure Scala plugin.

  2. BSP should be automatically run. If it doesn't, click bsp on the right bar, then right-click on your project to reload.

For VSCode users

  1. Install and configure Metals extension.

  2. Execute VSCode command Metals: Import build.

Contributors

Contributing guidelines can be found in CONTRIBUTING.md.

A list of contributors can be found here.

Attribution

If used for research, please cite Rocket Chip by the technical report:

Krste Asanović, Rimas Avižienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, The Rocket Chip Generator, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016