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update imports based on scalafix after rebasing
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hcook committed Nov 13, 2020
1 parent 0ec4bd7 commit 10bf48a
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Showing 3 changed files with 2 additions and 4 deletions.
3 changes: 1 addition & 2 deletions src/main/scala/interrupts/BlockDuringReset.scala
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Expand Up @@ -2,9 +2,8 @@

package freechips.rocketchip.interrupts

import chisel3._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.util.BlockDuringReset

/** BlockDuringReset ensures that no interrupt is raised while reset is raised. */
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2 changes: 1 addition & 1 deletion src/main/scala/subsystem/HasTiles.scala
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Expand Up @@ -12,7 +12,7 @@ import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalModuleTree
import freechips.rocketchip.interrupts._
import freechips.rocketchip.tile.{BaseTile, LookupByHartIdImpl, TileParams, InstantiableTileParams, MaxHartIdBits, TilePRCIDomain}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.prci.{ClockGroup, ClockNode, ResetCrossingType}
import freechips.rocketchip.prci.{ClockGroup, ResetCrossingType}
import freechips.rocketchip.util._

/** Entry point for Config-uring the presence of Tiles */
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1 change: 0 additions & 1 deletion src/main/scala/tilelink/CrossingHelper.scala
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Expand Up @@ -5,7 +5,6 @@ package freechips.rocketchip.tilelink
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.prci._
import freechips.rocketchip.util.RationalDirection

trait TLOutwardCrossingHelper {
type HelperCrossingType <: CrossingType
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