From 1a97b466377a0e5f59f4b34a13b4eabf5928da21 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Tue, 10 Mar 2020 20:03:03 -0700
Subject: [PATCH] config: create and use config alterations WithJustOneBus,
 WithIncoherentTopology, WithCoherentTopology

---
 src/main/scala/subsystem/Configs.scala | 29 ++++++++++++++++++++++----
 src/main/scala/system/Configs.scala    |  8 ++++---
 2 files changed, 30 insertions(+), 7 deletions(-)

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
index 2fefede243e..4734073bc35 100644
--- a/src/main/scala/subsystem/Configs.scala
+++ b/src/main/scala/subsystem/Configs.scala
@@ -43,18 +43,39 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
   case DebugModuleKey => Some(DefaultDebugModuleParams(site(XLen)))
   case CLINTKey => Some(CLINTParams())
   case PLICKey => Some(PLICParams())
+})
+
+/* Composable partial function Configs to set individual parameters */
+
+class WithJustOneBus extends Config((site, here, up) => {
   case TLNetworkTopologyLocated("InSubsystem") => List(
+    JustOneBusTopologyParams(sbus = site(SystemBusKey))
+  )
+})
+
+class WithIncoherentBusTopology extends Config((site, here, up) => {
+  case TLNetworkTopologyLocated("InSubsystem") => List(
+    JustOneBusTopologyParams(sbus = site(SystemBusKey)),
     HierarchicalBusTopologyParams(
-      sbus = site(SystemBusKey),
       pbus = site(PeripheryBusKey),
       fbus = site(FrontBusKey),
-      mbus = site(MemoryBusKey),
       cbus = site(ControlBusKey),
-      l2 = site(BankedL2Key),
       xTypes = SubsystemCrossingParams()))
 })
 
-/* Composable partial function Configs to set individual parameters */
+class WithCoherentBusTopology extends Config((site, here, up) => {
+  case TLNetworkTopologyLocated("InSubsystem") => List(
+    JustOneBusTopologyParams(sbus = site(SystemBusKey)),
+    HierarchicalBusTopologyParams(
+      pbus = site(PeripheryBusKey),
+      fbus = site(FrontBusKey),
+      cbus = site(ControlBusKey),
+      xTypes = SubsystemCrossingParams()),
+    CoherentBusTopologyParams(
+      sbus = site(SystemBusKey),
+      mbus = site(MemoryBusKey),
+      l2 = site(BankedL2Key)))
+})
 
 class WithNBigCores(n: Int) extends Config((site, here, up) => {
   case RocketTilesKey => {
diff --git a/src/main/scala/system/Configs.scala b/src/main/scala/system/Configs.scala
index 2c81ddba1c9..b76507bb07a 100644
--- a/src/main/scala/system/Configs.scala
+++ b/src/main/scala/system/Configs.scala
@@ -22,14 +22,14 @@ class BaseConfig extends Config(
   new BaseSubsystemConfig()
 )
 
-class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)
+class DefaultConfig extends Config(new WithNBigCores(1) ++ new WithCoherentBusTopology ++ new BaseConfig)
 
 class DefaultBufferlessConfig extends Config(new WithBufferlessBroadcastHub ++ new DefaultConfig)
-class DefaultSmallConfig extends Config(new WithNSmallCores(1) ++ new BaseConfig)
+class DefaultSmallConfig extends Config(new WithNSmallCores(1) ++ new WithCoherentBusTopology ++ new BaseConfig)
 class DefaultRV32Config extends Config(new WithRV32 ++ new DefaultConfig)
 
 class DualBankConfig extends Config(new WithNBanks(2) ++ new DefaultConfig)
-class DualCoreConfig extends Config( new WithNBigCores(2) ++ new BaseConfig)
+class DualCoreConfig extends Config(new WithNBigCores(2) ++ new WithCoherentBusTopology ++ new BaseConfig)
 class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new DefaultConfig)
 class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new DefaultConfig)
 
@@ -54,6 +54,7 @@ class TinyConfig extends Config(
   new WithNMemoryChannels(0) ++
   new WithNBanks(0) ++
   new With1TinyCore ++
+  new WithIncoherentBusTopology ++
   new BaseConfig)
 
 class MemPortOnlyConfig extends Config(
@@ -69,6 +70,7 @@ class MMIOPortOnlyConfig extends Config(
   new WithNBanks(0) ++
   new WithIncoherentTiles ++
   new WithScratchpadsOnly ++
+  new WithIncoherentBusTopology ++
   new DefaultConfig
 )