From 2acb5e29977091a145c7b5a076876f986bb342a5 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 28 Oct 2020 10:12:02 -0700
Subject: [PATCH] update imports based on scalafix after rebasing

---
 src/main/scala/interrupts/BlockDuringReset.scala | 3 +--
 src/main/scala/subsystem/HasTiles.scala          | 2 +-
 src/main/scala/tilelink/CrossingHelper.scala     | 1 -
 3 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/interrupts/BlockDuringReset.scala b/src/main/scala/interrupts/BlockDuringReset.scala
index 3697b853aea..e4bc77231b8 100644
--- a/src/main/scala/interrupts/BlockDuringReset.scala
+++ b/src/main/scala/interrupts/BlockDuringReset.scala
@@ -2,9 +2,8 @@
 
 package freechips.rocketchip.interrupts
 
-import chisel3._
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
 import freechips.rocketchip.util.BlockDuringReset
 
 /** BlockDuringReset ensures that no interrupt is raised while reset is raised. */
diff --git a/src/main/scala/subsystem/HasTiles.scala b/src/main/scala/subsystem/HasTiles.scala
index 446e63fd745..41ef05e2af6 100644
--- a/src/main/scala/subsystem/HasTiles.scala
+++ b/src/main/scala/subsystem/HasTiles.scala
@@ -12,7 +12,7 @@ import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{LogicalModuleTree
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.tile.{BaseTile, LookupByHartIdImpl, TileParams, InstantiableTileParams, MaxHartIdBits, TilePRCIDomain}
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.prci.{ClockGroup, ClockNode, ResetCrossingType}
+import freechips.rocketchip.prci.{ClockGroup, ResetCrossingType}
 import freechips.rocketchip.util._
 
 /** Entry point for Config-uring the presence of Tiles */
diff --git a/src/main/scala/tilelink/CrossingHelper.scala b/src/main/scala/tilelink/CrossingHelper.scala
index 1ac4528b45c..2a6797f9e56 100644
--- a/src/main/scala/tilelink/CrossingHelper.scala
+++ b/src/main/scala/tilelink/CrossingHelper.scala
@@ -5,7 +5,6 @@ package freechips.rocketchip.tilelink
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
-import freechips.rocketchip.util.RationalDirection
 
 trait TLOutwardCrossingHelper {
   type HelperCrossingType <: CrossingType