subsystem: put two CoherenceManagerInstantiationFns in CoherenceManag…

…erWrapper object
chipsalliance · Apr 15, 2020 · 30cb4ea · 30cb4ea
1 parent c9f39f7
commit 30cb4ea
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Showing 2 changed files with 28 additions and 21 deletions.
diff --git a/src/main/scala/subsystem/BankedL2Params.scala b/src/main/scala/subsystem/BankedL2Params.scala
@@ -8,40 +8,34 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
+import CoherenceManagerWrapper._
 
-// TODO: applies to all caches, for now
+/** Global cache coherence granularity, which applies to all caches, for now. */
 case object CacheBlockBytes extends Field[Int](64)
 
+/** L2 Broadcast Hub configuration */
 case object BroadcastKey extends Field(BroadcastParams())
-case object BankedL2Key extends Field(BankedL2Params())
 
-/** L2 Broadcast Hub configuration */
 case class BroadcastParams(
   nTrackers:  Int     = 4,
   bufferless: Boolean = false)
 
 /** L2 memory subsystem configuration */
+case object BankedL2Key extends Field(BankedL2Params())
+
 case class BankedL2Params(
   nBanks: Int = 1,
-  coherenceManager: CoherenceManagerWrapper.CoherenceManagerInstantiationFn = { subsystem =>
-    implicit val p = subsystem.p
-    val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
-    val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
-    val ss = TLSourceShrinker(nTrackers)
-    ss :*= bh.node
-    (bh.node, ss, None)
-  }
+  coherenceManager: CoherenceManagerInstantiationFn = broadcastManager
 ) {
   require (isPow2(nBanks) || nBanks == 0)
 }
 
-
 case class CoherenceManagerWrapperParams(
     blockBytes: Int,
     beatBytes: Int,
     nBanks: Int,
     name: String)
-  (val coherenceManager: CoherenceManagerWrapper.CoherenceManagerInstantiationFn)
+  (val coherenceManager: CoherenceManagerInstantiationFn)
   extends HasTLBusParams 
   with TLBusWrapperInstantiationLike
 {
@@ -55,10 +49,6 @@ case class CoherenceManagerWrapperParams(
   }
 }
 
-object CoherenceManagerWrapper {
-  type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode])
-}
-
 class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) {
   val (tempIn, tempOut, halt) = params.coherenceManager(context)
 
@@ -71,3 +61,21 @@ class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: Ha
     if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) :*= node }
   val outwardNode = banked(tempOut)
 }
+
+object CoherenceManagerWrapper {
+  type CoherenceManagerInstantiationFn = HasTileLinkLocations => (TLInwardNode, TLOutwardNode, Option[IntOutwardNode])
+
+  val broadcastManager: CoherenceManagerInstantiationFn = { context =>
+    implicit val p = context.p
+    val BroadcastParams(nTrackers, bufferless) = p(BroadcastKey)
+    val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
+    val ss = TLSourceShrinker(nTrackers)
+    ss :*= bh.node
+    (bh.node, ss, None)
+  }
+
+  val incoherentManager: CoherenceManagerInstantiationFn = { _ =>
+    val node = TLNameNode("no_coherence_manager")
+    (node, node, None)
+  }
+}
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -223,10 +223,9 @@ class WithIncoherentTiles extends Config((site, here, up) => {
   case RocketCrossingKey => up(RocketCrossingKey, site) map { r =>
     r.copy(master = r.master.copy(cork = Some(true)))
   }
-  case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = { subsystem =>
-    val node = TLNameNode("no_coherence_manager")
-    (node, node, None)
-  })
+  case BankedL2Key => up(BankedL2Key, site).copy(
+    coherenceManager = CoherenceManagerWrapper.incoherentManager
+  )
 })
 
 class WithRV32 extends Config((site, here, up) => {