fix bad merge

chipsalliance · Mar 12, 2020 · 3b1a2a8 · 3b1a2a8
1 parent 2be8a2e
commit 3b1a2a8
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/src/main/scala/tilelink/Parameters.scala b/src/main/scala/tilelink/Parameters.scala
@@ -570,6 +570,8 @@ class TLSlavePortParameters private(
     })
   }
 
+  def infoString = "Manager Port Beatbytes = " + beatBytes + "\n" + "Manager Port MinLatency = " + minLatency + "\n\n" + managers.map(_.infoString).mkString
+
   def v1copy(
     managers:   Seq[TLSlaveParameters] = slaves,
     beatBytes:  Int = -1,
@@ -635,8 +637,6 @@ object TLSlavePortParameters {
       minLatency   = minLatency)
   }
 
-  def infoString = "Manager Port Beatbytes = " + beatBytes + "\n" + "Manager Port MinLatency = " + minLatency + "\n\n" + managers.map(_.infoString).mkString
-
 }
 
 object TLManagerPortParameters {