From 724974d92c2018f1f03ebfa739642b38d53798b3 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Tue, 14 May 2024 14:47:02 -0700 Subject: [PATCH] setvl should use new vtype to compute vlMax --- src/main/scala/rocket/RocketCore.scala | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala index dfa54e5e71f..82c2b2a2518 100644 --- a/src/main/scala/rocket/RocketCore.scala +++ b/src/main/scala/rocket/RocketCore.scala @@ -466,15 +466,15 @@ class Rocket(tile: RocketTile)(implicit p: Parameters) extends CoreModule()(p) A2_SIZE -> Mux(ex_reg_rvc, 2.S, 4.S))) val (ex_new_vl, ex_new_vconfig) = if (usingVector) { + val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( + ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), + !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_avl = Mux(ex_ctrl.rxs1, Mux(ex_reg_inst(19,15) === 0.U, - Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, csr.io.vector.get.vconfig.vtype.vlMax), + Mux(ex_reg_inst(11,6) === 0.U, csr.io.vector.get.vconfig.vl, ex_new_vtype.vlMax), ex_rs(0) ), ex_reg_inst(19,15)) - val ex_new_vtype = VType.fromUInt(MuxCase(ex_rs(1), Seq( - ex_reg_inst(31,30).andR -> ex_reg_inst(29,20), - !ex_reg_inst(31) -> ex_reg_inst(30,20)))) val ex_new_vl = ex_new_vtype.vl(ex_avl, csr.io.vector.get.vconfig.vl, false.B, false.B, false.B) val ex_new_vconfig = Wire(new VConfig) ex_new_vconfig.vtype := ex_new_vtype