diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala
index 347466709f1..f2c8ebbf333 100644
--- a/src/main/scala/subsystem/BaseSubsystem.scala
+++ b/src/main/scala/subsystem/BaseSubsystem.scala
@@ -90,8 +90,7 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem)
 
   val busContextName = "subsystem"
 
-  // TODO must there really always be an "sbus"?
-  val sbus = tlBusWrapperLocationMap(SBUS)
+  val sbus = tlBusWrapperLocationMap(p(TLManagerViewpointLocated(location)))
   tlBusWrapperLocationMap.lift(SBUS).map { _.clockGroupNode := allClockGroupsNode }
 
   // TODO: Preserve legacy implicit-clock behavior for IBUS for now. If binding