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Expose control over take field for all ClockSinkParameters
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jerryz123 committed Aug 24, 2020
1 parent 6eb1a3d commit 9381382
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Showing 7 changed files with 13 additions and 5 deletions.
2 changes: 2 additions & 0 deletions src/main/scala/groundtest/TraceGen.scala
Original file line number Diff line number Diff line change
Expand Up @@ -27,6 +27,7 @@ import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{TileCrossingParamsLike, CanAttachTile}
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters}

// =======
// Outline
Expand Down Expand Up @@ -75,6 +76,7 @@ case class TraceGenParams(
val beuAddr = None
val blockerCtrlAddr = None
val name = None
val clockSinkParams = ClockSinkParameters()
}

trait HasTraceGenParams {
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2 changes: 1 addition & 1 deletion src/main/scala/subsystem/BankedL2Params.scala
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Expand Up @@ -37,12 +37,12 @@ case class CoherenceManagerWrapperParams(
blockBytes: Int,
beatBytes: Int,
nBanks: Int,
dtsFrequency: Option[BigInt],
name: String)
(val coherenceManager: CoherenceManagerInstantiationFn)
extends HasTLBusParams
with TLBusWrapperInstantiationLike
{
val dtsFrequency = None
def instantiate(context: HasTileLinkLocations, loc: Location[TLBusWrapper])(implicit p: Parameters): CoherenceManagerWrapper = {
val cmWrapper = LazyModule(new CoherenceManagerWrapper(this, context))
cmWrapper.suggestName(loc.name + "_wrapper")
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2 changes: 1 addition & 1 deletion src/main/scala/subsystem/BusTopology.scala
Original file line number Diff line number Diff line change
Expand Up @@ -79,7 +79,7 @@ case class CoherentBusTopologyParams(
) extends TLBusWrapperTopology(
instantiations = (if (l2.nBanks == 0) Nil else List(
(MBUS, mbus),
(L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, L2.name)(l2.coherenceManager)))),
(L2, CoherenceManagerWrapperParams(mbus.blockBytes, mbus.beatBytes, l2.nBanks, sbus.dtsFrequency, L2.name)(l2.coherenceManager)))),
connections = if (l2.nBanks == 0) Nil else List(
(SBUS, L2, TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_STAR)()),
(L2, MBUS, TLBusWrapperConnection(driveClockFromMaster = Some(true), nodeBinding = BIND_QUERY)())
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3 changes: 2 additions & 1 deletion src/main/scala/subsystem/HasTiles.scala
Original file line number Diff line number Diff line change
Expand Up @@ -229,7 +229,8 @@ trait CanAttachTile {

/** Narrow waist through which all tiles are intended to pass while being instantiated. */
def instantiate(implicit p: Parameters): TilePRCIDomain[TileType] = {
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](tileParams.hartId) {
val clockSinkParams = tileParams.clockSinkParams.copy(name = Some(s"${tileParams.name.getOrElse("core")}_${tileParams.hartId}"))
val tile_prci_domain = LazyModule(new TilePRCIDomain[TileType](clockSinkParams) {
val tile = LazyModule(tileParams.instantiate(crossingParams, lookup))
})
tile_prci_domain
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2 changes: 2 additions & 0 deletions src/main/scala/tile/BaseTile.scala
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.rocket._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters}

case object TileVisibilityNodeKey extends Field[TLEphemeralNode]
case object TileKey extends Field[TileParams]
Expand All @@ -28,6 +29,7 @@ trait TileParams {
val beuAddr: Option[BigInt]
val blockerCtrlAddr: Option[BigInt]
val name: Option[String]
val clockSinkParams: ClockSinkParameters
}

abstract class InstantiableTileParams[TileType <: BaseTile] extends TileParams {
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3 changes: 3 additions & 0 deletions src/main/scala/tile/RocketTile.scala
Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,8 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.rocket._
import freechips.rocketchip.subsystem.TileCrossingParamsLike
import freechips.rocketchip.util._
import freechips.rocketchip.prci.{ClockSinkParameters}


case class RocketTileParams(
core: RocketCoreParams = RocketCoreParams(),
Expand All @@ -24,6 +26,7 @@ case class RocketTileParams(
hartId: Int = 0,
beuAddr: Option[BigInt] = None,
blockerCtrlAddr: Option[BigInt] = None,
clockSinkParams: ClockSinkParameters = ClockSinkParameters(),
boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
) extends InstantiableTileParams[RocketTile] {
require(icache.isDefined)
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4 changes: 2 additions & 2 deletions src/main/scala/tile/TilePRCIDomain.scala
Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,13 @@ import freechips.rocketchip.tilelink._
* hierarchical P&R boundary buffers, core-local interrupt handling,
* and any other IOs related to PRCI control.
*/
abstract class TilePRCIDomain[T <: BaseTile](id: Int)(implicit p: Parameters)
abstract class TilePRCIDomain[T <: BaseTile](clockSinkParams: ClockSinkParameters)(implicit p: Parameters)
extends ClockDomain
{
val tile: T

val clockNode = ClockIdentityNode()
val clockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(take = None, name = Some(s"core_$id"))))
val clockSinkNode = ClockSinkNode(Seq(clockSinkParams))
def clockBundle = clockSinkNode.in.head._1

/** External code looking to connect and clock-cross the interrupts driven into this tile can call this. */
Expand Down

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