subsystem: MemoryBus supports banking internally/natively

chipsalliance · Mar 13, 2020 · 99e1a12 · 99e1a12
1 parent 187752a
commit 99e1a12
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Showing 3 changed files with 10 additions and 6 deletions.
diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala
@@ -75,7 +75,6 @@ case class CoherentBusTopologyParams(
     (L2, CoherenceManagerWrapperParams(sbus.blockBytes, sbus.beatBytes, L2.name)(l2.coherenceManager)))),
   connections = (if (l2.nBanks == 0) Nil else List(
     (SBUS, L2,   TLBusWrapperCrossToConnection  (NoCrossing)()),
-    (L2,   MBUS, TLBusWrapperCrossToConnection  (NoCrossing)
-      (inject = { implicit p => BankBinder(p(CacheBlockBytes) * (l2.nBanks-1)) }))
+    (L2,   MBUS, TLBusWrapperCrossToConnection  (NoCrossing)())
   ))
 )
diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -34,7 +34,8 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
   case MemoryBusKey => MemoryBusParams(
     beatBytes = site(XLen)/8,
     blockBytes = site(CacheBlockBytes),
-    replicatorMask = site(MultiChipMaskKey))
+    replicatorMask = site(MultiChipMaskKey),
+    nInwardBanks = site(BankedL2Key).nBanks)
   case FrontBusKey => FrontBusParams(
     beatBytes = site(XLen)/8,
     blockBytes = site(CacheBlockBytes))

diff --git a/src/main/scala/subsystem/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala
@@ -17,7 +17,8 @@ case class MemoryBusParams(
   dtsFrequency: Option[BigInt] = None,
   zeroDevice: Option[AddressSet] = None,
   errorDevice: Option[DevNullParams] = None,
-  replicatorMask: BigInt = 0)
+  replicatorMask: BigInt = 0,
+  nInwardBanks: Int = 0)
   extends HasTLBusParams
   with HasBuiltInDeviceParams
   with HasRegionReplicatorParams
@@ -35,8 +36,11 @@ class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p
     extends TLBusWrapper(params, name)(p)
 {
   private val xbar = LazyModule(new TLXbar).suggestName(busName + "_xbar")
-  def inwardNode: TLInwardNode =
-    if (params.replicatorMask == 0) xbar.node else { xbar.node :=* RegionReplicator(params.replicatorMask) }
+  private def replicate(node: TLInwardNode): TLInwardNode =
+    if (params.replicatorMask == 0) node else { node :=* RegionReplicator(params.replicatorMask) }
+  private def bank(node: TLInwardNode): TLInwardNode =
+    if (params.nInwardBanks == 0) node else { node :=* BankBinder(params.nInwardBanks, blockBytes) :*= TLTempNode() }
+  def inwardNode: TLInwardNode = bank(replicate(xbar.node))
   def outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node
   def busView: TLEdge = xbar.node.edges.in.head
   attachBuiltInDevices(params)