From a133d5141d42226eda43db22fdffe6bf1a098c32 Mon Sep 17 00:00:00 2001
From: Abhinay Kayastha <59576105+abhinay-kayastha@users.noreply.github.com>
Date: Wed, 1 Jul 2020 16:11:35 -0500
Subject: [PATCH] Fix the wdata in frfWriteBundle for fp loads (#2546)

---
 src/main/scala/tile/FPU.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/tile/FPU.scala b/src/main/scala/tile/FPU.scala
index 99acf47a003..88ffd551488 100644
--- a/src/main/scala/tile/FPU.scala
+++ b/src/main/scala/tile/FPU.scala
@@ -754,7 +754,7 @@ class FPU(cfg: FPUParams)(implicit p: Parameters) extends FPUModule()(p) {
       printf("f%d p%d 0x%x\n", load_wb_tag, load_wb_tag + 32, load_wb_data)
     frfWriteBundle(0).wrdst := load_wb_tag
     frfWriteBundle(0).wrenf := true.B
-    frfWriteBundle(0).wrdata := load_wb_data
+    frfWriteBundle(0).wrdata := ieee(wdata)
   }
 
   val ex_rs = ex_ra.map(a => regfile(a))