From d585e68013baf46fb48878093304408c9219b76e Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 17 Nov 2020 13:09:20 -0800 Subject: [PATCH] tile: add backwards compatibility trace broadcast node --- src/main/scala/tile/BaseTile.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index 11e9df4654a..9651e352f98 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -256,8 +256,9 @@ abstract class BaseTile private (val crossing: ClockCrossingType, q: Parameters) protected def traceRetireWidth = tileParams.core.retireWidth /** Node for the core to drive legacy "raw" instruction trace. */ val traceSourceNode = BundleBridgeSource(() => Vec(traceRetireWidth, new TracedInstruction())) + private val traceNexus = BundleBroadcast[Vec[TracedInstruction]]() // backwards compatiblity; not blocked during stretched reset /** Node for external consumers to source a legacy instruction trace from the core. */ - val traceNode: BundleBridgeOutwardNode[Vec[TracedInstruction]] = traceSourceNode + val traceNode: BundleBridgeOutwardNode[Vec[TracedInstruction]] = traceNexus := traceSourceNode protected def traceCoreParams = new TraceCoreParams() /** Node for core to drive instruction trace conforming to RISC-V Processor Trace spec V1.0 */