diff --git a/src/main/scala/subsystem/BankedL2Params.scala b/src/main/scala/subsystem/BankedL2Params.scala index 717434c5064..f6e15129532 100644 --- a/src/main/scala/subsystem/BankedL2Params.scala +++ b/src/main/scala/subsystem/BankedL2Params.scala @@ -4,6 +4,7 @@ package freechips.rocketchip.subsystem import chisel3.util.isPow2 import freechips.rocketchip.config._ +import freechips.rocketchip.devices.tilelink.BuiltInDevices import freechips.rocketchip.diplomacy._ import freechips.rocketchip.interrupts._ import freechips.rocketchip.tilelink._ @@ -56,6 +57,7 @@ class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: Ha val viewNode = TLIdentityNode() def busView: TLEdge = viewNode.edges.out.head val inwardNode = tempIn :*= viewNode + val builtInDevices = BuiltInDevices.none private def banked(node: TLOutwardNode): TLOutwardNode = if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) :*= node } diff --git a/src/main/scala/subsystem/BaseSubsystem.scala b/src/main/scala/subsystem/BaseSubsystem.scala index 4f679b1bad5..a72994850ea 100644 --- a/src/main/scala/subsystem/BaseSubsystem.scala +++ b/src/main/scala/subsystem/BaseSubsystem.scala @@ -62,7 +62,7 @@ trait HasConfigurableTLNetworkTopology { this: HasTileLinkLocations => // Calling these functions populates tlBusWrapperLocationMap and connects the locations to each other. val topology = p(TLNetworkTopologyLocated(location)) - private val buses = topology.map(_.instantiate(this)) + topology.map(_.instantiate(this)) topology.foreach(_.connect(this)) // This is used lazily at DTS binding time to get a view of the network @@ -115,7 +115,7 @@ abstract class BaseSubsystem(val location: HierarchicalLocation = InSubsystem) lazy val logicalTreeNode = new SubsystemLogicalTreeNode() - buses.foreach { bus => + tlBusWrapperLocationMap.values.foreach { bus => val builtIn = bus.builtInDevices builtIn.errorOpt.foreach { error => LogicalModuleTree.add(logicalTreeNode, error.logicalTreeNode)