subsystem: move nBanks and binder to CoherenceManagerWrapper

chipsalliance · Mar 30, 2020 · e93ec18 · e93ec18
1 parent 2cd4d58
commit e93ec18
Show file tree

Hide file tree

Showing 4 changed files with 17 additions and 12 deletions.
diff --git a/src/main/scala/subsystem/BankedL2Params.scala b/src/main/scala/subsystem/BankedL2Params.scala
@@ -36,7 +36,11 @@ case class BankedL2Params(
 }
 
 
-case class CoherenceManagerWrapperParams(blockBytes: Int, beatBytes: Int, name: String)
+case class CoherenceManagerWrapperParams(
+    blockBytes: Int,
+    beatBytes: Int,
+    nBanks: Int,
+    name: String)
   (val coherenceManager: CoherenceManagerWrapper.CoherenceManagerInstantiationFn)
   extends HasTLBusParams 
   with TLBusWrapperInstantiationLike
@@ -56,9 +60,14 @@ object CoherenceManagerWrapper {
 }
 
 class CoherenceManagerWrapper(params: CoherenceManagerWrapperParams, context: HasTileLinkLocations)(implicit p: Parameters) extends TLBusWrapper(params, params.name) {
-  val (temp, outwardNode, halt) = params.coherenceManager(context)
+  val (tempIn, tempOut, halt) = params.coherenceManager(context)
+
   // TODO could remove temp if we could get access to .edges from InwardNodeHandle
   val viewNode = TLIdentityNode()
-  val inwardNode = temp :*= viewNode
   def busView: TLEdge = viewNode.edges.out.head
+  val inwardNode = tempIn :*= viewNode
+
+  private def banked(node: TLOutwardNode): TLOutwardNode =
+    if (params.nBanks == 0) node else { TLTempNode() :=* BankBinder(params.nBanks, params.blockBytes) :*= node }
+  val outwardNode = banked(tempOut)
 }
diff --git a/src/main/scala/subsystem/BusTopology.scala b/src/main/scala/subsystem/BusTopology.scala
@@ -72,7 +72,7 @@ case class CoherentBusTopologyParams(
 ) extends TLBusWrapperTopology(
   instantiations = (if (l2.nBanks == 0) Nil else List(
     (MBUS, mbus),
-    (L2, CoherenceManagerWrapperParams(sbus.blockBytes, sbus.beatBytes, L2.name)(l2.coherenceManager)))),
+    (L2, CoherenceManagerWrapperParams(sbus.blockBytes, sbus.beatBytes, l2.nBanks, L2.name)(l2.coherenceManager)))),
   connections = (if (l2.nBanks == 0) Nil else List(
     (SBUS, L2,   TLBusWrapperConnection.crossTo(NoCrossing)),
     (L2,   MBUS, TLBusWrapperConnection.crossTo(NoCrossing))

diff --git a/src/main/scala/subsystem/Configs.scala b/src/main/scala/subsystem/Configs.scala
@@ -34,8 +34,7 @@ class BaseSubsystemConfig extends Config ((site, here, up) => {
   case MemoryBusKey => MemoryBusParams(
     beatBytes = site(XLen)/8,
     blockBytes = site(CacheBlockBytes),
-    replicatorMask = site(MultiChipMaskKey),
-    nInwardBanks = site(BankedL2Key).nBanks)
+    replicatorMask = site(MultiChipMaskKey))
   case FrontBusKey => FrontBusParams(
     beatBytes = site(XLen)/8,
     blockBytes = site(CacheBlockBytes))

diff --git a/src/main/scala/subsystem/MemoryBus.scala b/src/main/scala/subsystem/MemoryBus.scala
@@ -17,8 +17,7 @@ case class MemoryBusParams(
   dtsFrequency: Option[BigInt] = None,
   zeroDevice: Option[AddressSet] = None,
   errorDevice: Option[DevNullParams] = None,
-  replicatorMask: BigInt = 0,
-  nInwardBanks: Int = 0)
+  replicatorMask: BigInt = 0)
   extends HasTLBusParams
   with HasBuiltInDeviceParams
   with HasRegionReplicatorParams
@@ -39,10 +38,8 @@ class MemoryBus(params: MemoryBusParams, name: String = "memory_bus")(implicit p
   private val xbar = LazyModule(new TLXbar).suggestName(busName + "_xbar")
   private def replicate(node: TLInwardNode): TLInwardNode =
     if (params.replicatorMask == 0) node else { node :=* RegionReplicator(params.replicatorMask) }
-  private def bank(node: TLInwardNode): TLInwardNode =
-    if (params.nInwardBanks == 0) node else { node :=* BankBinder(params.nInwardBanks, blockBytes) :*= TLTempNode() }
-  def inwardNode: TLInwardNode = this { bank(replicate(xbar.node)) }
-  def outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node
+  val inwardNode: TLInwardNode = replicate(xbar.node)
+  val outwardNode: TLOutwardNode = ProbePicker() :*= xbar.node
   def busView: TLEdge = xbar.node.edges.in.head
   attachBuiltInDevices(params)
 }