Instruction page fault when D/A/U bits set in a non-leaf PTE

[sammy17]

Type of issue: bug report

Impact: unknown

Development Phase: request

Other information
From privilege spec (20190608) section 4.3.1:

For non-leaf PTEs, the D, A, and U bits are reserved for future use and must be cleared by software
for forward compatibility

I observed that this behavior is not implemented in Rocket. Spike has fixed the same issue fairly recently with riscv-software-src/riscv-isa-sim#752.
I have attached a testcase that has D/A/U bits set in non-leaf PTEs which should give instruction page fault according to the above sentence from spec.
Spike and rocket RTL sim trace is also attached.

NOTE:
This attached test will go into an infinite loop in spike since the instruction page fault is not handled in the exception handler.

If the current behavior is a bug, please provide the steps to reproduce the problem:

What is the current behavior?
No instruction page fault exceptions when non-leaf PTEs have D/A/U bits set.

What is the expected behavior?
Instruction page fault exception should trigger when non-leaf PTEs have D/A/U bits set.

Please tell us about your environment:
- version: 148d5d2
- OS: Linux 3.10.0-1160.36.2.el7.x86_64 #1 SMP x86_64 x86_64 x86_64 GNU/Linux

What is the use case for changing the behavior?
Compliance with the privilege spec.

Test and trace logs:
rocket.log
spike_1.log
test_1.zip