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Make verilog Error #3657
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Same here. It seems like firtool isn't being built properly and I narrowed down the error portion to this specific piece of code in the build.sc file:
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so what is debup? I have firtool installed and when i run make verilog, the following error occurs:
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To generate Verilog from rocket-chip, I recommend using Chipyard. The rocket-chip repo is intended to be used as a library by more complex projects. |
@yulong-lan |
Hi Team,
we installed rocket tools and chisel in machine and set the path, when we run the cmd "make verilog" in rocket-chip we are geeting attached error. Can you help me on this issue please
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