From e1404d9a421b5b252bd4f10668d510f8a5cc1098 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Tue, 20 Aug 2019 11:20:17 -0700 Subject: [PATCH] Add test_en pin to ClockGate This is intended to help with DFT insertion for explicit clock gates. --- src/main/resources/vsrc/EICG_wrapper.v | 5 +++-- src/main/scala/util/ClockGate.scala | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/main/resources/vsrc/EICG_wrapper.v b/src/main/resources/vsrc/EICG_wrapper.v index 9e22a225dfa..76ee093b616 100644 --- a/src/main/resources/vsrc/EICG_wrapper.v +++ b/src/main/resources/vsrc/EICG_wrapper.v @@ -3,14 +3,15 @@ module EICG_wrapper( output out, input en, + input test_en, input in ); reg en_latched /*verilator clock_enable*/; - always @(en or in) begin + always @(*) begin if (!in) begin - en_latched = en; + en_latched = en || test_en; end end diff --git a/src/main/scala/util/ClockGate.scala b/src/main/scala/util/ClockGate.scala index 9663e4679f8..4cc66838896 100644 --- a/src/main/scala/util/ClockGate.scala +++ b/src/main/scala/util/ClockGate.scala @@ -10,6 +10,7 @@ case object ClockGateImpl extends Field[() => ClockGate](() => new EICG_wrapper) abstract class ClockGate extends BlackBox { val io = IO(new Bundle{ val in = Input(Clock()) + val test_en = Input(Bool()) val en = Input(Bool()) val out = Output(Clock()) }) @@ -23,6 +24,7 @@ object ClockGate { val cg = Module(p(ClockGateImpl)()) name.foreach(cg.suggestName(_)) cg.io.in := in + cg.io.test_en := false.B cg.io.en := en cg.io.out }