Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Debug APB: Prevent aliasing on undefined addresses #2213

Merged
merged 1 commit into from
Dec 2, 2019
Merged

Debug APB: Prevent aliasing on undefined addresses #2213

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
9 changes: 8 additions & 1 deletion src/main/scala/devices/debug/APB.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -10,10 +10,15 @@ import freechips.rocketchip.amba.apb.{APBRegisterNode}

case object APBDebugRegistersKey extends Field[Map[Int, Seq[RegField]]](Map())

object APBDebugConsts {
def apbDebugRegBase = 0xF00
def apbDebugRegSize = 0x100
}

class APBDebugRegisters()(implicit p: Parameters) extends LazyModule {

val node = APBRegisterNode(
address = AddressSet(base=0xF00, mask=0xFF),
address = AddressSet(base=APBDebugConsts.apbDebugRegBase, mask=APBDebugConsts.apbDebugRegSize-1),
beatBytes = 4,
executable = false
)
Expand All @@ -23,3 +28,5 @@ class APBDebugRegisters()(implicit p: Parameters) extends LazyModule {

}
}


18 changes: 14 additions & 4 deletions src/main/scala/devices/debug/Debug.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ import freechips.rocketchip.regmapper._
import freechips.rocketchip.rocket.Instructions
import freechips.rocketchip.tile.MaxHartIdBits
import freechips.rocketchip.tilelink._
import freechips.rocketchip.devices.tilelink.{DevNullParams, TLError}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.util.property._
Expand Down Expand Up @@ -594,6 +595,8 @@ class TLDebugModuleOuter(device: Device)(implicit p: Parameters) extends LazyMod

class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends LazyModule {

val cfg = p(DebugModuleKey).get

val dmiXbar = LazyModule (new TLXbar())

val dmi2tlOpt = (!p(ExportDebug).apb).option({
Expand All @@ -605,14 +608,18 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
val apbNodeOpt = p(ExportDebug).apb.option({
val apb2tl = LazyModule(new APBToTL())
val apb2tlBuffer = LazyModule(new TLBuffer(BufferParams.pipe))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())
val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2
val tlErrorParams = DevNullParams(AddressSet.misaligned(dmTopAddr, APBDebugConsts.apbDebugRegBase-dmTopAddr),
maxAtomic=0, maxTransfer=4)
val tlError = LazyModule(new TLError(tlErrorParams))
val apbXbar = LazyModule(new APBFanout())
val apbRegs = LazyModule(new APBDebugRegisters())

apbRegs.node := apbXbar.node
apb2tl.node := apbXbar.node
apb2tlBuffer.node := apb2tl.node
dmiXbar.node := apb2tlBuffer.node

tlError.node := dmiXbar.node
apbXbar.node
})

Expand Down Expand Up @@ -643,6 +650,7 @@ class TLDebugModuleOuterAsync(device: Device)(implicit p: Parameters) extends La
dmOuter.module.io.hgDebugInt := io.hgDebugInt
io.hartResetReq.foreach { x => dmOuter.module.io.hartResetReq.foreach {y => x := y}}
io.dmAuthenticated.foreach { x => dmOuter.module.io.dmAuthenticated.foreach { y => y := x}}

}
}

Expand All @@ -655,11 +663,13 @@ class TLDebugModuleInner(device: Device, getNComponents: () => Int, beatBytes: I
val cfg = p(DebugModuleKey).get
def getCfg = () => cfg

val dmTopAddr = (1 << cfg.nDMIAddrSize) << 2

val dmiNode = TLRegisterNode(
// Address is range 0 to 0x1FF except DMCONTROL, HAWINDOWSEL, HAWINDOW which are handled by Outer
address = AddressSet.misaligned(0, DMI_DMCONTROL << 2) ++
AddressSet.misaligned((DMI_DMCONTROL + 1) << 2, ((DMI_HAWINDOWSEL << 2) - ((DMI_DMCONTROL + 1) << 2))) ++
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (0x200 - ((DMI_HAWINDOW + 1) << 2))),
AddressSet.misaligned((DMI_HAWINDOW + 1) << 2, (dmTopAddr - ((DMI_HAWINDOW + 1) << 2))),
device = device,
beatBytes = 4,
executable = false
Expand Down