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BEU <-> HART link added in DTS #2373

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merged 2 commits into from
Mar 28, 2020
Merged

BEU <-> HART link added in DTS #2373

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BEU <-> HART link added in DTS
mhtwn Mar 27, 2020
8e8d74f
Update src/main/scala/tile/RocketTile.scala
mhtwn Mar 28, 2020
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6 changes: 5 additions & 1 deletion src/main/scala/tile/RocketTile.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -88,11 +88,15 @@ class RocketTile private(

val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p))

val beuProperty = bus_error_unit.map(d => Map(
"sifive,buserror" -> d.device.asProperty)).getOrElse(Nil)

val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) {
override def parent = Some(ResourceAnchors.cpus)
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty)
Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty
++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty)
}
}

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