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BEU <-> HART link added in DTS #2373

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Mar 28, 2020
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BEU <-> HART link added in DTS #2373

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BEU <-> HART link added in DTS
mhtwn Mar 27, 2020
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Update src/main/scala/tile/RocketTile.scala
mhtwn Mar 28, 2020
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6 changes: 5 additions & 1 deletion src/main/scala/tile/RocketTile.scala
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Expand Up @@ -88,11 +88,15 @@ class RocketTile private(

val itimProperty = frontend.icache.itimProperty.toSeq.flatMap(p => Map("sifive,itim" -> p))

val beuProperty = bus_error_unit.map(d => Map(
"sifive,buserror0" -> d.device.asProperty)).getOrElse(Nil)
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I think it would be more idiomatic and readable to call .toSeq instead of .getOrElse(Nil).

Also, do we actually want to call this sifive,buserror0 or should it just be sifive,buserror?

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It should be not be "sifive,buserror0", but simply be "sifive,buserror" as the version as described in the compatible string.

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ok, i suggested the change, but would like @mhtwn to show what the outputted DTS looks like with this change and get @bsousi5 's final approval before approving the PR

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@mhtwn mhtwn Mar 28, 2020 •
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@mwachs5 its a plain string - it will show up in the dts as is.

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well i see that string in the DTS above in 2 places. I thought that @bsousi5 was saying in the "compat" he expected it to say sifive,buserror0 but the device type to be sifive,buserror

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ok, just to not create any confusion, the dts in the release notes (updated above) is how the generated dts looks:

  1. In the cpu component listing: buserror0 is now -> buserror
  2. Compatible field in the 'bus_error_unit' component still lists sifive_buserror0

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thanks! @bsousi5 if that looks good to you can you please approve the PR? If that's not enough to make it mergable i will approve it

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@bsousi5 bsousi5 Mar 28, 2020 •
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I am good with what @mhtwn commented and shown in the release note above.

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It seems I don't have the permission to hit the approve button. So @mwachs5, you need to approve.

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I do. So I’ve approved based on your, @richardxia and @mwachs5’s reviews.

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val cpuDevice: SimpleDevice = new SimpleDevice("cpu", Seq("sifive,rocket0", "riscv")) {
override def parent = Some(ResourceAnchors.cpus)
override def describe(resources: ResourceBindings): Description = {
val Description(name, mapping) = super.describe(resources)
Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty ++ tileProperties ++ dtimProperty ++ itimProperty)
Description(name, mapping ++ cpuProperties ++ nextLevelCacheProperty
++ tileProperties ++ dtimProperty ++ itimProperty ++ beuProperty)
}
}

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