From e5c0f576d86bd360c5d2e0e65b4fc1cabdcb42b5 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 8 May 2020 18:01:45 -0700 Subject: [PATCH 1/2] Broadcast: Releases should be marked as AMBA cache ops --- src/main/scala/tilelink/Broadcast.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main/scala/tilelink/Broadcast.scala b/src/main/scala/tilelink/Broadcast.scala index 29516fbc0b4..4d134de5d6f 100644 --- a/src/main/scala/tilelink/Broadcast.scala +++ b/src/main/scala/tilelink/Broadcast.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.util.CompileOptions.NotStrictInferReset import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ +import freechips.rocketchip.amba.AMBAProt import scala.math.{min,max} class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters) extends LazyModule @@ -142,6 +143,15 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa val put_who = Mux(c_releasedata, in.c.bits.source, c_trackerSrc) putfull.valid := in.c.valid && (c_probeackdata || c_releasedata) putfull.bits := edgeOut.Put(Cat(put_what, put_who), in.c.bits.address, in.c.bits.size, in.c.bits.data)._2 + putfull.bits.user.lift(AMBAProt).foreach { x => + x.fetch := false.B + x.secure := true.B + x.privileged := true.B + x.bufferable := true.B + x.modifiable := true.B + x.readalloc := true.B + x.writealloc := true.B + } // Combine ReleaseAck or the modified D TLArbiter.lowest(edgeOut, in.d, releaseack, d_normal) From 7c46f54603bf6ea7be333f128526c60ac9925cea Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 8 May 2020 18:02:12 -0700 Subject: [PATCH 2/2] CacheCork: Releases should be marked as AMBA cache ops --- src/main/scala/tilelink/CacheCork.scala | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/main/scala/tilelink/CacheCork.scala b/src/main/scala/tilelink/CacheCork.scala index 08cf94e0883..b832de9b36b 100644 --- a/src/main/scala/tilelink/CacheCork.scala +++ b/src/main/scala/tilelink/CacheCork.scala @@ -6,6 +6,7 @@ import Chisel._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.diplomacy._ import freechips.rocketchip.util._ +import freechips.rocketchip.amba.AMBAProt import scala.math.{min,max} import TLMessages._ @@ -91,6 +92,15 @@ class TLCacheCork(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Paramet lgSize = in.c.bits.size, data = in.c.bits.data, corrupt = in.c.bits.corrupt)._2 + c_a.bits.user.lift(AMBAProt).foreach { x => + x.fetch := false.B + x.secure := true.B + x.privileged := true.B + x.bufferable := true.B + x.modifiable := true.B + x.readalloc := true.B + x.writealloc := true.B + } // Releases without Data succeed instantly val c_d = Wire(in.d)