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Release as amba cache op #2457

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merged 2 commits into from
May 11, 2020
Merged

Release as amba cache op #2457

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e5c0f57
Broadcast: Releases should be marked as AMBA cache ops
terpstra May 9, 2020
7c46f54
CacheCork: Releases should be marked as AMBA cache ops
terpstra May 9, 2020
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10 changes: 10 additions & 0 deletions src/main/scala/tilelink/Broadcast.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ import freechips.rocketchip.util.CompileOptions.NotStrictInferReset
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.amba.AMBAProt
import scala.math.{min,max}

class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = false)(implicit p: Parameters) extends LazyModule
Expand Down Expand Up @@ -142,6 +143,15 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
val put_who = Mux(c_releasedata, in.c.bits.source, c_trackerSrc)
putfull.valid := in.c.valid && (c_probeackdata || c_releasedata)
putfull.bits := edgeOut.Put(Cat(put_what, put_who), in.c.bits.address, in.c.bits.size, in.c.bits.data)._2
putfull.bits.user.lift(AMBAProt).foreach { x =>
x.fetch := false.B
x.secure := true.B
x.privileged := true.B
x.bufferable := true.B
x.modifiable := true.B
x.readalloc := true.B
x.writealloc := true.B
}

// Combine ReleaseAck or the modified D
TLArbiter.lowest(edgeOut, in.d, releaseack, d_normal)
Expand Down
10 changes: 10 additions & 0 deletions src/main/scala/tilelink/CacheCork.scala
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Expand Up @@ -6,6 +6,7 @@ import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util._
import freechips.rocketchip.amba.AMBAProt
import scala.math.{min,max}
import TLMessages._

Expand Down Expand Up @@ -91,6 +92,15 @@ class TLCacheCork(unsafe: Boolean = false, sinkIds: Int = 8)(implicit p: Paramet
lgSize = in.c.bits.size,
data = in.c.bits.data,
corrupt = in.c.bits.corrupt)._2
c_a.bits.user.lift(AMBAProt).foreach { x =>
x.fetch := false.B
x.secure := true.B
x.privileged := true.B
x.bufferable := true.B
x.modifiable := true.B
x.readalloc := true.B
x.writealloc := true.B
}

// Releases without Data succeed instantly
val c_d = Wire(in.d)
Expand Down